KR20010006946A - Active matrix array substrate and its manufacturing method - Google Patents

Abstract

PURPOSE: A method for producing an active matrix array substrate is provided to improve the production yield by preventing an electrostatic breakdown between scanning lines and data lines or between adjacent data lines in the production process. CONSTITUTION: An active matrix array substrate has active elements arranged in a matrix and a plurality of scanning lines(4) and data lines(5) to drive the active elements. Each scanning line(4) is connected through an inspection resistor(12) for the scanning lines to a common scanning bus(10), while each data line(5) is connected through an inspection resistor(13) for the data lines to a common data bus(11). Each data line(5) consists of a multilayered metal layer, and each of the inspection resistor(12) for scanning line and the inspection resistor(13) for the data line consists of the lowermost metal layer of the multilayered metal layer.

Description

ACTIVE MATRIX ARRAY SUBSTRATE AND ITS MANUFACTURING METHOD}

The present invention relates to active matrix array substrates used in the field of active matrix array substrates, in particular, to display panels employed in liquid crystal display devices used for information processing and the like and methods of manufacturing the same.

Liquid crystal display devices (LCDs) are widely used as image display devices for information devices including OA terminals and television sets. In particular, LCDs with high display performance, such as devices using thin film transistors (TFTs), use active array substrates in which multiple active elements are aligned.

Generally, such active matrix array substrates are inspected for electrical defects at their final fabrication stage. For this purpose, a test resistor is formed on the active matrix substrate. Japanese Laid-Open Patent No. H8-101397 discloses an active matrix array substrate on which a resistor is formed and a method of manufacturing the same.

Typically, as shown in FIG. 3, the pixel unit is composed of a pixel electrode 3 and a TFT 2. The plurality of pixel units are arranged in a matrix form. A plurality of scanning lines 4 and a plurality of data lines 5 for scanning each TFT are disposed between the pixel units. Each of the scan lines 4 is connected to the common scan bus 10 through a scan line test resistor 12 to enable electrical inspection. Each of the data lines 5 is connected to the common data bus 11 through a data line test resistor 13. The scan line input pad 6 and the data line input pad 8 are respectively disposed on the scan line 4 and the data line 5, respectively. These pads are used for electrical inspection and to input drive signals to scan lines and data lines after they are finally connected to external circuits (drive ICs). The common scan pad 14 and the common data pad 15 for inspection are respectively connected to the ends of the common scan bus 10 and the common data bus 11.

3 shows the steps of forming a metal layer to produce a scan line, processing a pattern of the scan line, a gate insulating layer, an a-Si (amorphous-Si) layer and a low resistive a-Si layer. Forming a branch layer, forming an a-Si island for the TFT by processing a pattern of a-Si layer / low resistance a-Si layer, creating a contact window on the gate insulating layer, and Forming a metal layer to produce a line, processing a pattern of data lines, etching the channel (by removing the exposed low resistance a-Si layer), forming a protective insulating layer; Shows a conventional active matrix array fabricated through processing a contact window on a protective insulating layer, forming an ITO layer for the pixel electrode, and processing a pattern of the pixel electrode.

Since the sheet resistance value is preferable, the scan line test resistor 12 and the data line test resistor 13 are formed using the ITO layer used to form the pixel electrode 3.

In each of the above steps, at least after the step of processing the pattern of the data lines, all data lines 5 and the common data bus 11 are always electrically connected so that the local abnormal voltage even if the data lines are charged during the process. It is important that the generation of) can be prevented.

An ITO resistor is formed between the data line 5 and the common data bus 11 in the final manufacturing stage of the array substrate. Therefore, the data line 5 and the common data bus 11 need to be electrically connected by some other means until the final stage. Thus, when an a-Si island for the TFT is created, the a-Si island connecting the data line 5 and the common data bus is also in the step of processing the pattern of the a-Si layer / low resistance a-Si layer. Is formed.

However, after the low resistance a-Si layer on its surface is removed during the step of etching the channel (by removing the exposed low resistance a-Si layer), the resistance of the a-Si island increases. This results in insufficient discharge of the electrostatic charge and reduction of the potential generated at the data line to the common data bus. In particular, when using dry etching for channel etching, as a result of the plasma use in dry etching, the data lines are filled to high levels causing serious problems.

It is an object of the present invention to provide an active matrix array substrate and a method of manufacturing the same, which eliminate the reduction in yield caused by electrostatic breakdown to yield satisfactory yields and enable electrical inspection.

The active matrix array of the present invention includes two or more active elements arranged in a matrix on a substrate, two or more scan lines for driving the active elements, two or more data lines for supplying image data to the active elements, and a common scan bus. And at least two scan line test resistors for connecting each of the scan lines to the common data bus, and at least two data line test resistors for connecting each of the data lines to the common data bus. Each data line and common data bus is comprised of a multilayer structure comprising a plurality of metal layers and each scan line test resistor and data line test resistor are constructed by removing at least the top layer of the multilayer structure.

This configuration prevents electrostatic breakdown between scan lines and data lines or neighboring data lines and enables the production of active matrix arrays with good yields. Each test resistor can also be constructed using only the bottom layer of a multilayer metal structure.

The active matrix array substrate of the present invention includes two or more drain electrodes made of the same material at the same level as each data line, a protective insulating layer covering each drain electrode and two or more pixel electrodes formed on the protective insulating layer. Each pixel electrode is connected to each drain electrode through a contact window provided on the protective insulating layer.

This configuration provides a high aperture ratio of the pixels in the active matrix array on the substrate.

The present invention provides an active matrix array substrate having a multilayer structure in which two or more data lines include an upper layer made of Al and a lower layer made of Cr, Ti, W, Mo, or Ta. This reduces parasitic resistance and achieves satisfactory picture quality with less flickering or cross talk in liquid crystal display devices.

The method of manufacturing the active matrix array of the present invention

(a) forming a plurality of active elements arranged in matrix form on the substrate surface;

(b) forming a plurality of scan lines and a common scan bus on the substrate, each scan line being connected to the common scan bus via a first temporary connection;

(c) a plurality of data lines for supplying image data to a plurality of active elements, a common data bus connected to the plurality of data lines, and a plurality of scan line bridges forming a second connection between each of the plurality of scan lines and the common scan bus. Forming a data line, a common data bus and a scan line bridge as a multi-layer structure consisting of a plurality of metal layers comprising an upper metal layer and a lower metal layer by patterning and depositing at least two metal layers; ,

(d) cutting each of the first temporary connections between each of the common scan bus and the scan line;

(e) a test resistor and a scan line and a common scan connecting each of the data line and the common data bus by removing one of the metal layers other than the bottom metal layer from a portion of each of the data lines adjacent to the common data bus and from each of the scan line bridges. Forming a test resistor connecting each of the buses.

This configuration prevents electrostatic breakdown between the scan line and the data line or adjacent data lines.

1 is a schematic partial plan view illustrating one point during a method process of manufacturing an active matrix array substrate according to a preferred embodiment of the present invention;

2A-2E show schematic partial plan views illustrating each step in a method of manufacturing an active matrix array substrate according to a preferred embodiment of the present invention;

3 is a circuit diagram of an active matrix array substrate of the present invention and prior art.

Explanation of symbols for the main parts of the drawings

1: pixel unit 2: TFT

3: pixel electrode 5: data line

6 scan line input pad 8 data line input pad

10: common scan bus 11: common data bus

12: scan line test resistance 13: data line test resistance

14 common scan pad 15 common data pad

20: gate electrode 21: a-Si island

22 contact window of the gate insulator layer 23 source electrode

24 drain electrode 25 scanning line bridge

An active matrix array substrate and a method for manufacturing the same according to a preferred embodiment of the present invention will be described below with reference to FIGS. 1, 2A to 2E, and FIG. 3. Like numbers refer to like parts in all figures. Reference numerals for each element arranged in the matrix are given only to the representative parts in this drawing, and other parts are omitted to avoid the drawing complexity due to cluttering.

The active matrix array substrate according to a preferred embodiment of the present invention has the same final circuit configuration as described in the prior art and shown in FIG. Referring next to FIG. 1, two TFTs 2 and pixel electrodes 3 of a plurality of TFTs and pixel electrodes are shown, each electrode TFT 2 in the form of a matrix on a glass substrate (not shown). Is connected to the drain electrode 24. Also shown are a scanning line 4 scanning the gate electrode of each TFT 2 and a data line 5 supplying image data to the source electrode 23 of each TFT 2. Each TFT 2 includes a gate electrode 20, an a-Si island 21, a source electrode 23 and a drain electrode 24. Each scan line 4 is connected to a common scan bus 10 via a scan line test resistor 12, and each data line 5 is connected to a common data bus 11 through a data line test resistor 13. do. Scan line input pads 6 are provided for each scan line 4 and data line input pads 8 are provided for each data line 5. The common scan pad 14 is provided on the common scan bus 10 and the common data pad 15 is connected to the common data bus 11. Electrical inspection is implemented by probes from external pads 6, 8, 14, 15.

The preferred embodiment of the present invention differs from the prior art in that the data line 5 is a multilayer metal conductor and the scan line test resistor 12 and the data line test resistor 13 have a multilayer metal structure instead of the conventional ITO layer. It is composed of a part of. A fabrication method for producing an active matrix array on a substrate according to a preferred embodiment of the present invention having such a multilayer metal conductor and resistance is described below with reference to FIGS. 2A-2E.

First, an AlZr alloy (Zr: extremely small 1%) layer having a thickness of 350 nm is formed on the glass substrate, and then, as shown in FIG. 2, the scan line 4, the TFT gate electrode 20, and the scan line input pad 6 are formed. Are etched to form the common scan bus 10 and the common scan pad 14. Preferably they are all formed simultaneously. The scan line 4 and the common scan pad 14 are connected to the temporary scan line connection path 4a. This temporary scan line connection path 4a is removed during subsequent processes, but in the meantime serves to protect the interior of the array from the formation of electrostatic charges. During the subsequent process step, the pad 4b is a pad which serves to connect the scan line bridge 25.

Next, three layers are formed on the entire surface using the chemical vapor deposition method (p-CVD method) supported by the plasma. The SiNx layer forms a TFT gate insulating layer. The a-Si layer forms a channel layer, and the low-resistance a-Si layer is formed to fix the contact between the TFT source and the drain. After formation of these layers, as shown in Fig. 2B, the a-Si layer and the low-resistance a-Si layer are etched in an island shape to form the a-Si island 21, which is the main component of the TFT. Next, as also shown in FIG. 2B, a portion of the gate insulating SiNx layer covering the temporary scan line connection path 4a and a portion of the SiNx layer on the upper portion of the scan line bridge pad 4b are removed to make the contact window 22. And a contact window of the gate insulating layer.

Next, a 100 nm thick Ti layer and a 300 nm thick Al layer are sequentially formed to form a multilayer metal layer. Subsequently, as shown in FIG. 2C, this multilayer metal layer includes a data line 5, a data line connection path 5 a, a source electrode 23, a data line input pad 8, and a common data bus 11. The common data pad 15, the drain electrode 24 and the scan line bridge 25 are dry etched to form simultaneously if desired. In this etching step, the temporary scan line connection channel 4a exposed through the contact window 22 of the gate insulating layer is removed.

The common data bus 11 and the data line 5 are subsequently connected by the data line connection path 5a which becomes the data line test resistor 13. Scan line bridge 25 is also processed to form scan line test resistor 12 thereafter. However, at this stage, even after the temporary scan line connection path 4a is removed, the scan line bridge 25 continues to connect to the scan line 4 and the common scan bus 10. Etching of the data line 5 and removal of the temporary scan line connection path 4a can be implemented in the same step. In the preferred embodiment of the present invention, the data line 5 and the temporary scan line connection path 4a are made of Al and are therefore etched simultaneously. However, even if the data line 5 and the temporary scan line connection path 4a are made of different materials, both may be etched by changing the etching gas or etching solution.

The low-resistance a-Si layer in the a-Si island 21 between the source electrode 23 and the drain electrode 24 is then removed to achieve the channel of the TFT 2 (Fig. 1).

The Al top layer on the part of the scan line bridge 25, the data line connection path 5a and the drain electrode 24 is subsequently removed so that only the Ti layer remains at the bottom. As shown in FIG. 2D, they become the scan line test resistor 12, the data line test resistor 13, and the drain contact electrode 24a. The Al layer on the drain electrode 24 is removed because it is desirable for the lower Ti layer to contact the ITO pixel electrode to be formed later at low resistance. The upper Al layer is used to reduce the resistance of the data line 5 to prevent any delay in the signal.

Next, a SiN _x layer is formed using the p-CVD method to create a protective insulating layer. Subsequently, as shown in FIG. 2E, the protective insulating layer on the scan line input pad 6, the data line input pad 8, the common scan pad 14, the common data pad 15, and the drain contact electrode 24a. Silver is removed to form contact windows 26 respectively through a protective insulating layer. After forming a 100 nm thick ITO layer on the entire surface, a pixel electrode 3 connected to the TFT drain contact electrode 24a through a contact window 26 on the protective insulating layer is formed, as shown in Fig. 2E. Likewise, the active matrix array substrate is completed.

As mentioned above, a preferred embodiment of the present invention relates to an active matrix array in which a transparent LCD uses ITO as its pixel electrode. If metals such as Al and Ag are used in place of ITO, the pixel electrode will also function as a reflector to obtain an active matrix array for reflective LCDs. In the case of reflective LCDs, since ITO is not used, the test resistance cannot be formed using conventional methods described in the prior art of the invention. Thus, the present invention demonstrates greater efficiency in active matrix arrays for reflective LCDs.

The pixel electrode may also be formed in the step before forming the scan line or the data line. In a preferred embodiment of the present invention, the pixel electrode is formed on the protective insulating layer to ensure the aperture ratio as high as possible.

In the preferred embodiment of the present invention, the scan line 4 and the common scan bus 10 are connected by the scan line bridge 25 during the step of forming the TFT channel by removing the low-resistance a-Si layer. The data line 5 and the common data bus 11 are connected by the data line connection path 5a. This prevents electrostatic breakdown from occurring. If an amorphous Si island is used for the connection instead of the data line connection path 5a as in the prior art, the resistance value of the island after removing the low-resistance a-Si layer is tens of millions of ohms. The multilayer structure of Ti and Al according to a preferred embodiment of the present invention has a resistance value of several hundred ohms. This prevents the formation of any damage due to the electrostatic charge caused by the plasma during the dry etching process. Electrical inspection requires the scan line test resistor 12 and data line test resistor 13 to be set at a few tens of ohms. These resistance levels can be obtained only by removing the upper Al layer and leaving high-resistance Ti on the scan line bridge 25 and the data line connection path 5a.

In the above description, the scan line 4 and the gate electrode 20 are made of Al—Zr alloy. Metals with high melting points such as Cr, Ta, etc. may also be used. Multilayer metal structures such as Ti / Al / Ti can also be used. In the case of LCDs with large display areas or very high display densities, Al system metals with low resistance are effective in preventing image quality damage caused by signal delay in the scanning line.

The data line 5 and the scan line bridge 25 are formed of a multilayer structure layer of Ti and Al according to a preferred embodiment of the present invention. However, any material having a sufficiently low resistance that does not delay the data signal may be used in the upper layer of the multilayer structure, and electrically enough to satisfy ITO and any material having a resistance value suitable for realizing each test resistance for inspection. Any material that contacts can be used in the underlying layer. The lower layer may be composed of a metal having a high melting point such as Cr, W, Mo or Ta, and the upper layer may be composed of an alloy of Al and one or more metals having a high melting point. The metal multilayer structure may have three or more layers, in which case each test test resistance is provided to these metal layers except the top layer. A preferred embodiment of the present invention uses a TFT as an active element. However, other non-linear two-terminal elements such as MIM can also be used.

The present invention provides a data line test resistor formed of the lowermost layers of a plurality of metal structure data lines, and a scan line test resistor composed of the same material as the bottom layer of at least two data lines and a common data bus respectively connected to two or more data lines. It includes a common scan bus, each connected to two or more scan lines.

The present invention has the effect of providing an active matrix array substrate and its manufacturing method which prevent electrostatic breakdown between each scan line and data line or adjacent data line to yield satisfactory yields and enable electrical inspection.

Claims (16)

In an active matrix array, A plurality of active elements arranged in a matrix on a substrate, A plurality of scan lines scanning the plurality of active elements, A plurality of data lines for supplying image data to the plurality of active elements; With a common scan bus, Common data bus, A plurality of scan line test resistors connecting each of the plurality of scan lines to the common scan bus; A plurality of data line test resistors connecting each of said data lines to said common data bus, Each of the data line and the common data bus comprises a composite multilayer structure having a top metal layer and a bottom metal layer; Each of the plurality of scan line test resistors and each of the plurality of data line test resistors comprise the multilayer structure without at least the top metal layer. The method of claim 1, And each of the plurality of scan line test resistors and each of the data line test resistors comprise only one metal layer that is the bottom metal layer. The method of claim 1, A plurality of drain electrodes formed simultaneously with each of the data lines using the same structure and material as the multilayered structure and material of the data line including the top and bottom layers; A protective insulating layer covering each of the drain electrodes; A plurality of pixel electrodes formed on the protective insulating layer; And each of the plurality of pixel electrodes is connected to each of the drain electrodes through a contact window provided in the protective insulating layer. The method of claim 3, wherein At least the top layer of the multilayer structure of each of the drain electrodes is removed at least in portions connected to each of the plurality of pixel electrodes. The method of claim 3, wherein And the plurality of pixel electrodes comprise ITO. The method of claim 3, wherein And said plurality of pixel electrodes comprise a metal selected from the group consisting of Al and Ag, said plurality of pixel electrodes reflecting incident radiation. The method of claim 1, And the plurality of active devices are thin film transistors. The method of claim 2, The multilayer structure includes an upper layer composed of Al and a lower layer composed of at least one metal selected from the group consisting of Cr, Ti, W, Mo and Ta. The method of claim 1, And each of the plurality of scan lines is an Al alloy. In the method of manufacturing an active matrix array, Ⓐ forming a plurality of active elements arranged in a matrix on the substrate surface; (B) forming a plurality of scan lines and a common scan bus on the substrate, each of which is connected to the common scan bus via a first temporary connection; A plurality of data lines for supplying image data to the plurality of active elements, a plurality of scan lines for forming a second connection between each of the plurality of scan lines and the common scan bus and the common data bus connected to the plurality of data lines Forming a bridge, the multilayer structure consisting of a plurality of metal layers comprising a top metal layer and a bottom metal layer, patterning and depositing at least two metal layers to form the data line, the common data bus, and the scan line bridge By doing-Wow, Ⓓ cutting each of the first temporary connections between each of the common scan bus and the scan line; A test resistor connecting each of the data line and the common data bus by removing one of the metal layers other than the bottom metal layer from each portion of the data line adjacent to the common data bus and from each of the scan line bridges; Forming a test resistor connecting each of the scan lines and the common scan bus. The method of claim 10, And said plurality of scan lines, scan buses and first temporary connections are formed simultaneously. The method of claim 11, And the patterning in step ⓒ occurs simultaneously for all data lines, common data buses, and scan line bridges. The method of claim 10, And the step ⓓ of forming each of the plurality of data lines and the cutting of each of the first temporary connections are performed in a single step. The method of claim 10, In said step ⓔ a metal layer is removed to form said test resistance. The method of claim 10, Wherein the plurality of active devices are thin film transistors. The method of claim 14, Wherein said multilayer structure comprises said top layer of Al and said bottom layer of at least one metal selected from the group consisting of Cr, Ti, W, Mo, and Ta.