TWI240134B - Thin film transistor liquid crystal display and method of making the same - Google Patents

Abstract

A thin film transistor liquid crystal display and method of making the same. The method comprises the steps as follow. A scan line and a gate are formed on a substrate, and a gate insulating (GI) layer and an amorphous silicon layer are then formed on the substrate. Portions of the amorphous silicon layer are removed, and a metal layer is formed on the substrate thereafter. By performing a photo-etching-process (PEP), a source and a drain, as well as a dummy signal line and a signal line, are formed on the substrate. A passivation layer with at least one via hole is then formed on the substrate. Finally, a transparent conductive layer is formed to fill the via hole, and unnecessary portions of the transparent conductive layer are removed. The thin film transistor liquid crystal display comprises a substrate; a plurality of transistors each comprising a gate, a source and a drain; a plurality of scan lines, a plurality of data lines; and a plurality of dummy data lines.

Description

1240134 Amendment_Case No. 92101074 V. Description of the invention (1) Technical field to which the invention belongs Benlaming provides a thin film transistor liquid crystal display (translst〇r liQU1d crystal dispUy, / η lcd), especially a method to avoid gate / Source short-circuit (eh ", = 〇rt, GS-short) thin-film transistor liquid crystal display manufacturing method0 Previous technology With the booming development of the electronic Gongxun industry, liquid crystal displays (丨 丨 叩 id crystal display, LCD) The application scope and market demand are also continuously expanding 'from small products' such as electronic sphygmomanometers to portable information products such as personal digital assistants (PDAs) and notebook computers (notebOOk), so that it is very likely in the future Commercial large-screen displays can be seen in the wide use of liquid crystal displays. Because the structure of the liquid crystal display is very thin, short, and has the advantages of low power consumption and no radiation pollution, it is widely used in the above-mentioned people's livelihood and Information products: Basically, thin-film transistor liquid crystal displays include a transparent substrate. There are many thin film transistors arranged in small arrays, pixel electrodes, scan or gate lines and data or signal lines orthogonal to each other, and a filter plate (color filter), and a liquid crystal material filled between the transparent substrate and the filter plate, and matched with

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(5) Appropriate capacitors, connection pads, etc. produce rich and bright images. Iron II, to drive liquid crystal pixels, the scanner, the scanning line and the signal line g, for thin-film transistor liquid crystal display process or man-made factors, and lead = two spoons are often easy because of unexpected line defects. The display system of the point-and-resistance system of the display products of night and day is displayed on the transparent panel, etc., as usual, the line is made with the intention of referring to 10-10. Scan the layout of a thin-film electricity. When you are familiar with glass substrates, each element of the surface electrode displays' therefore, the drawing is shown in the drawing and the view in Figure 2. The crystal is technically covered and swept on the 11-shaped plate, and the drawing is in the same picture with thin film telecommunications. Lines A to Figures A to E are for making and scanning lines and signal lines using yellow light to form a TFT LCD system. 10 contains a variety of different element lines, signal lines, and capacitors with a certain space. As well as the cross-section crystals, pixel electrodes, and parent parts of the top views IIA to IIE.

Fig. 1 is a conventional single TFT LCD. Fig. 1 is a cross-section of a TFT LCD interleaving process (p E p). Because the actual components, such as the thin-film electrical and connection pad configuration, will not be shown on the map and the top view, the scanning lines and signals are indicated. As shown in Figures 1 and 2A through 2E, the surface of the glass substrate (not shown in Figure 1) contains at least one thin film transistor (TFT) 44 and a scanning line (s ^ an line). 18 and a signal line (signal Hne) 36. Among them, the thin-film transistor 44 is arranged in the transistor region 12 on the surface of the slope substrate, and the scanning lines 18 and signal lines 36 are staggered perpendicularly to the surface of the glass substrate 11 (cr0ss 0verM 14). on.

Page 8 1240134 ---_-- year, month, and day of revision _ five, send _㈣⑶: " ~~ " The source 32 of the thin film transistor 44 is connected to the signal line 36, the thin film transistor 4 4 The drain electrode 3 4 is connected to a pixel electrode 42 through a via hole (v 丨 ah 〇1 e) 4 1. "The conventional method for making a thin film transistor liquid crystal display is to first deposit a first metal layer (not shown) on the surface of the glass substrate 11 and then proceed with the process of kappa light and money engraving (pep -1), so that The σHypermonium layer on the surface of the glass substrate 11 forms an interelectrode 16 and a scan line 18 passing through the staggered area ΐ4, as shown in FIG. 2A. Among them, the gate electrode 6 is connected to the scan line. 18, and the first metal layer (not shown in the figure) is a single layer * metal layer or a metal layer with more than one or two layers. If it is the former, the material constituting the second metal layer (not shown in the figure) Contains tungsten, chromium, molybdenum (Mo) or tungsten-containing molybdenum alloy (Mow). In the latter case, the material constituting the first metal layer (not + shown in the figure) contains chromium (Cr) and is covered by Aluminum (Al), > Molybdenum on aluminum, Molybdenum on aluminum alloy (A1Nd) containing “(Nd), Molybdenum alloy containing tungsten on aluminum or Molybdenum alloy containing tungsten on On titanium (Nd) aluminum alloy (AiNd), the material combinations of the two metal layers listed above are just some common examples. In the above, the materials constituting the two metal layers may be chromium (Cr), aluminum (A1), molybdenum (Mo), an alloy (AINd) containing pd), and a molybdenum alloy (Mw) containing tungsten 0). In any combination, in one step, the first metal layer is a three-layer metal structure, and the material constituting the first metal layer includes Mo / A1 / Mo and

Ti / Al / Ti. After completing the first yellow light and etching process,

Page 9 1240134-_ No. 92101074 _ _ year month and month correction __ 5. Description of the invention (4) A gate insuiator 22 and a semiconductor layer are sequentially deposited on the board 1 1 in sequence. twenty four. The inter-electrode insulation layer 22 is a single dielectric layer or a composite dielectric layer. Its material is, for example, silicon oxide (S i 〇χ) or silicon nitride. (S i Ny) or oxynitride (SiON). The semiconductor layer 24 is also referred to as an active layer. It is a hydrogenated amorphous silicon layer (α-Si: H layer), and is used when the thin film transistor 44 is turned on. Channel (channel). The material of the semiconductor layer 24 is, for example, a polycrystalite layer (p 0 1 y s 丨 1 丨 c 〇 η 1 a y e Γ).

After the l1 edge, a etching stop layer (not shown in the figure) is fully deposited on the glass substrate 11 and its material is, for example, silicon nitride. In fact, the gate insulating layer 2 2, the semiconductor layer 2 4 And the etch stop layer (not shown in FIG. 1) is made by a continuous plasma enhanced chemical vapor deposition (CVD) process in the same reaction chamber (Chamber). Growing up

to make. A second yellow light and etching process (PEP-2) is performed to form a stop pattern 26 of the stop pattern (not shown in the figure) above the gate electrode 16 to avoid The semiconductor layer 24 is eroded by the subsequent etching process, and the etch stop layer (not shown in the figure) is not retained in the staggered region 14 at all, as shown in FIG. 2 β. As shown in FIG. 2C, a doped semiconductor layer (n +, not shown in the figure) is then deposited on the semiconductor layer 24 and the etch stop pattern 26 over the entire surface. The doped semiconductor layer (not shown in FIG. (In the figure) usually by blending

Page 10 1240134 92101074

V. Description of the invention (5) Doped phosphorus (phOsphOr) made of amorphous silicon. Then a second metal layer (not shown in the figure) is deposited on the doped semiconductor layer (not shown: shown in the figure). Middle), and a third yellow light and etching process (pEp-3) is performed to define the pattern of the second metal layer, (not shown in the figure), the doped semiconductor layer (not shown in the figure), and the semiconductor layer 24 In order to form the source electrode 32 and the drain electrode 34 of the thin-film electric solar element in the transistor region 12, and simultaneously form a signal line 36 passing through the interlaced region 14 4. Spring second metal layer ( (Not shown in the figure) is one. A single metal layer or one or two or more metal layers. For the former, the material constituting the second metal layer includes tungsten (W), chromium (cr), and Molybdenum (Μα). In the latter case, the material constituting the second metal layer (not shown) includes chromium (Cr) over aluminum (A1), molybdenum over aluminum, and molybdenum over beryllium (Nd ) On aluminum alloy (Al / d), molybdenum alloy containing tungsten is covered on aluminum or molybdenum alloy containing tungsten is covered on Is alloy (AINd) containing “(Nd) The material combinations of the two metal layers listed above are just some common examples. In fact, the materials constituting the two metal layers can be chromium (C r), aluminum (a 1), molybdenum (Mo), and titanium. Any combination of (Nd) aluminum alloy (AINd) and tungsten (f) -containing molybdenum alloy (MoW). Further, the second metal layer is a three-layer metal structure, and the material constituting the second metal layer includes There are Mo / a 1 / Mo and T i / A 1 / T i. At the same time, the doped semiconductor layer (not shown in the figure) is used to promote the second metal layer (not shown in the figure) to perform the semiconductor layer 2 4 The ability of ohmic contact to avoid various problems arising when the second metal layer (not shown in the figure) with a very different work functin is in direct contact with the semiconductor layer 24.

Page 11 of 1240134 _Case No. 921Q1074_ Year Month Amendment _ V. Description of the invention (6) Subsequently, a protective layer 3 8 is formed on the glass substrate 11 1, and the material is, for example, silicon oxide or silicon nitride, and a first The four yellow light and etching process (PEP-4) removes a part of the protective layer 38 above the drain 34 of the thin film transistor 44 to form a via hole 4 in the protective layer 3 all the way to the surface of the drain 3 4 1, and exposed part of the pole 3 3, as shown in Figure 2 D households.

Finally, a transparent conductive layer (not shown in the figure) composed of indium tin oxide (ITO) or indium zinc oxide (IZO) is formed on the glass substrate 11 (see above). The fifth yellow light and etching process (PEP-5) makes the transparent conductive layer form a pixel electrode 42 electrically connected to the drain electrode 34 of the thin film transistor 44 to complete the production of the thin film transistor 44. At this time, as shown in FIG. 2E, only the semiconductor layer 24 and the gate insulation layer 2 2 are separated between the signal line 36 and the scanning line 18 in the staggered area 14 covered by the protective layer 38. .

However, the conventional method for manufacturing a thin-film transistor liquid crystal display does not provide any repair circuit. After one process after another, the thin-film transistor liquid crystal display is very easy to affect the production yield due to various defects. And, as the size of the LCD panels produced becomes larger and larger, such problems will become more serious. In particular, the staggered area 14 passing through the signal line 36 and the scanning line 18 at the same time is often caused by the shape of the scanning line 18 in the lower layer being not good enough, the undercut of the scanning line 18 or the gate line (under cut) phenomenon, metal ejection

1240134 on page 12 _Case No. 92101074 Rev. _15. Explanation of invention (7) eruption) phenomenon and unexpected pollution particles (P artic 1 e) in semiconductor layer 24 and gate insulating layer 22 Factors cause a “gate-signal short” phenomenon of the scan lines 18 and the signal lines 36 after the second metal layer is deposited. Therefore, how to overcome this problem to maintain a certain production yield has become an important issue when manufacturing liquid crystal displays. SUMMARY OF THE INVENTION Therefore, the main object of the present invention is to provide a method for manufacturing a thin film transistor liquid crystal display (TFT LCD), so as to solve the above-mentioned conventional manufacturing method of a gate / source short, GS-short). In a preferred embodiment of the present invention, a substrate for producing a thin film transistor is provided on the substrate in a display state including at least one pixel sheep (sub-P i X e 1) region, and one for forming a thin film transistor. A transistor (t rans is tor) region of the crystal (τ F τ) and at least one wire staggered region. First, a first metal layer is deposited on the substrate, and then a first photo-etching process (PEP) is performed on the first metal layer to form a pass-through The scan lines (scan ^ e) of the staggered area form a gate of the thin film transistor in the transistor region. A gate insulation (ga te in = ula ^ lng, Gi) layer and an amorphous stone (am〇rph〇us siHcOn) ^ 6 doped semiconductor layer ( n + layer). Followed by a first

Page 13 1240134 _Case No. 92101074_Year Month and Day_ί ± ^ _ V. Description of the Invention (8)

Two yellow light and etching processes are performed to remove part of the amorphous silicon layer and the doped semiconductor layer, and then a second metal layer is formed on the substrate. After a third yellow light and etching process is performed on the second metal layer, a source and a drain of the thin film transistor are formed in the transistor region, and a dummy data line is formed on the surface of the substrate. And a signal line (data 1 ine) passing through the staggered area, and the spare signal line is electrically connected to the source and the signal line. A passivation layer is then formed on the substrate, and a fourth yellow light and etching process is performed on the passivation layer to form at least one via hole in the passivation layer. A transparent conductive layer is then formed on the substrate, and the via hole is filled, and then a fifth yellow light and etching process is performed to remove the transparent conductive layer around the via hole and outside the sub-pixel unit area. Floor. Finally, a circuit test is performed. When it is detected that the signal line is electrostatically damaged at the scan line, the signal line is cut at the scan line to make the signal line conductive through the backup signal line; otherwise, Cut the spare signal cable.

Since the manufacturing method of the present invention forms the backup signal line synchronously when the signal line is formed, if the gate / source short circuit of the thin film transistor is found during the subsequent circuit test, the damage can be truncated and damaged The signal line is conducted with the backup signal line to improve the production yield of the thin film transistor liquid crystal display, thereby reducing the production cost.

Page 14 1240134-Case No. 92101074_ Year Month Chromium π:

V. Description of the invention (9) Please refer to FIG. 3, which is a top view of a substrate 50, which is one of the manufacturing methods of a thin film transistor liquid crystal display (TFT LCD) used in the present invention. As shown in FIG. 3, the material of the substrate 50 is, for example, a glass substrate, a quartz substrate, or a plastic substrate, and the substrate 50 includes at least one pixel unit a (sub-pixel) region 52, and a thin film transistor is formed. (Tft) transistor region 54 and at least one wire interleaving region 56. First, please refer to FIGS. 4 to 8, FIGS. 4 to 7 are manufacturing methods of the thin film transistor liquid crystal display of the present invention, and FIG. 8 is a top view of the layout of the single thin film transistor liquid crystal display system of the present invention. And b — b 'method schematic diagram. As shown in FIG. 4, a first metal layer (not shown) is first deposited on the substrate 50, and its material is, for example, tungsten (W), chromium (Cr), | mesh (M0), titanium (Ti) Or I (A 1), and then a first photo-etching-process (PEP) is performed on the first metal layer to form the first metal layer remaining on the surface of the substrate 50 A scan line 58 passing through the staggered area 56 forms a gate 60 of one of the thin film transistors in the transistor area 54, and the scan line 58 is connected to the gate 60 series. As shown in FIG. 5, a gate insulating (GI) layer 62, an amorphous silicon (AMOS) layer 64, and a doped layer (64) are sequentially formed on the gate 60. doped) semiconductor layer 66 (n +

Page 15 1240134 __Case No. 92101074 R Amendment_ V. Description of the invention (10) 1 ayer). The t gate insulation layer 62 is a single gate insulation layer or a composite (compos i te) composed of silicon oxide (Si OX), silicon nitride (Si Ny), or silicon oxynitride (Si ON). ) The gate insulating layer is formed by performing a p 1 asmaenhanced chemical vapor deposition (PECVD) process. As shown in FIG. 6, a portion of the amorphous silicon layer 64 and the doped semiconductor layer 66 is subsequently removed by performing a second saccharine and etching process, and a substrate made of tungsten, chromium, A second metal layer (not shown) composed of molybdenum (M0), titanium (τ i), or aluminum. Then, a third yellow light and etching process is performed on the second metal layer, so that the remaining second metal layer forms a source 68 and a drain 7 of the thin film transistor in the transistor region 54. At the same time, a dummy data line 72 (see Fig. 8) is formed on the surface of the substrate 50 and a signal line 74 (data 1 ine) passes through the interleaved area 56, and the spare signal line 72 It is directly connected to the source 68 and the signal line 7 4. As shown in FIG. 7, a passivating layer 76 made of silicon oxide or nitride nitride is then formed on the substrate 50, and a first passivation layer 76 is formed in the transistor region 54. Four yellow light and etching processes to form at least one via hole 78 in the protective layer 76 in the transistor region 54 and finally to form an indium tin oxide (IT0) or It is copper zinc oxide (IZO)

Page 16 1240134 Month Day Amendment

__Case No. 92101074 V. Description of the invention (11) The transparent conductive layer 80 is formed and fills the interstitial hole 78, and then by performing the fifth yellow light and etching process, the interstitial hole 7 8 is removed and the The transparent conductive layer 80 outside the pixel unit region 52 is shown in FIG. 8 at this time. After completing the above processes, the present invention may further perform a circuit test including at least an array test or an optical inspection (AO I) to test whether the thin film transistor is A gate / source short (GS-short) phenomenon occurs. When testing through this circuit to detect defects such as electrostatic damage near the intersection of signal line 7 4 and scanning line 5 8 (that is, the conductor staggered area 5 6), the laser will be used to close the signal near the intersection. The line 7 4 is cut off, so that the signal of the signal line 7 4 is transmitted to the source 68 through the backup signal line 7 2 and the signal line 7 4 across the wire interleaving area 5 6; otherwise, when the backup signal line 7 2 is detected When a defect such as electrostatic damage occurs, 'the spare signal line 7 2 is cut off' so that the circuit is guided through the signal line 7 4. It is worth noting that the main purpose of the present invention is to connect the signal line 7 4 through the wire interleaving area 5 6 At the end, at least one backup signal line 7 2 electrically connected to the source 68 and the signal line 74 is formed, and the source 68, the signal line 74, and the backup signal line 72 are formed into a directly connected loop. A repair circuit (repair circuit) is formed to perform laser repair when defects such as a gate / source short (GS-short) are detected. Therefore, the signal wires 7 4 at both ends of the conductor staggered area 5 6 have

Page 17 1240134 _Case No. 92101074_Year Month and Date__ V. Description of the Invention (12) Source 6 The 8-phase electrical connection circuit structure to facilitate repair methods should all be equal changes made within the scope of the patent application of the present invention . In addition, when it is detected that the signal line 7 4 can operate normally, it is not necessary to cut off the spare signal line 7 2.

Compared with the conventional technology, the manufacturing method of the present invention forms the backup signal line 72 simultaneously when the signal line 7 4 is formed. Therefore, it is found that the shape of the scanning line 5 8 in the lower layer is not good enough in the subsequent test of the circuit. , Scan line 5 8 or gate 1 60 undercut (gate 1 ine) undercut, metal erupt i on phenomenon and amorphous stone layer 64 and gate insulation layer 62 There are factors such as unexpected part icles in the film. When the gate / source short circuit occurs in the thin film transistor, the damaged signal line 7 4 can be cut off and the spare signal line 7 2 can be used for conduction. In order to improve the production yield of the thin film transistor liquid crystal display, thereby reducing the production cost. The above are only the preferred embodiments of the present invention. Any equivalent changes and modifications made in accordance with the scope of the patent application for the present invention shall fall within the scope of the patent for the present invention.

Page 18 1240134 _Case No. 92101074_Year Month Day__ Brief Description of the Drawings Brief Description of the Drawings: Figure 1 is a top view of the layout of a conventional single thin film liquid crystal display system. Figures 2A to 2E are schematic cross-sectional views of the thin film transistor and the interlaced portion of the scanning line and the signal line in the thin film transistor liquid crystal display system of Figure 1. Fig. 3 is a top view of a substrate used in a method for manufacturing a thin film transistor liquid crystal display of the present invention. FIG. 4 to FIG. 7 are schematic diagrams of a method of manufacturing a thin film transistor liquid crystal display according to the present invention at the a-a 'axis and b-b' axis in FIG. FIG. 8 is a top view of the layout of a single thin-film transistor liquid crystal display system of the present invention. Symbol description of the icon:

Page 19 10 TFT LCD system 11 Glass substrate 12 Transistor area 14 Staggered 16 Gate electrode 18 Scan line 22 Gate insulating layer 24 Semiconductor layer 26 Etch stop pattern 32 Source 34 Drain 36 Signal line 38 Protective layer 41 Interlayer Hole 42 Pixel electrode 44 Thin film transistor 1240134 _ Case No. 92101074_ Year, month, and day correction diagrams Simple description 50 Substrate 52 Pixel unit area 54 Transistor area 56 Wire staggered area 58 Scan line 60 Gate 62 Gate insulation 64 Silicon layer 66 Doped semiconductor layer 68 Source 70 Drain 72 Spare signal line 74 Signal line 7 6 Protective layer 78 Via hole 80 Transparent conductive layer

Page 20

Claims (1)

^ Perform a fourth yellow light engraving process on the protective layer to form at least one via hole in the protective layer; form a transparent conductive layer on the substrate and fill the interlayer Holes; and, performing a fifth yellow light and etching process to remove the transparent conductive layer around the via hole and outside the sub-pixel unit area. 1. The manufacturing method according to item 1 of the scope of patent application, wherein the substrate is a glass substrate, a quartz substrate or a plastic substrate. 1 · -The manufacturing method according to item 1 of the scope of patent application, wherein the first and the =: metal layers are both a single-layer metal structure, and the material constituting the first and the one metal layer contains tungsten (w ), Chromium (Cr), copper (Cu), or molybdenum C Mo) 〇i · As in the manufacturing method of the scope of the first patent application, wherein the first and the f, the metal layer is a two-layer metal structure And the materials constituting the first and the J-1 metallized layer include chromium (Cr) covered on the inscription (A1), key (M0) box on Shao (A1), and molybdenum (Mo) covered with (Nd) aluminum alloy (AINd), molybdenum alloy (MoW) containing tungsten (W) is covered on the inscription (A1), or rhenium alloy (Mow) containing tungsten (w) is covered on Aluminum alloy (A1Nd). f _ The manufacturing method of item 1 in the scope of patent application, wherein the first and the second metal layers are both a three-layer metal structure and constitute the first and the second metal layers. 1240134 Case No. 92101074 Date of Amendment VI. Scope of Patent Application The material of the second metal layer includes Μο / Α1 / Μο and Ti / Al / Ti. 6. The manufacturing method according to item 1 of the scope of patent application, wherein the gate insulating layer comprises silicon oxide (Si 0x), silicon nitride (Si Ny) or silicon oxynitride (SiON), In addition, the protective layer includes oxide stone nitride or nitride stone. 7. The manufacturing method according to item 6 of the patent application, wherein the gate insulating layer is formed by performing a plasma enhanced chemical vapor deposition (PECVD) process. 8. The manufacturing method according to item 1 of the scope of patent application, wherein the material of the transparent conductive layer is indium tin oxide (IT0) or indium zinc oxide (IZ0) ° 9. If patent is applied The manufacturing method of the first item in the scope further includes a circuit test 'for detecting the gate / source short circuit of the film transistor. (gate / source short, GS — short), when it is detected that the tfl wire is electrostatically damaged near the wrong parent wire area, then the signal line near the wire staggered area is cut to make the signal of the signal line Conducted through the backup signal line; when static damage is detected on the backup signal line through the circuit test, the backup signal line is cut off. Page 23 1240134 _Case No. 92101074_year month_i ± i-_ VI. Patent application scope 10. For the manufacturing method of item 9 of the patent application scope, the circuit test includes an array test or An optical test (AO I) o 1 1. A method for manufacturing a thin film transistor liquid crystal display that avoids a gate / source short circuit, the manufacturing method includes the following steps: a substrate is provided, and the substrate includes At least one pixel unit region, a transistor region for forming a thin film transistor, and at least one wire interleaving region; Depositing a first metal layer on the substrate; performing a first yellow light and money engraving process on the first metal layer to form a scan line passing through the wire staggered area on the substrate surface, and in the transistor area A gate electrode of the rhenium film transistor is formed therein, and a gate insulating layer, an amorphous silicon layer, and a doped semiconductor layer (n + layer) are sequentially formed on the gate electrode; a second yellow light is performed; An etching process to remove a part of the amorphous silicon layer and the doped semiconductor layer; forming a second metal layer on the substrate; A third yellow light and etching process is performed on the second metal layer to form a source electrode and a drain electrode of the thin film transistor in the transistor region, and a backup signal line and a lead wire are formed on the substrate surface. A signal line in the staggered area, and the spare signal line is electrically connected to the source electrode and the signal line; forming a protective layer on the substrate; Page 24 1240134 _Case No. 92101074_ Revised Year of the Year_ 6. The scope of the patent application is to apply a fourth yellow light and etching process to the protective layer to form at least one via hole in the protective layer; and form on the substrate A transparent conductive layer and filling the via hole; performing a fifth yellow light and etching process to remove the transparent conductive layer around the via hole and outside the sub-pixel unit area; and performing a circuit test; Wherein, when it is detected that the signal line is damaged near the conductor staggered area, the signal line near the conductor staggered area is cut off, so that the signal of the signal line is conducted through the spare signal line. When static electricity damage is detected on the spare signal line through the circuit test, the spare signal line is cut off. · 1 2. The manufacturing method according to item 11 of the scope of patent application, wherein the substrate comprises a glass substrate, a quartz substrate or a plastic substrate. 13 3. The manufacturing method according to item 11 of the scope of patent application, wherein the first and the second metal layers are both a single-layer metal structure, and the material constituting the first and the second metal layers includes tungsten (W), chromium (Cr), copper (Cu) or key (Μ 〇) 〇 14. The manufacturing method according to item 11 of the scope of patent application, wherein the first and the second metal layers are each a two-layer metal structure, and the material constituting the first and the second metal layers contains chromium (C r) on aluminum (A 1), molybdenum (Μ 〇) on the inscription (A 1), thorium (Μ 〇) on a Sau alloy containing beryllium (N d) Page 25 1240134 Case No. 92101074 Amendment VI. On the scope of patent application (AINd), molybdenum alloy (MoW) containing tungsten (W) is covered on aluminum (A1). Molybdenum alloy (M) containing tungsten (W). (W) Covered with AINd. ^ 1 5 · As for the manufacturing method of item 丨 丨 in the scope of patent application, i branch ί Ϊ f is a three-layer metal structure, and the material constituting the first to the third layer contains M0 / A1 / Ma ^ Ti / Ai / T 卜-1 6 · If the edge range of the patent application is a single idler insulation layer 'and the gate electrode is Si Ny or nitrogen oxide oxide 17 · If the edge range of the patent application is By carrying out-^ 18. If the scope of patent application includes silicon oxide or nitrogen 19 · If the scope of patent application includes electrical layer system, which contains indium oxide 20 · If the scope of patent application scope includes-Array Test No. 11 The manufacturing method, wherein the gate insulation layer or the first composite (C0m Posite) gate edge layer comprises silicon oxide (Si0x), nitride (Si0N) 〇 manufacturing of item 16 The method wherein the gate insulation is enhanced by a chemical vapor deposition process. The manufacturing method according to item 11, wherein the protective layer is a fossil maggot. The manufacturing method of item 11, wherein the transparent tin conductor is indium zinc oxide. ^ The manufacturing method of item 11, wherein the circuit test or an optical test. Page 1212134