TW533510B - Production method of silicon mirror wafer - Google Patents

Production method of silicon mirror wafer Download PDF

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TW533510B
TW533510B TW090109662A TW90109662A TW533510B TW 533510 B TW533510 B TW 533510B TW 090109662 A TW090109662 A TW 090109662A TW 90109662 A TW90109662 A TW 90109662A TW 533510 B TW533510 B TW 533510B
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wafer
silicon
mirror
roughness
heat treatment
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Shoji Akiyama
Norihiro Kobayashi
Yuichi Matsumoto
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Shinetsu Handotai Co Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H01L21/3247Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering for altering the shape, e.g. smoothing the surface
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B82NANOTECHNOLOGY
    • B82YSPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y15/00Nanotechnology for interacting, sensing or actuating, e.g. quantum dots as markers in protein assays or molecular motors

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  • Crystallography & Structural Chemistry (AREA)
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  • Crystals, And After-Treatments Of Crystals (AREA)

Abstract

The invented production method of silicon mirror wafer is characterized that a mirror-polished CZ silicon wafer having an interstitial oxygen concentration below 16 ppma is heat-treated in an atmosphere of hydrogen, argon or a mixer of these gases so that the micro-roughness of the silicon wafer is up to 1.00 nm in terms of a 2 mum-square P-V value measured by an atomic force microscope, whereby providing a simple method for producing a silicon mirror wafer, capable of reducing grown-in defects in the vicinity of the surface of a CZ silicon wafer without sacrifice in micro-roughness and haze on the surface thereof.

Description

533510 A7 B7__ 五、發明説明(1 ) 本發明係有關對C Z矽晶圓作熱處理(退火)而製作 之矽鏡面晶圓之製造方法。 (請先閲讀背面之注意事項再填寫本頁) 先行技術 以柴式法(C Z法)製作之C Z矽晶圓,已知有源自 日日體之顆粒C〇P及氧析出物%之所g胃長入(Grown-in)缺 陷的結晶缺陷之存在,其乃引起氧化膜耐壓劣化、配線斷 線的原因之一,可係所製作之元件良率下降的主因。 近年來,消除該晶圓表面附近之長入缺陷的方法,盛 行在氫氣環境或氟氣環境中作熱處理之方法。然而,若對 鏡面硏磨晶圓作此等退火,則晶圓表面附近之長入缺陷雖 可減少或消除,另一方面,也已知有晶圓表面(鏡面硏磨 面)之局部粗度(微粗度)、長週期之粗度(霧度)的惡 化。如此之微粗度、霧度已知會對氧化膜耐壓及Μ 0 S電 晶體之氧化膜直接下方的載子之移動度造成影響(參考J. Appl. Phys. 79(2),1 5 January,1 996, P. 1 1 )。 經濟部智慧財產苟Μ工消费合作社印製 又,因退火而霧度惡化,則有難以測定附著於晶圓表 面之顆粒的弊病。此乃由於目前所用之顆粒計數器’係用 雷射光同時測定顆粒及霧度之故,霧度若高則與顆粒之信 號難以分離。 爲抑制如此的退火後產生於晶圓表面之霧度’其技術 有將供作退火之矽晶圓的面方位限定於(1 0 0 )起的特 定偏向角度(偏角)範圍內之提議(參考曰本專利特開平 5 — 1 5 2 1 7 9號、特開平8 — 3 2 1 4 4 3號公報) 本紙張尺度適用中國國家標準(CNS ) Α4規格(210X 297公釐) -4- 533510 A7 _B7 五、發明説明(2 ) 。然而,如此之方法,因在從矽晶棒切片成晶圓時必須嚴 密管控晶圓的表面方位,末必可謂簡便之方法。 (請先閲讀背面之注意事項再填寫本頁) 目前爲止,元件特性多僅矚目於氧化膜耐壓,此外, 今後當MO S元件之積體度更爲提升時,可以預見其附帶 的載子移動度之提升將成爲重要項目。 因此,用以製作元件之晶圓,不僅長入缺陷之減少, 微粗度、霧度的降低亦屬必要。爲此,對於可藉退火減少 長入缺陷,且無微粗度、霧度之劣化的退火方法有所期待 發明之揭示 本發明乃爲滿足如此之期待而完成,其目的在以極爲 簡便之方法供作至少不使微粗度、霧度惡化,可減少C Z 單晶晶圓表面附近之長入缺陷的砂鏡面晶圓之製造方、法。 經濟部智慧財/i^a(工消f合作社印製 爲達上述目的,本發明之矽鏡面晶圓的製造方法,乃 對晶格間氧濃度在1 6 p p m a以下之經鏡面硏磨的c Z 石夕晶圓,在氫、氬或其混合氣體環境下作熱處理,上述石夕 晶圓之微粗度成爲,以原子力顯微鏡測定的2微米見方之 P - V値在1 · 〇〇奈米以下爲其特徵的砂鏡面晶圓之製 造方法。 如此,選用晶格間氧濃度在1 6 p p m a (日本電;子· 工業振興協會(J[ E I D A )規格)以下者作爲施以退火 之經鏡面硏磨C Z矽晶圓作熱處理,可使矽晶圓之微粗g 成爲以原子力顯微鏡測定的2微米見方之P〜V i[g # 本紙張尺度適用中國國家標準(CNS ) A4規格(210X 297公釐) -5- 533510 A7 B7 五、發明説明(3 ) 1 . 〇 0奈米以下’無晶圓表面粗度之惡化而減少或消除 長入缺陷。 (請先閲讀背面之注意事項再填寫本頁) 此時,熱處理溫度係以1 1 0 0 °C至1 3 0 0 °C爲佳 。此乃因不足1 1 〇 〇 °c則無法充分減少長入缺陷,以及 ,超過1 3 0 0°c時有熱處理中之晶圓遭重金屬污染及熱 處理爐的耐久性之疑慮等理由。 如此,根據本發明,可用極其簡便之方法製得無晶圓 表面之微粗度、霧度之惡化,而晶圓表面附近之長入缺陷 減少的C Z矽鏡面晶圓。特別是,本發明之矽晶圓的微粗 度可達,以原子力顯微鏡測定之2微米見方的P — v値在 0 0奈米以下。並且不會產生晶圓表面粗度惡化,附著 圚表面的顆粒之測定困難之類的弊病。 、' 、-V、' \f 圖面之簡單說明 經濟部智慧財產^員工消費合作社印t 第1圖係呈示晶格間氧濃度與表面粗度之關係的圖, (a)示spl的與霧度之關係,(b)示LS — 6〇30之與霧度的關係,(〇:)示八?-之與?一¥値 的關係。 發明之最佳實施形態 以下詳細明本發明。 本發明人等對爲減少C Z矽晶圓之長入缺陷所施行之 退火所發生的鏡面硏磨面之粗化(微粗度、霧度之劣化) ’除以往之限制偏角的方法以外,爲以晶圓本身之特性控 本紙張尺度適用中國國家標準(CNS ) A4規格(210X 297公釐) -6 - 533510 A7 _____ B7 五、發明説明(4 ) 制找出改善方法,進行了精心探討。 (請先閲讀背面之注意事項再填寫本頁) 因而,著眼於一般已知係退火後晶圓表面粗化之原因 的以下事實。其乃因進行退火的原料氣體中含極少量之雜 質的氧、水分,熱處理步驟中從反應管之爐口卷入外氣中 的氧、水分,於晶圓表面形成氧化膜,該氧化膜與矽反應 侵蝕晶圓表面,結果晶圓表面粗度劣化之現象。 附帶一提,對此已有使原料氣體中雜質含量在5 p p m以下,並於熱處理爐爐口設置沖吹箱,以防止晶圓 插入爐內時捲入空氣(特開平11 一 135511號), 及爲抑制晶圓插入時空氣捲入,保持晶圓於3 0 〇 °C以下 投入之方法等的提議。 經濟部智慧財/i^M工消費合作社印奴 在此本發明人等所關注著爲,熱處理環境氣體中導入 之微量氧成爲表面粗化之原因的一點。該微量氧之供給源 ,向來僅考慮到來自原料氣體、外氣之侵入,但當係c z 晶圚時退火中之晶圓亦有微量氧之存在。因此,有可能係 退火中表面粗化之原因,基於此一觀點,終於導致本發明 。因而,爲確認晶圓中之氧是否即起自退火的表面粗化之 原因,進行了以下實驗。 首先,製備晶格間氧濃度各爲9、 1 2、 1 6、 2 0 p pma ( J E I DA)之末處理(as-grown) C Z 砂鏡面 晶圓。所有晶圓的(1 0 0 )偏角均在0 · 1 °以下。 將這些晶圓同時投入直立型熱處理爐內,於1 2 0〇 °C作6 0分鐘之氫氣退火(1 〇 0 %氫氣)後,測定各晶 圓之霧度及微粗度,示於第1圖(a)、 (b)、 ( c ) 本紙張尺度適用中國國家標隼(CNS ) A4規格(210X 297公釐) · " 533510 Μ Β7_— ___ 五、發明説明(5 ) 。霧度之測定係用K L A「天扣」公司製之顆粒計數器 Surf Scan SP1,及日立電子工程製L S - 6 〇 3 0 (檢測電 (請先閲讀背面之注意事項再填寫本頁) 壓700伏特)(第1圖(a)、 (b)。而微粗度之評 估,係用Dlglul Instruments公司製之AFM (原子力顯微 鏡)NanoScope-II,以2微米見方之P — V (峰頂至谷底 )値作比較(第1圖(C ))。 由第1圖可知,霧度及微粗度均具隨晶圓之氧濃度的 增加而惡化之傾向。特別是,當氧濃度超過1 6 p p m a 時其程度變大。由此實驗可以確認,使退火之晶圓其氧濃 度低至某一程度,即可抑制起因於退火的表面粗化。 如上述,矽晶圓的熱處理之際表面所生之粗化,深受 矽晶圓本身所含的氧(晶格間氧)濃度影響一事,乃初次 由本發明人等所發現。 以下更具體說明本發明。 使用於本發明的C Z矽單晶棒之製作,可用已知方法 。亦即,將納入石英坩堝中之多晶矽原料加熱熔化,以種 晶接觸熔體,將之一面旋轉一面緩慢上拉製成所欲直徑之 經濟部智慈財/4¾員工消费合作社印製 石夕卓晶棒。 此時,爲使含於上拉之矽單晶棒中之晶格間氧濃度在 1 6 p p m a ( J E I D A )以下,可用例如,減少坩堝 之轉速,增加導入氣體流量,降低環境氣壓,調整矽熔體 之溫度分布及對流等常用方法。一面施加磁場一面上拉的 所謂M C Z法之使用,可使氧濃度低的矽單晶棒之上拉變 得易於控制。 本紙張尺度適用中國國家標準(CNS ) A4規格(210X297公着) -8 - 533510 A7 B7_ 五、發明説明(6 ) 又,在原料熔體中投入形成有氮化膜之矽晶圓等,於 上拉之結晶中以氮摻雜,則可縮小長入缺陷之大小,故有 利於來自熱處理的長入缺陷之減少、消除。 如此,上拉之氧濃度1 6 P P m a以下之矽單晶棒, 以通常之方法切片、倒角、拋光、蝕刻、硏磨等,可加工 成鏡面硏磨晶圓。當然,此等步驟僅係例示,此外也有淸 洗、打磨者,可作合適之步驟的追加、變更、替代。於是 ,本發明係,將如上製得之晶格間氧濃度在1 6 p p m a 以下之矽鏡面晶圓投入熱處理爐,氫環境氣體下或氬環境 氣體下,或其混合環境氣體下,於選定溫度、選定時間作 熱處理,即可無晶圓表面粗度惡化,而減少或消除長入缺 陷。 特別是,本發明可作熱處理而無霧度惡化,並將矽晶 圓之微粗度提升到以原子力測定的2微米見方之P - V値 在1 · 0 0奈米以下。 此時,爲求熱處理後表面粗度方面特別良好,氧濃度 以在1 2 p pm a以下爲佳。又,熱處理爐除通常之加熱 器加熱式,可同時處理多數晶圓之批式爐以外,可用燈具 加熱式R T A (快熱退火)。而爲減少長入缺陷,熱處理 溫度須在1〇〇CTC以上,1 1〇〇至1 3〇〇°C之範圍 更具效果。 以下舉本發明之實施例及比較例作具體說明,惟本發 明並非僅限於此。 本紙張尺度適用中國國家標準(CNS ) A4規格(21〇X:297公釐) ---------— (請先閲讀背面之注意事項再填寫本頁) 訂 經濟部智慧財產苟a (工消f合作社印製 -9- 經濟部智慧財/i^s (工消費合作社印災 533510 A7 B7 五、發明説明(7 ) (實施例、比較例) 以施加磁場之c Z法,拉製晶格間氧濃度約9 p p m a及約2 0 P P m a之矽單晶棒,製作直徑2〇〇 毫米,面方位(100)之偏向角度0 · 1°以下之鏡面 硏磨晶圓。其次,將這些氧濃度不同的鏡面硏磨晶圓同時 投入直立型熱處理爐,在氬環境氣體(氬氣1 〇 〇%)下 ,於1 2 0 0°C,6 0分鐘進行熱處理,其前後的晶圓表 面之霧度以上述S P 1測定,微粗度2微米見方的p — v 値以上述之Nano Scope-II測定。測定結果記載於表1。 表 1 晶格間氧 霧度(ppm) P ~ V ( :n m ) 濃度 熱處理前 熱處理後 熱處理前 熱處理後 實施例 9ppma 0.08 0.15 1.5 0.72 比較例 2 Oppma 0.07 0.32 1.6 1.27 從表1之結果可知,若矽鏡面晶圓中晶格間氧濃度低 ,在爲減少長入缺陷而作熱處理時,熱處理後之霧度亦不 怎麼惡化,微粗度(P - V )則可反而提升,矽晶圓之微 粗度可爲,以原子力顯微鏡測定之2微米見方的P〜V値 在1 . 0 0奈米以下。 又,爲確認長入缺陷之低減效果’以上述之s p 1測 定存在於熱處理後之晶圓表面的大小〇 · 1微米之L p D (光點缺陷)。實施例之晶圓的L P〇爲5 0個/晶圓, 本紙張尺度適用中國國家標準(CNS ) A4規格(210><297公釐) (請先閲讀背面之注意事項再填寫本頁)533510 A7 B7__ 5. Description of the invention (1) The present invention relates to a method for manufacturing a silicon mirror wafer made by heat-treating (annealing) a C Z silicon wafer. (Please read the precautions on the back before filling in this page.) The CZ silicon wafer made by the CZ method is a known technology. It is known that the particles are derived from the solitary particles Cop and oxygen precipitates. The existence of crystalline defects with Growing-in defects is one of the causes of the degradation of the oxide film's withstand voltage and the disconnection of the wiring. It can be the main cause of the decrease in the yield of the produced components. In recent years, a method of eliminating long-term defects near the surface of the wafer has been prevalently performed as a heat treatment method in a hydrogen environment or a fluorine gas environment. However, if such annealing is performed on a mirror-honed wafer, the long-term defects near the wafer surface can be reduced or eliminated. On the other hand, the local roughness of the wafer surface (mirror-honed surface) is also known ( Micro-roughness), long-term coarseness (haze) deterioration. Such micro-roughness and haze are known to affect the withstand voltage of the oxide film and the mobility of carriers directly below the oxide film of the M 0 S transistor (see J. Appl. Phys. 79 (2), 1 5 January , 1 996, P. 1 1). Printed by the Intellectual Property of the Ministry of Economic Affairs and Consumer Cooperatives. Moreover, the haze deteriorates due to annealing, which makes it difficult to measure the particles attached to the wafer surface. This is because the currently used particle counter 'uses laser light to measure particles and haze simultaneously. If the haze is high, it is difficult to separate the signal from the particles. In order to suppress the haze generated on the wafer surface after such annealing, its technology has a proposal to limit the surface orientation of the silicon wafer used for annealing to a specific deflection angle (off-angle) from (100) Refer to Japanese Patent Laid-Open No. 5 — 1 5 2 1 7 9 and Japanese Patent Laid-open No. 8 — 3 2 1 4 4 3] This paper size is applicable to China National Standard (CNS) Α4 specification (210X 297 mm) -4- 533510 A7 _B7 V. Description of the invention (2). However, this method must be a simple method because it is necessary to closely control the surface orientation of the wafer when slicing it from a silicon rod into a wafer. (Please read the precautions on the back before filling out this page.) Until now, most of the device characteristics have been focused only on the withstand voltage of the oxide film. In addition, when the integration of the MO S device is further improved, it is possible to predict the carriers attached to it. The improvement of mobility will become an important item. Therefore, the wafer used to make components not only reduces the growth defects, but also reduces the micro-roughness and haze. For this reason, there is an expectation for an annealing method that can reduce long-term defects by annealing, and there is no deterioration in micro-roughness and haze. DISCLOSURE OF THE INVENTION The present invention is completed to meet such expectations, and its purpose is to use a very simple method It is used as a manufacturing method and method for sand mirror wafers that do not at least degrade micro-roughness and haze and can reduce long-term defects near the surface of CZ single crystal wafers. Printed by the Ministry of Economic Affairs / I ^ a (Industrial and Consumer Cooperative Society) to achieve the above-mentioned purpose, the method for manufacturing the silicon mirror wafer of the present invention is a mirror-honed c Z Shixi wafers are heat-treated in the environment of hydrogen, argon, or their mixed gas. The micro-roughness of the above Shixi wafers is 2 μm square P-V 値 measured by atomic force microscope at 1.0 nm. The following is a method for manufacturing a sand mirror wafer with its characteristics. In this way, the inter-lattice oxygen concentration below 16 ppma (Nihon Denki; Industrial and Industrial Promotion Association (J [EIDA) specifications) is selected as the annealed mirror surface Honing CZ silicon wafers for heat treatment can make the micro-g rough of silicon wafers into P ~ V i [g # 2 micron square as measured by atomic force microscope. This paper size is applicable to Chinese National Standard (CNS) A4 specification (210X 297 (Mm) -5- 533510 A7 B7 V. Description of the invention (3) 1. 00 nm or less' No deterioration of wafer surface roughness reduces or eliminates growth defects. (Please read the precautions on the back before filling in (This page) At this time, the heat treatment temperature is 1 1 0 0 ° C to 1 3 0 0 ° C is preferred. This is because the growth defect cannot be reduced sufficiently below 1 1 000 ° C, and when the temperature exceeds 1 300 ° C, the wafer in the heat treatment is contaminated by heavy metals and the durability of the heat treatment furnace. Reasons such as doubts. In this way, according to the present invention, a CZ silicon mirror wafer with no micro-roughness and haze deterioration of the wafer surface and reduced growth defects near the wafer surface can be produced by an extremely simple method. Especially The micro-roughness of the silicon wafer of the present invention can be reached, and the 2 μm square P — v 値 measured by the atomic force microscope is below 0 0 nm. Moreover, the surface roughness of the wafer will not be deteriorated, and particles on the surface of the radon will not be deteriorated. Defects such as difficulty in measurement., ', -V,' \ f A simple illustration of the figure of the Ministry of Economic Affairs intellectual property ^ Employee Consumption Cooperative Association t Figure 1 is a graph showing the relationship between the oxygen concentration between the lattices and the surface roughness (A) shows the relationship between spl and haze, (b) shows the relationship between LS-6030 and haze, and (0 :) shows the relationship between eight?-? And? ¥. The best of the invention Embodiments The present invention will be described in detail below. The present inventors and others are interested in reducing the length of CZ silicon wafers. The roughening of the mirror honing surface (deterioration of micro-roughness and haze) that occurs during the annealing performed by the defect. In addition to the conventional method of limiting the deflection angle, the paper size is controlled by the characteristics of the wafer itself. It is applicable in China National Standard (CNS) A4 Specification (210X 297 mm) -6-533510 A7 _____ B7 V. Invention Description (4) The system has been found to find ways to improve it, and has been carefully discussed. (Please read the precautions on the back before filling out this page Therefore, we will focus on the following facts that are generally known as the cause of wafer surface roughening after annealing. The reason is that the oxygen and moisture contained in the raw material gas with a very small amount of impurities are oxidized into the outside air from the furnace tube of the reaction tube during the heat treatment step to form an oxide film on the surface of the wafer. The silicon reaction erodes the surface of the wafer, and as a result, the roughness of the wafer surface deteriorates. Incidentally, for this reason, the impurity content in the raw material gas has been lower than 5 ppm, and a blow box is installed at the furnace mouth of the heat treatment furnace to prevent the air from being drawn into the wafer when it is inserted into the furnace (Japanese Patent Application No. 11-135511). In order to suppress air entrapment at the time of wafer insertion, and a method to keep the wafer input below 300 ° C, etc. The Ministry of Economic Affairs, Intellectual Property, and Industrial Cooperative Co., Ltd. Innu. Here, the inventors are paying attention to the fact that the trace amount of oxygen introduced into the heat-treated ambient gas has become a cause of surface roughening. The supply source of this trace of oxygen has always only considered the intrusion of raw material gas and outside air, but when the c z crystal is a wafer, there is also a trace of oxygen in the wafer. Therefore, it may be the cause of surface roughening during annealing. Based on this viewpoint, the present invention has finally been achieved. Therefore, in order to confirm whether the oxygen in the wafer is caused by the surface roughening from the annealing, the following experiments were performed. First, as-grown C Z sand mirror wafers with inter-lattice oxygen concentrations of 9, 1, 2, 16 and 20 p pma (J E I DA) were prepared. The (100 °) deflection angle of all wafers is below 0 · 1 °. These wafers were simultaneously put into an upright heat treatment furnace, and hydrogen annealing (100% hydrogen) was performed at 120 ° C for 60 minutes, and the haze and micro-roughness of each wafer were measured. 1 Figures (a), (b), (c) The dimensions of this paper are applicable to China National Standard (CNS) A4 (210X 297 mm) · " 533510 Μ Β7_— ___ 5. Description of the invention (5). The haze is measured using Surf Scan SP1, a particle counter manufactured by KLA "Tiankou", and LS-6 by Hitachi Electronics Engineering. 0 (Detection of electricity (please read the precautions on the back before filling this page). 700 volts ) (Figure 1 (a), (b). The micro-roughness was evaluated using AFM (Atomic Force Microscopy) NanoScope-II manufactured by Dlglul Instruments, Inc., P-V (peak to valley) in 2 micron square)値 For comparison (Figure 1 (C)). From Figure 1, it can be seen that the haze and micro-roughness tend to worsen as the oxygen concentration of the wafer increases. In particular, when the oxygen concentration exceeds 16 ppma The degree becomes larger. From this experiment, it can be confirmed that by making the annealed wafer's oxygen concentration low to a certain degree, the surface roughening caused by the annealing can be suppressed. The roughening, which is deeply affected by the oxygen (inter-lattice oxygen) concentration contained in the silicon wafer itself, was first discovered by the present inventors and others. The present invention will be described in more detail below. Among the CZ silicon single crystal rods used in the present invention It can be produced by known methods. That is, quartz crucible will be incorporated The polycrystalline silicon material in the medium is heated and melted, the seed crystal contacts the melt, and one side is rotated and the other side is slowly pulled up to produce the Shi Xizhuo crystal rod of the Ministry of Economic Affairs Zhicicai / 4¾ Employee Consumer Cooperative. The inter-lattice oxygen concentration in the pulled-up silicon single crystal rod is below 16 ppma (JEIDA), which can be used, for example, to reduce the speed of the crucible, increase the flow of introduced gas, reduce the ambient air pressure, and adjust the temperature distribution of the silicon melt. And common methods such as convection. The application of the so-called MCZ method while applying a magnetic field and pulling on one side can make it easy to control the pull-up of silicon single crystal rods with low oxygen concentration. This paper size applies the Chinese National Standard (CNS) A4 specification ( 210X297) -8-533510 A7 B7_ V. Description of the Invention (6) In addition, silicon wafers with a nitride film formed in the raw material melt are put into the pull-up crystal with nitrogen, which can be reduced. The size of the growing defect is beneficial to the reduction and elimination of the growing defect from the heat treatment. In this way, the silicon single crystal rod with an oxygen concentration of 16 PP ma or less is sliced, chamfered, polished, and etched in the usual way. , Honing, etc., can be processed into mirror honing wafers. Of course, these steps are only examples, and there are also honing, polishing, and can add, change, and replace suitable steps. Therefore, the present invention, will The silicon mirror wafer with the inter-lattice oxygen concentration below 16 ppma prepared as above is put into a heat treatment furnace, under a hydrogen ambient gas or an argon ambient gas, or a mixed ambient gas, and heat-treated at a selected temperature and a selected time, that is, It can reduce the roughness of the wafer surface, and reduce or eliminate the growth defects. In particular, the invention can be used for heat treatment without deterioration of the haze, and the micro-roughness of the silicon wafer can be increased to 2 micron square measured by atomic force. P-V 値 is below 1.0 nm. In this case, in order to obtain particularly good surface roughness after heat treatment, the oxygen concentration is preferably 1 2 p pm a or less. In addition, the heat treatment furnace can be a lamp heating type R T A (rapid thermal annealing) in addition to a normal heater heating type and a batch type furnace capable of processing most wafers simultaneously. In order to reduce long-term defects, the heat treatment temperature must be above 100CTC, and the range of 1100 to 1300 ° C is more effective. Examples and comparative examples of the present invention will be specifically described below, but the present invention is not limited thereto. This paper size applies the Chinese National Standard (CNS) A4 specification (21〇X: 297 mm) ---------— (Please read the notes on the back before filling this page) Order the intellectual property of the Ministry of Economic Affairs a (Printed by Industrial Consumers Cooperatives-9- Wisdom of the Ministry of Economic Affairs / i ^ s (Printed by Industrial and Consumer Cooperatives 533510 A7 B7 V. Description of the Invention (7) (Examples, Comparative Examples) c z method of applying a magnetic field, A silicon single crystal ingot having an oxygen concentration of about 9 ppma and about 20 PP ma was drawn to produce a mirror-honed wafer with a diameter of 200 mm and a deflection angle of a plane orientation (100) of 0. 1 ° or less. Next The mirror-polished honing wafers with different oxygen concentrations were simultaneously put into an upright heat treatment furnace, and heat treatment was performed at 12,000 ° C for 60 minutes under an argon ambient gas (100% argon). The haze on the wafer surface was measured with SP 1 above, and the micro-roughness was 2 μm square p — v 値 was measured with Nano Scope-II. The measurement results are shown in Table 1. Table 1 Inter-lattice oxygen haze (ppm) P ~ V (: nm) Concentration before heat treatment After heat treatment After heat treatment Example 9ppma 0.08 0.15 1.5 0.72 Comparison Example 2 Oppma 0.07 0.32 1.6 1.27 It can be seen from the results in Table 1 that if the oxygen concentration in the crystal lattice of the silicon mirror wafer is low, when the heat treatment is performed to reduce the growth of defects, the haze after heat treatment will not be deteriorated, and it will be slightly coarse. The degree (P-V) can be improved instead, and the micro-roughness of the silicon wafer can be P ~ V 値, which is 2 micrometers square measured by atomic force microscope, is less than 1.0 nm. In addition, in order to confirm long-term defects Low-reduction effect 'Measured at the above-mentioned sp 1 on the surface of the wafer after heat treatment. The size of L p D (light point defect) of 0.1 micron. The LP0 of the wafer of the example is 50 pieces / wafer. This paper size applies to China National Standard (CNS) A4 specification (210 > < 297mm) (Please read the precautions on the back before filling this page)

-10 - 533510 A7 B7 五、發明説明(8 ) 較之熱處理前之水準(數百個/晶圓),知已大爲減少。 另一方面,比較例之晶圓,因霧度高,無法正確測定 D Ρ L之 、大米微 ----------0 —I (請先閱讀背面之注意事項再填寫本頁)-10-533510 A7 B7 V. Description of the invention (8) Compared with the level before heat treatment (hundreds / wafer), it is known that it has been greatly reduced. On the other hand, the wafer of the comparative example has a high haze and cannot accurately measure D ρ L, rice micro ---------- 0 —I (Please read the precautions on the back before filling this page )

、1T 經濟部智慧財產:ιΐτ員工消費合作社印製 本紙張尺度適用中國國家標準(CNS ) A4規格(210X 297公釐) -11 -1T Intellectual Property of the Ministry of Economic Affairs: Printed by ιΐτ Employee Cooperative Cooperative This paper is sized for China National Standard (CNS) A4 (210X 297 mm) -11-

Claims (1)

533510 A8 B8 C8 D8 六、申請專利範圍 1 · 一種矽鏡面晶圓之製造方法,其特徵爲:對晶格 間氧濃度在1 6 p p m a以下之經鏡面硏磨的C Z矽晶圓 ,在氫、氬或這些之混合氣體環境下進行熱處理,該矽晶 圓之微粗度成爲,以原子力顯微鏡測定之2微米見方的P —V値在1 · 0 0奈米以下。 2 ·如申請專利範圍第1項之矽鏡面晶圓的製造方法 ,其中上述熱處理係在1 1 0 0 °C至1 3 0 0 °C之溫度範 圍進行。 (請先閲讀背面之注意事項再填寫本頁} 經濟部智慧財產局”只工消費合作社印製 12 本紙張尺度逋用中國國家梂準(CNS ) A4規格(210X297公釐)533510 A8 B8 C8 D8 VI. Patent application scope 1 · A method for manufacturing silicon mirror wafers, which is characterized by mirror-honed CZ silicon wafers with inter-lattice oxygen concentration below 16 ppma. When the heat treatment is performed in an argon or a mixed gas environment, the micro-roughness of the silicon wafer becomes 2 μm square P — V 値 measured by an atomic force microscope, which is below 1.0 nm. 2 · The method for manufacturing a silicon mirror wafer according to item 1 of the patent application range, wherein the above heat treatment is performed at a temperature range of 1 100 ° C to 130 ° C. (Please read the notes on the back before filling in this page} The Intellectual Property Bureau of the Ministry of Economic Affairs “Printed by the Consumer Cooperatives only 12 paper sizes in accordance with China National Standards (CNS) A4 (210X297 mm)
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CN113281304B (en) * 2021-04-01 2023-11-21 上海新昇半导体科技有限公司 Annealing furnace cooling rate calibration method

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