JP2000026196A - Silicon semiconductor substrate and its production - Google Patents

Silicon semiconductor substrate and its production

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Publication number
JP2000026196A
JP2000026196A JP8491599A JP8491599A JP2000026196A JP 2000026196 A JP2000026196 A JP 2000026196A JP 8491599 A JP8491599 A JP 8491599A JP 8491599 A JP8491599 A JP 8491599A JP 2000026196 A JP2000026196 A JP 2000026196A
Authority
JP
Japan
Prior art keywords
substrate
semiconductor substrate
silicon semiconductor
atoms
crystal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP8491599A
Other languages
Japanese (ja)
Other versions
JP4084902B2 (en
Inventor
Atsushi Ikari
敦 碇
Hikari Sakamoto
光 坂本
Katsuhiko Nakai
克彦 中居
Taizo Hoshino
泰三 星野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Steel Corp
Siltronic Japan Corp
Original Assignee
Nippon Steel Corp
NSC Electron Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Steel Corp, NSC Electron Corp filed Critical Nippon Steel Corp
Priority to JP08491599A priority Critical patent/JP4084902B2/en
Priority to US09/508,467 priority patent/US6548886B1/en
Priority to DE19983188T priority patent/DE19983188T1/en
Priority to PCT/JP1999/002336 priority patent/WO1999057344A1/en
Priority to KR1020007012157A priority patent/KR100541882B1/en
Publication of JP2000026196A publication Critical patent/JP2000026196A/en
Application granted granted Critical
Publication of JP4084902B2 publication Critical patent/JP4084902B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Crystals, And After-Treatments Of Crystals (AREA)
  • Liquid Deposition Of Substances Of Which Semiconductor Devices Are Composed (AREA)

Abstract

PROBLEM TO BE SOLVED: To prevent vacancy defects from being caused by adding nitrogen and thereby to produce a heat-treated substrate having a high quality surface layer of denuded zone(DZ) in the production of a silicon single crystal substrate by a Czochralski method. SOLUTION: In this production, nitrogen is added at the time of producing a silicon single crystal by a Czochralski method and the produced silicon single crystal contg. 1×1013 to 1×1016 atoms/cm3 nitrogen is subjected to heat treatment to produce a semiconductor substrate in which the density of crystal defects each having a >=0.1 μm size (expressed in terms of the diameter), in the region ranging from the surface of the substrate to a 1 μm depth, is <=104 ((number of defects)/cm3). Thus, the objective substrate having an almost defectless surface layer of denuded zone(DZ) can be produced and a wafer that enable a high manufacturing yield of a device, can be provided.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、シリコン半導体基
板の品質改善に関し、特に、基板内部あるいは基板表面
の欠陥を除去し、基板上に作成するデバイスの歩留りを
向上させるシリコン半導体基板及びその製造方法に関す
る。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the improvement of the quality of a silicon semiconductor substrate, and more particularly to a silicon semiconductor substrate for removing defects inside or on the surface of a substrate and improving the yield of devices formed on the substrate, and a method of manufacturing the same. About.

【0002】[0002]

【従来の技術】シリコン半導体基板を用いて半導体デバ
イスを作成する際に、基板中の結晶欠陥がデバイスの動
作不良を引き起こし、基板中の結晶欠陥密度によりデバ
イスの製造歩留りが変化することが知られている。近
年、このデバイス動作不良を引き起こす結晶欠陥とし
て、COP(Crystal Originated
Particle)と呼ばれる欠陥が注目されている。
これは、シリコン半導体基板をアンモニア−過酸化水素
の混合液でエッチングした際、結晶中の格子欠陥を原因
としたピットが基板表面に生じ、基板表面のパーティク
ルを計数する検査装置によりこのピットが測定されるた
め、このように呼ばれている。COPとはこのような測
定法で検出される欠陥全般を指す名称であるが、通常の
チョクラルスキー(CZ)法もしくは磁場を印加したC
Z法により育成されたシリコン単結晶では、この欠陥の
実体は結晶中の八面体様の空隙(以下、空孔欠陥と称
す)と考えられており、これがデバイスの構造的な破壊
を引き起こすと推定されている。このようなデバイス作
成に有害なCOPを低減あるいは消滅させる技術とし
て、これまでにいくつかの提案がなされている。
2. Description of the Related Art When a semiconductor device is manufactured using a silicon semiconductor substrate, it is known that crystal defects in the substrate cause operation failure of the device, and the manufacturing yield of the device changes depending on the density of crystal defects in the substrate. ing. In recent years, COP (Crystal Originated) has been used as a crystal defect causing this device operation failure.
A defect called “Particle” has attracted attention.
This is because when a silicon semiconductor substrate is etched with a mixture of ammonia and hydrogen peroxide, pits are generated on the substrate surface due to lattice defects in the crystal, and the pits are measured by an inspection device that counts particles on the substrate surface. It is so called. The COP is a name indicating all the defects detected by such a measuring method, and is usually a Czochralski (CZ) method or a C
In a silicon single crystal grown by the Z method, the substance of this defect is considered to be an octahedral-like void in the crystal (hereinafter referred to as a vacancy defect), which is presumed to cause structural destruction of the device. Have been. Several techniques have been proposed as techniques for reducing or eliminating COPs harmful to device fabrication.

【0003】COPを消滅させる技術として、単結晶育
成の際の結晶成長速度を0.8mm/min以下とする
ことが知られている(特開平2−267195号公
報)。これは、空孔欠陥を作る要素である空孔型点欠陥
(vacancy)の結晶成長界面での導入量を減少さ
せ、また単結晶の冷却速度を緩やかなものとすることに
より、冷却中に発生する過飽和な空孔型点欠陥(vac
ancy)の発生を抑えるものである。しかしながら、
この方法では、成長速度の低下による生産性の低下を招
くとともに、転位ループ等のCOPとは別種の結晶欠陥
を発生させると言う問題がある。
As a technique for eliminating COP, it is known that the crystal growth rate during growing a single crystal is 0.8 mm / min or less (Japanese Patent Laid-Open No. 2-267195). This is because the amount of vacancy type vacancies, which are the elements that create vacancy defects, at the crystal growth interface is reduced, and the cooling rate of the single crystal is reduced, thereby causing vacancy during cooling. Supersaturated vacancy type point defects (vac
ancy) is suppressed. However,
This method has a problem that productivity is lowered due to a reduction in growth rate, and another type of crystal defect such as a dislocation loop is generated from the COP.

【0004】COP発生を抑制する技術としては、単結
晶の冷却挙動の制御、特に単結晶が約1200℃から1
000℃の温度範囲を通過する時間の制御が有効である
ことが知られている(特開平8−12493号公報、特
開平8−91983号公報、特開平9−227289号
公報)。これらの技術は、単結晶の成長速度を大きく低
下させないため、生産性という点では問題はないが、C
OP密度の低減下限は概ね105 個/cm3 程度であ
り、更なる低減、例えば104 個/cm3 以下の密度を
達成することは困難である。
As a technique for suppressing the generation of COP, control of the cooling behavior of a single crystal, in particular, when the single crystal
It is known that the control of the time for passing through the temperature range of 000 ° C. is effective (JP-A-8-12493, JP-A-8-91983, and JP-A-9-227289). Since these techniques do not significantly reduce the growth rate of the single crystal, there is no problem in terms of productivity.
The lower limit of the OP density reduction is about 10 5 / cm 3 , and it is difficult to achieve a further reduction, for example, a density of 10 4 / cm 3 or less.

【0005】また、COP低減技術として結晶育成時に
結晶を冷却する際850℃〜1100℃の温度範囲での
冷却中の単結晶の保持時間を80分未満とし、または結
晶を育成する際窒素濃度が1×1014/cm3であるシ
リコン単結晶を育成し、その後シリコンウェハに加工後
1000℃以上の温度で1時間以上熱処理する技術が知
られている(特開平10−98047号公報)。これ
は、結晶製造時に発生するCOPのサイズ分布をより小
さい方にシフトさせることにより熱処理の際に欠陥を消
滅させやすくする技術である。しかしながら、このサイ
ズ減少の効果は酸素濃度が低いほど顕著とされており、
チョクラルスキー法で常用される7〜10×1017/c
3の酸素濃度では実施されていない。このため、通常
基板中の酸素濃度を高めることにより得られる基板内部
での酸素析出物の発生を利用したゲッタリング能の付与
とCOPの低減との両立が難しい。
[0005] Further, as a COP reduction technique, when the crystal is cooled at the time of growing the crystal, the holding time of the single crystal during the cooling in the temperature range of 850 ° C to 1100 ° C is set to less than 80 minutes, or the nitrogen concentration when growing the crystal is reduced. There is known a technique in which a silicon single crystal of 1 × 10 14 / cm 3 is grown, then processed into a silicon wafer and then heat-treated at a temperature of 1000 ° C. or more for 1 hour or more (Japanese Patent Application Laid-Open No. 10-98047). This is a technique that makes it easier to eliminate defects during heat treatment by shifting the size distribution of COP generated during crystal production to a smaller size. However, the effect of this size reduction is more pronounced as the oxygen concentration is lower,
7 to 10 × 10 17 / c commonly used in the Czochralski method
Not performed at an oxygen concentration of m 3 . For this reason, it is difficult to achieve both the provision of the gettering ability utilizing the generation of oxygen precipitates inside the substrate and the reduction of COP, which are usually obtained by increasing the oxygen concentration in the substrate.

【0006】また、単結晶育成時のCOP低減技術以外
にも、単結晶からスライス・研磨して基板とした後に熱
処理をすることにより、基板表面のCOPを低減・消滅
させる技術も知られている。例えば、特開平3−233
936号公報には、800〜1250℃で10時間以下
の熱処理を行うことが提案されている。しかしながら、
この公報の実施例に示されている酸化雰囲気で熱処理を
行うと、基板表面の酸化侵食に伴い、空孔欠陥が基板表
面に転写され、基板表面のピットの増大を招くと言う欠
点があるとともに、基板表面から深さ1μmの範囲内の
COP密度を104 個/cm3 以下とすることは困難で
ある。また、特開昭59−20264号公報には、水素
雰囲気中で熱処理することが提案されている。この方法
は、水素雰囲気を用いることにより、最表面のCOPを
消滅させ、かつ表面から0.5μm以内のCOP密度を
104 個/cm3 以下とすることができるが、表面から
さらに深い部分のCOP密度を104 個/cm3 以下と
することはできず、デバイス作成の観点からは無欠陥層
の形成が不充分である。さらに、この方法では、水素と
いう爆発性の雰囲気を用いるため安全上の対策を充分に
行う必要がある。
In addition to the COP reduction technique at the time of growing a single crystal, there is also known a technique of reducing and eliminating COP on a substrate surface by performing a heat treatment after slicing and polishing a single crystal to form a substrate. . For example, JP-A-3-233
No. 936 proposes performing a heat treatment at 800 to 1250 ° C. for 10 hours or less. However,
When heat treatment is performed in an oxidizing atmosphere shown in the examples of this publication, there is a defect that vacancy defects are transferred to the substrate surface due to oxidative erosion of the substrate surface and pits on the substrate surface increase, and It is difficult to reduce the COP density within a range of 1 μm from the substrate surface to 10 4 / cm 3 or less. Japanese Patent Application Laid-Open No. 59-20264 proposes a heat treatment in a hydrogen atmosphere. According to this method, the COP on the outermost surface can be eliminated by using a hydrogen atmosphere, and the COP density within 0.5 μm from the surface can be reduced to 10 4 particles / cm 3 or less. The COP density cannot be reduced to 10 4 pieces / cm 3 or less, and formation of a defect-free layer is insufficient from the viewpoint of device fabrication. Further, in this method, since an explosive atmosphere of hydrogen is used, it is necessary to take sufficient safety measures.

【0007】シリコンの単結晶成長の際に窒素を添加す
ることについて、添加方法に関しては特開昭60−25
1190号公報等が知られている。また、フロートゾー
ン(FZ)単結晶における窒素添加効果として、特開昭
57−17497号公報等には結晶強度の増加が、特開
平8−91993号公報には抵抗率の変化を抑える方法
が開示されている。さらに、酸素が単結晶中に存在する
場合には、窒素を添加することによりCOP欠陥が小さ
くなることがD.Graf等によって報告されている
(The Electrochemical Soci
ety Proceeding Vol.96−13,
pp117, 1996)が、このメカニズムについ
ては、FZ結晶中の空孔型欠陥(vacancy)を抑
制するのと同様なメカニズムがCZ結晶の場合にも働
き、空孔型欠陥の凝集体である空孔欠陥のサイズを小さ
くしているものと推論している。
[0007] Regarding the addition of nitrogen during single crystal growth of silicon, the method of addition of nitrogen is described in JP-A-60-25.
No. 1190 is known. JP-A-57-17497 discloses an increase in crystal strength, and JP-A-8-91993 discloses a method of suppressing a change in resistivity as a nitrogen addition effect in a float zone (FZ) single crystal. Have been. Further, when oxygen is present in the single crystal, COP defects can be reduced by adding nitrogen. Graf et al. (The Electrochemical Soci
ety Proceeding Vol. 96-13,
pp. 117, 1996), regarding this mechanism, the same mechanism that suppresses vacancy type defects (vacancies) in FZ crystals also works in the case of CZ crystals, and vacancies that are aggregates of vacancy type defects are used. Infers that the size of the defect is reduced.

【0008】[0008]

【発明が解決しようとする課題】本発明は、半導体デバ
イス作成用のシリコン半導体基板において、前述したよ
うな従来の技術では完全には除去できないデバイス作成
上問題となる結晶欠陥を、生産性良く、効果的に低減あ
るいは消滅させたシリコン半導体基板及びその製造方法
を提供することを目的とする。
SUMMARY OF THE INVENTION The present invention is to provide a silicon semiconductor substrate for producing a semiconductor device, with good productivity, a crystal defect which becomes a problem in device production which cannot be completely removed by the conventional technique as described above. It is an object of the present invention to provide a silicon semiconductor substrate that has been effectively reduced or eliminated and a method for manufacturing the same.

【0009】[0009]

【課題を解決するための手段】我々は、シリコン半導体
基板中に生成する欠陥について鋭意検討を加え、シリコ
ン半導体基板のデバイス作成領域で問題となる大きさの
欠陥をほぼ完全に消滅できることを見出し、本発明を完
成させたものである。
Means for Solving the Problems We have made intensive studies on defects generated in a silicon semiconductor substrate, and found that defects having a problematic size can be almost completely eliminated in a device fabrication region of a silicon semiconductor substrate. The present invention has been completed.

【0010】即ち、本発明は、チョクラルスキー(C
Z)法又は磁場印加CZ法により育成したシリコン単結
晶から得たシリコン半導体基板であって、少なくとも基
板表面から深さ1μmまでの領域において、直径換算で
0.1μm以上の結晶欠陥の密度が104 個/cm3
下であることを特徴とするシリコン半導体基板である。
更に好ましくは前記シリコン半導体基板の厚み中心にお
ける窒素含有量が1×1013atoms/cm3 以上1
×1016atoms/cm3 以下であるシリコン半導体
基板である。また、本発明は、前記シリコン半導体基板
の窒素含有量が1×1016atoms/cm3 以下、特
に1×1013atoms/cm3 以上1×1016ato
ms/cm3 以下であり、かつ該基板中を二次イオン質
量分析法で測定した窒素濃度が、平均信号強度の2倍以
上の信号強度を示す窒素偏析による局所濃化部を有する
シリコン半導体基板である。
That is, the present invention relates to Czochralski (C)
Z) A silicon semiconductor substrate obtained from a silicon single crystal grown by a method or a magnetic field applying CZ method, wherein a density of crystal defects having a diameter of 0.1 μm or more in terms of a diameter of at least 10 μm in a region from the substrate surface to a depth of 1 μm is 10%. A silicon semiconductor substrate characterized in that the number is 4 / cm 3 or less.
More preferably, the nitrogen content at the center of the thickness of the silicon semiconductor substrate is 1 × 10 13 atoms / cm 3 or more.
It is a silicon semiconductor substrate having a density of × 10 16 atoms / cm 3 or less. Further, the present invention provides the silicon semiconductor substrate having a nitrogen content of 1 × 10 16 atoms / cm 3 or less, particularly 1 × 10 13 atoms / cm 3 or more and 1 × 10 16 atoms / cm 3 or more.
a silicon semiconductor substrate having a local concentration portion due to nitrogen segregation, which has a signal intensity of not more than 2 ms / cm 3 and a nitrogen concentration measured by secondary ion mass spectrometry in the substrate of not more than twice the average signal intensity. It is.

【0011】また、本発明は、CZ法又は磁場印加CZ
法により育成したシリコン単結晶から得たシリコン半導
体基板であって、基板厚み中心から表面に向かって結晶
欠陥が減少する密度分布を有し、基板表面における直径
換算で0.1μm以上の結晶欠陥の面密度が1個/cm
2 以下であり、かつ基板表面から深さ0.1μmにおけ
る直径換算で0.1μm以上の結晶欠陥の体積密度が基
板厚み中心に比べ1%以下であり、さらに基板厚み中心
における窒素含有量が1×1013atoms/cm3
上1×1016atoms/cm3 以下であることを特徴
とするシリコン半導体基板である。ここでいう結晶欠陥
に含まれるものとしては空孔欠陥、酸素析出物、積層欠
陥などのデバイス不良の原因となるあらゆる結晶欠陥を
指す。
The present invention also relates to a CZ method or a CZ applying a magnetic field.
A silicon semiconductor substrate obtained from a silicon single crystal grown by a method, having a density distribution in which crystal defects decrease from the center of the substrate thickness toward the surface, and having a crystal defect of 0.1 μm or more in terms of diameter on the substrate surface. Area density 1 piece / cm
2 or less, and the volume density of crystal defects having a diameter of 0.1 μm or more at a depth of 0.1 μm from the substrate surface is 1% or less of the substrate thickness center and the nitrogen content at the substrate thickness center is 1% or less. A silicon semiconductor substrate characterized by being at least 10 13 atoms / cm 3 and not more than 1 10 16 atoms / cm 3 . The term “crystal defects” as used herein refers to any crystal defects that cause device failure, such as vacancy defects, oxygen precipitates, and stacking faults.

【0012】また、本発明は、1×1016atoms/
cm3 以上1.5×1019atoms/cm3 以下の窒
素を含有するシリコン融液を用いてCZ法又は磁場印加
CZ法により育成したシリコン単結晶から得たシリコン
半導体基板を、1000℃以上1300℃以下の温度で
1時間以上熱処理することを特徴とするシリコン半導体
基板の製造方法であり、更に、シリコン単結晶をCZ法
又は磁場印加CZ法により育成する際に、引上速度をV
(mm/min)、シリコンの融点から1300℃まで
の温度範囲における引上軸方向の結晶内温度勾配の平均
値をG(℃/mm)とするとき、V/G≧0.2(mm
2 /℃min)を満足する条件で育成することが好まし
く、また熱処理条件としては、非酸化性ガス雰囲気中で
熱処理すること、もしくは、酸素を0.01vol%以
上100vol%以下を含有するガス雰囲気中で熱処理
した後基板表面を0.5μm以上1.0μm以下研磨し
て基板表面を鏡面とすることが、好ましい。
[0012] The present invention also provides a method of 1 × 10 16 atoms /
The silicon semiconductor substrate obtained from a silicon single crystal grown by the CZ method or the magnetic field applied CZ method using a silicon melt containing cm 3 or more 1.5 × 10 19 atoms / cm 3 or less of nitrogen, 1000 ° C. to 1,300 A method for producing a silicon semiconductor substrate, comprising performing heat treatment at a temperature of not more than 1 ° C. for 1 hour or more. Further, when growing a silicon single crystal by a CZ method or a CZ method applying a magnetic field, the pulling speed is set to V
(Mm / min), when the average value of the temperature gradient in the crystal in the pulling axis direction in the temperature range from the melting point of silicon to 1300 ° C. is G (° C./mm), V / G ≧ 0.2 (mm
2 / ° C. min), and heat treatment is preferably performed in a non-oxidizing gas atmosphere or in a gas atmosphere containing oxygen in an amount of 0.01 vol% or more and 100 vol% or less. It is preferable that the surface of the substrate is mirror-finished by polishing the surface of the substrate after the heat treatment in 0.5 μm or more and 1.0 μm or less.

【0013】[0013]

【発明の実施の形態】以下に、本発明について詳細に説
明する。
BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, the present invention will be described in detail.

【0014】本発明のシリコン半導体基板は、CZ法又
は磁場印加CZ法により育成したシリコン単結晶から得
たシリコン半導体基板であって、少なくとも基板表面か
ら深さ1μmまでの領域において、直径換算で0.1μ
m以上の結晶欠陥の密度が104 個/cm3 以下である
ことが必要である。我々は、シリコン半導体基板のデバ
イス作成領域における結晶欠陥について検討を加えた結
果、デバイスの構造的な破壊を確実に引き起こす欠陥
は、直径換算で0.1μm以上の大きさを持つものであ
り、この大きさより小さい欠陥は障害にならないことが
多いことを見出した。また、シリコン半導体基板のデバ
イス作成では、表面から深さ1μmまでの領域の欠陥が
歩留まりに大きく影響するため、少なくとも基板表面か
ら深さ1μmの領域において、デバイスに有害な欠陥を
除去できれば、基板上に作成するデバイスの歩留りを大
幅に向上できる。欠陥密度としては体積密度で104
/cm3 以下であれば1cm×1cm×1μmの領域に
欠陥1個の割合であり、現在のデバイスの大きさを考慮
するとほぼ十分な欠陥密度であると考えられる。
The silicon semiconductor substrate of the present invention is a silicon semiconductor substrate obtained from a silicon single crystal grown by a CZ method or a magnetic field applying CZ method, and has a diameter of at least 1 μm from the substrate surface. .1μ
It is necessary that the density of crystal defects of m or more be 10 4 / cm 3 or less. We have examined crystal defects in the device fabrication region of the silicon semiconductor substrate, and as a result, defects that reliably cause structural destruction of the device have a size of 0.1 μm or more in terms of diameter. It has been found that defects smaller than the size often do not become obstacles. In addition, in device fabrication of a silicon semiconductor substrate, defects in a region from the surface to a depth of 1 μm greatly affect the yield. Therefore, at least in a region at a depth of 1 μm from the substrate surface, if a defect harmful to the device can be removed, The yield of devices to be created can be greatly improved. If the defect density is 10 4 / cm 3 or less, the defect density is a ratio of one defect in a 1 cm × 1 cm × 1 μm region. If the defect size is considered to be sufficient when the current device size is considered. Conceivable.

【0015】また、さらに本発明のシリコン半導体基板
は、基板厚み中心において窒素を1×1013atoms
/cm3 以上1×1016atoms/cm3 以下、より
好ましくは5×1013atoms/cm3 以上1×10
16atoms/cm3 以下、さらには5×1014ato
ms/cm3 以上1×1016atoms/cm3 以下含
有することが好ましい。シリコン単結晶中に窒素を導入
することにより、結晶育成時の点欠陥濃度及び点欠陥の
凝集挙動が変化して、結晶中に空孔欠陥を変容させ、密
度が107 個/cm3 以上の酸素析出物が発生するよう
になる。引上条件によっては変容した空孔欠陥が酸素析
出物の密度の5%以下発生する場合がある。基板中の窒
素含有量が、1×1013atoms/cm3 未満では空
孔欠陥を変容させることが難しく、1×1016atom
s/cm3 超になると結晶育成の際転位が入りやすくな
り、また窒素が酸素と複合欠陥を形成して基板の抵抗を
変化させたり、さらに熱処理により積層欠陥ができやす
くなる。なお、基板中の窒素含有量は、SIMS(Se
condary Ion Mass Spectros
copy)を用いることにより測定できる。
Further, in the silicon semiconductor substrate of the present invention, nitrogen is supplied at 1 × 10 13 atoms at the center of the substrate thickness.
/ Cm 3 or more and 1 × 10 16 atoms / cm 3 or less, more preferably 5 × 10 13 atoms / cm 3 or more and 1 × 10
16 atoms / cm 3 or less, and further 5 × 10 14 atoms
It is preferably contained in the range from ms / cm 3 to 1 × 10 16 atoms / cm 3 . By introducing nitrogen into a silicon single crystal, the concentration of point defects and the aggregation behavior of point defects at the time of crystal growth change, transforming the vacancy defects into the crystal, and increasing the density to 10 7 / cm 3 or more. Oxygen precipitates are generated. Depending on the pulling conditions, transformed vacancy defects may be generated at 5% or less of the density of oxygen precipitates. If the nitrogen content in the substrate is less than 1 × 10 13 atoms / cm 3 , it is difficult to transform the vacancy defects, and 1 × 10 16 atoms / cm 3 is difficult.
If it exceeds s / cm 3 , dislocation is likely to occur during crystal growth, and nitrogen forms complex defects with oxygen to change the resistance of the substrate, and stacking faults are more likely to occur by heat treatment. The nitrogen content in the substrate was determined by SIMS (Se
condary Ion Mass Spectros
copy)).

【0016】さらに本発明においては、前記シリコン半
導体基板の窒素含有量が1×1016atoms/cm3
以下、特に1×1013atoms/cm3 以上1×10
16atoms/cm3 以下であり、かつ該基板中を二次
イオン質量分析法で測定した窒素濃度が、平均信号強度
の2倍以上の信号強度を示す窒素偏析による局所濃化部
を有するものであることが好ましい。結晶育成の際に導
入された窒素は必ずしも結晶内に均一に分布するとは限
らない。結晶の育成条件によっては、窒素の局所的な偏
析・濃化により平均の窒素濃度もしくは測定下限の2倍
以上の強度で局所的な信号強度の増大が認められる場合
がある。これはたとえSIMSで測定された平均の窒素
濃度が1×1016atoms/cm3 未満あるいは測定
下限以下の場合でもみられることがある。このような場
合でも、結晶育成時の点欠陥の凝集の抑制・酸素析出物
の生成は十分であり、その後のアニールにより容易に欠
陥を消滅させることができる。
Further, in the present invention, the nitrogen content of the silicon semiconductor substrate is 1 × 10 16 atoms / cm 3.
Below, especially 1 × 10 13 atoms / cm 3 or more and 1 × 10
It has a local concentration portion due to nitrogen segregation that is 16 atoms / cm 3 or less and the nitrogen concentration in the substrate measured by secondary ion mass spectrometry is twice or more the average signal intensity. Preferably, there is. Nitrogen introduced during crystal growth is not always uniformly distributed in the crystal. Depending on crystal growth conditions, local segregation and concentration of nitrogen may cause a local increase in signal intensity at an average nitrogen concentration or at least twice the intensity of the lower limit of measurement. This may be observed even when the average nitrogen concentration measured by SIMS is less than 1 × 10 16 atoms / cm 3 or less than the lower limit of measurement. Even in such a case, the suppression of aggregation of point defects and the generation of oxygen precipitates during crystal growth are sufficient, and the defects can be easily eliminated by subsequent annealing.

【0017】また、窒素添加により発生した酸素析出物
は、基板厚み中心から表面に向かって酸素濃度が減少す
る密度分布を持たせることにより、基板表面付近で消滅
させることができる。そして、基板厚み中心から表面に
向かって結晶欠陥の減少する密度分布がつくられ、基板
表面から深さ0.1μmにおける直径換算で0.1μm
以上の結晶欠陥の体積密度が基板厚み中心に比べ2桁以
上(1%以下)低下させることが必要である。また基板
最表面における直径換算で0.1μm以上の結晶欠陥の
面密度も非酸化性雰囲気での熱処理あるいは表面の研磨
により1個/cm2 以下とすることができる。これらの
結晶欠陥(主として酸素析出物)の密度を越えると、デ
バイスの構造的破壊を引き起こし易くなり、基板上に作
成したデバイスの歩留りが悪化してしまう。
The oxygen precipitates generated by the addition of nitrogen can be eliminated near the substrate surface by providing a density distribution in which the oxygen concentration decreases from the center of the substrate thickness toward the surface. Then, a density distribution in which crystal defects decrease from the center of the substrate thickness toward the surface is formed, and the diameter is reduced to 0.1 μm at a depth of 0.1 μm from the substrate surface.
It is necessary to reduce the volume density of the above crystal defects by two digits or more (1% or less) as compared with the center of the substrate thickness. The surface density of crystal defects having a diameter of 0.1 μm or more at the outermost surface of the substrate can be reduced to 1 / cm 2 or less by heat treatment in a non-oxidizing atmosphere or surface polishing. If the density of these crystal defects (mainly oxygen precipitates) is exceeded, structural destruction of the device is likely to occur, and the yield of the device formed on the substrate will deteriorate.

【0018】このようなシリコン半導体基板の製造方法
としては、CZ法又は磁場印加CZ法により上述の条件
を満足する基板が得られる製造方法であれば良く、特に
限定するものではない。しかしながら、生産性良く効率
的に本発明のシリコン半導体基板を製造するためには、
1×1016atoms/cm3 以上1.5×1019at
oms/cm3 以下の窒素を含有するシリコン融液を用
いてCZ法又は磁場印加CZ法により育成したシリコン
単結晶から得たシリコン半導体基板を、1000℃以上
1300℃以下の温度で1時間以上熱処理することが望
ましい。窒素の偏析係数は7×10-4であり、1×10
16atoms/cm3 以上1.5×10 19atoms/
cm3 以下の窒素を含有するシリコン融液を用いれば1
×1013atoms/cm3 以上1×1016atoms
/cm3 以下の窒素を含有した結晶を育成し得る。
A method for manufacturing such a silicon semiconductor substrate
The above conditions are determined by the CZ method or the magnetic field applying CZ method.
Any manufacturing method can be used as long as a substrate that satisfies
It is not limited. However, with good productivity and efficiency
In order to manufacture the silicon semiconductor substrate of the present invention,
1 × 1016atoms / cmThree1.5 × 10 or more19at
oms / cmThreeUse a silicon melt containing the following nitrogen
Silicon grown by CZ method or CZ method applying magnetic field
A silicon semiconductor substrate obtained from a single crystal at a temperature of 1000 ° C. or higher
It is desirable to heat-treat at a temperature of 1300 ° C or less for 1 hour or more.
Good. The segregation coefficient of nitrogen is 7 × 10-FourAnd 1 × 10
16atoms / cmThree1.5 × 10 or more 19atoms /
cmThreeIf a silicon melt containing the following nitrogen is used,
× 1013atoms / cmThreeMore than 1 × 1016atoms
/ CmThreeThe following nitrogen-containing crystals can be grown.

【0019】また、CZ法もしくは磁場印加CZ法で結
晶を育成する際、引上速度をV(mm/min)とし、
シリコン融点から1300℃までの温度範囲における引
き上げ軸方向の結晶内温度勾配の平均値をG(℃/m
m)とするとき、V/G値を0.2(mm2 /℃mi
n)以上の条件のもとで、窒素を1×1016atoms
/cm3 以上1.5×1019atoms/cm3 以下含
有するシリコン融液より育成し(通常の引き上げ炉では
これは引上速度約1.5mm/min以上で、結晶中の
窒素濃度が1×1013atoms/cm3 以上1×10
16atoms/cm 3 に対応する)、その結晶から作成
した半導体基板を用いることにより、表面無欠陥領域
(DZ層)の深さを1μm以上より深くすることができ
る。
The CZ method or the magnetic field application CZ method
When growing a crystal, the pulling speed is set to V (mm / min),
Pull in the temperature range from the silicon melting point to 1300 ° C.
G (° C./m
m), the V / G value is 0.2 (mmTwo/ ℃ mi
n) Under the above conditions, 1 × 1016atoms
/ CmThree1.5 × 10 or more19atoms / cmThreeIncluding
Grown from a silicon melt that has
This is at a pulling speed of about 1.5 mm / min or more,
Nitrogen concentration is 1 × 1013atoms / cmThreeMore than 1 × 10
16atoms / cm ThreeCreated from the crystal)
Using a semiconductor substrate that has been
(DZ layer) can be made deeper than 1 μm.
You.

【0020】上記の様に結晶中に窒素を含有した結晶
は、酸素析出物が発生しているため、ウエハ表面の酸素
を外方拡散させるだけで欠陥をほぼ完全に消滅させるこ
とができる。また変容した空孔欠陥は不安定な形態を持
っており、熱処理により容易に消滅する。それに対し、
従来の結晶は空孔欠陥を消滅させなければならず、その
消滅にはシリコンの点欠陥の吸収放出及び結晶中の酸素
の析出・放出が複雑にからむためその熱処理パターンは
複雑になり、熱処理温度も1200℃程度の高温が必要
であり、また雰囲気として水素などの危険なガスを用い
ないとより完全に消滅させることはできない。本発明の
熱処理温度に関しては1000℃以上1300℃以下、
望ましくは1100℃以上1200℃以下が適当であ
る。温度が低いと酸素の外方拡散に多大の時間を要し、
温度が高すぎると結晶中の熱平衡酸素固溶度が上がり酸
素の外方拡散が起きなくなる。また、1150℃以上で
は高温になればなるほど基板表面の面荒れの問題が生じ
る。また一般的に、熱処理炉を高温で稼働させる際には
予期しない炉体の汚染が生じやすくなるため、その危険
性を減少させるためには熱処理温度を低くできることが
望ましい。従って、必要なDZ層の深さおよび経済的な
観点からの熱処理時間の許容時間を勘案しながら、表記
の温度範囲でできるだけ低い温度で熱処理することが望
ましい。
As described above, in the crystal containing nitrogen in the crystal, since oxygen precipitates are generated, defects can be almost completely eliminated only by outwardly diffusing oxygen on the wafer surface. Further, the transformed vacancy defect has an unstable form, and easily disappears by heat treatment. For it,
In conventional crystals, vacancy defects must be eliminated, and the elimination involves complicated absorption and release of silicon point defects and precipitation and release of oxygen in the crystal. Requires a high temperature of about 1200 ° C., and cannot be completely eliminated unless a dangerous gas such as hydrogen is used as the atmosphere. Regarding the heat treatment temperature of the present invention, 1000 ° C or higher and 1300 ° C or lower,
Desirably, the temperature is 1100 ° C or more and 1200 ° C or less. If the temperature is low, it takes a lot of time for oxygen to diffuse out,
If the temperature is too high, the thermal equilibrium solid solubility in the crystal will increase, preventing outward diffusion of oxygen. At 1150 ° C. or higher, the higher the temperature becomes, the more the surface of the substrate becomes rough. Generally, when the heat treatment furnace is operated at a high temperature, unexpected contamination of the furnace body is likely to occur. Therefore, it is desirable that the heat treatment temperature can be lowered to reduce the risk. Therefore, it is desirable to perform the heat treatment at a temperature as low as possible in the indicated temperature range, taking into account the required depth of the DZ layer and the allowable time of the heat treatment time from an economical viewpoint.

【0021】また、本発明のウエハにおいて内部の酸素
析出物は熱処理により成長するため、熱処理ウエハは内
部に高密度のゲッタリング層を持つことができる。通常
のこの様な表面にDZ層を持ち内部に高密度のゲッタリ
ング層を持つ、いわゆるIGウエハは3段の熱処理(酸
素の外方拡散+酸素析出核の形成+酸素析出物の形成)
によってのみ作成することができるが、本発明の製造方
法を用いれば、通常のIGウエハよりもより完全性が高
いDZ層を持ちかつ内部に高密度のゲッタリング層を持
つウエハを一回の熱処理で作成することが可能である。
In the wafer of the present invention, since the oxygen precipitate inside grows by heat treatment, the heat-treated wafer can have a high-density gettering layer inside. A so-called IG wafer having a DZ layer on such a surface and a high density gettering layer inside, so-called three-stage heat treatment (outward diffusion of oxygen + formation of oxygen precipitation nuclei + formation of oxygen precipitates)
However, if the manufacturing method of the present invention is used, a wafer having a DZ layer having higher integrity than a normal IG wafer and having a high density gettering layer therein can be subjected to a single heat treatment. It is possible to create with.

【0022】熱処理雰囲気としてはウエハ表面の酸素濃
度を効果的に低減でき、その結果窒素添加により発生し
た板状析出物を容易に消滅させることができる非酸化性
雰囲気が好ましい。非酸化性ガスとしては、経済性の観
点からアルゴンガスが望ましい。含有不純物純度、特に
ガス中の不純物酸素の量を減らすという点ではヘリウム
ガスを用いる利点があるが、経済性および、ヘリウムガ
スの大きな熱伝導性に由来する熱処理炉の取り扱いの難
しさの等の問題がある。窒素ガスは基板表面に窒化物を
形成するため不適当である。水素などの還元性雰囲気も
アルゴンガスと同等の効果を持つため使用することが可
能であるが、取り扱いの難しさ、特に爆発の危険性があ
ることから、必ずしも適当であるとは言えない。
The heat treatment atmosphere is preferably a non-oxidizing atmosphere in which the oxygen concentration on the wafer surface can be effectively reduced, and as a result, plate-like precipitates generated by the addition of nitrogen can be easily eliminated. As the non-oxidizing gas, an argon gas is desirable from the viewpoint of economy. Although the use of helium gas has the advantage of reducing the purity of the contained impurities, especially the amount of impurity oxygen in the gas, it is economical and difficult to handle the heat treatment furnace due to the large thermal conductivity of helium gas. There's a problem. Nitrogen gas is inappropriate because it forms nitride on the substrate surface. A reducing atmosphere such as hydrogen can be used because it has the same effect as argon gas, but it is not always suitable because of the difficulty of handling, especially the danger of explosion.

【0023】さらに付記すべきは、熱処理中に混入する
不純物の量をできる限り減らす必要があることである。
これは、試料の炉体内への挿入時を含む炉内雰囲気中の
酸素がDZ層の完全性や結晶表面の面荒れに大きな影響
を与えるためである。この点に関しては特願平9−29
7158号で指摘しているとおりである。また、これに
は不純物を低減することにより、表層の結晶の完全性を
より上げることができることを指摘しており、この効果
を用いて熱処理前に結晶表面に存在したCOPピットを
平滑化することが可能である。
It should be further noted that it is necessary to reduce the amount of impurities mixed during the heat treatment as much as possible.
This is because oxygen in the atmosphere in the furnace including when the sample is inserted into the furnace has a great effect on the integrity of the DZ layer and the surface roughness of the crystal surface. Regarding this point, Japanese Patent Application No. 9-29
As pointed out in No. 7158. It also points out that by reducing impurities, it is possible to further improve the crystallinity of the surface layer, and to use this effect to smooth the COP pits present on the crystal surface before heat treatment. Is possible.

【0024】雰囲気ガスとして非酸化性雰囲気ではな
く、酸素を0.01vol%以上100vol%以下含
む雰囲気を用いることもできるが、この場合は表面の再
研磨が必要である。酸素を混合させるメリットとしては
前節で指摘した、熱処理中に混入する水分などの不純物
の管理をゆるめることができることが挙げられる。具体
的な雰囲気としては、アルゴンなどの不活性ガス雰囲気
中に酸素を混合したガスが用いられる。混合させる酸素
の量としては数%が望ましいが、100vol%酸素ガ
スを用いることも可能である。混合量が0.01vol
%未満であると、雰囲気ガスへの水分などの不純物の混
入を厳密に管理せねばならなくなり、酸素を混合させる
メリットが無くなる。熱処理後のウエハ表面には、熱処
理中に発生した酸化膜により結晶欠陥の痕が、化学エッ
チングのピットのようにウエハ表面に発生するため、表
面の再研磨が必要である。欠陥痕を完全に除去するため
には表面を0.5μm以上研磨する必要がある。また、
再研磨量が1.0μmより大きいと、直径換算で0.1
μm以上の結晶欠陥の密度が104 個/cm3 以下であ
る表面無欠陥層の厚みを1μm以上とすることが困難で
ある。
The atmosphere gas may be an atmosphere containing not less than 0.01 vol% and not more than 100 vol% of oxygen instead of a non-oxidizing atmosphere. In this case, the surface needs to be polished again. The merit of mixing oxygen is that the management of impurities such as moisture mixed during the heat treatment, which was pointed out in the previous section, can be relaxed. As a specific atmosphere, a gas obtained by mixing oxygen in an inert gas atmosphere such as argon is used. Although the amount of oxygen to be mixed is preferably several percent, it is also possible to use 100 vol% oxygen gas. The mixing amount is 0.01 vol
If it is less than%, it is necessary to strictly control the mixing of impurities such as moisture into the atmosphere gas, and the merit of mixing oxygen is lost. On the wafer surface after the heat treatment, traces of crystal defects are generated on the wafer surface like chemical etching pits due to an oxide film generated during the heat treatment, and thus the surface needs to be polished again. In order to completely remove defect marks, the surface needs to be polished by 0.5 μm or more. Also,
When the re-polishing amount is larger than 1.0 μm, the re-polishing amount is 0.1% in terms of diameter.
it is difficult to density the more crystal defects μm is 10 4 / cm 3 or less is a thickness of the surface defect-free layer 1μm or more.

【0025】以上のように、結晶育成の際に窒素を含有
させた結晶を熱処理することにより、従来よりも単純、
安全かつプロセス汚染の可能性が少ない熱処理条件で、
従来の熱処理ウエハと同等以上の欠陥密度の低減、従来
以上の深さのDZ層を得ることができる。
As described above, the heat treatment of the crystal containing nitrogen during the growth of the crystal makes it simpler than the conventional one.
Under heat treatment conditions that are safe and have little possibility of process contamination,
It is possible to obtain a DZ layer having a reduced defect density equal to or higher than that of a conventional heat-treated wafer and a depth higher than that of the conventional heat-treated wafer.

【0026】[0026]

【実施例】以下、実施例で本発明を具体的に説明する。The present invention will be specifically described below with reference to examples.

【0027】(参考例)参考例としてチョクラルスキー
法により以下の8つの結晶を引き上げた。酸素濃度は約
6.5〜8.5×1017atomos/cm3(赤外吸
収法によりJEIDAの換算係数を用いて測定)であっ
た。いずれの結晶も約40kgの原料を溶解し、直径1
55mmの約30kgのインゴットを作成し、p型10
Ωcmの結晶を得た。窒素の添加はノンドープのシリコ
ン結晶にCVD法により窒化膜を形成したウエハを、原
料の溶解時に同時に溶かすことにより行った。
Reference Example As a reference example, the following eight crystals were pulled up by the Czochralski method. The oxygen concentration was about 6.5 to 8.5 × 10 17 atoms / cm 3 (measured by an infrared absorption method using a conversion coefficient of JEIDA). Each crystal dissolves about 40 kg of raw material and has a diameter of 1
Create 55mm ingot of about 30kg, p-type 10
A crystal of Ωcm was obtained. Nitrogen was added by simultaneously dissolving a wafer having a nitride film formed on a non-doped silicon crystal by a CVD method at the time of dissolving the raw materials.

【0028】1) 窒素添加を行わず引上速度1mm/
minで結晶を育成した。
1) Pulling speed 1 mm / without adding nitrogen
A crystal was grown in min.

【0029】2) 原料の融液中に窒素を7×1015
toms/cm3 添加し、引上速度1mm/minで結
晶を育成した。このときのV/Gは0.15(mm2
℃min)である。結晶の窒素濃度をSIMSで測定し
たが、窒素は検出されず(1×1014atoms/cm
3 以下)、平衡偏析係数から窒素の濃度を計算すると、
結晶中に約5×1012atoms/cm3 となった。
2) 7 × 10 15 a of nitrogen in the melt of the raw material
toms / cm 3 was added, A crystal was grown at a pulling speed of 1mm / min. V / G at this time is 0.15 (mm 2 /
° C min). The nitrogen concentration of the crystal was measured by SIMS, but no nitrogen was detected (1 × 10 14 atoms / cm).
3 or less), and calculating the nitrogen concentration from the equilibrium segregation coefficient,
It was about 5 × 10 12 atoms / cm 3 in the crystal.

【0030】3) 原料の融液中に窒素を5×1016
toms/cm3 添加し、引上速度1mm/minで結
晶を育成した。このときのV/Gは0.15(mm2
℃min)である。結晶の窒素濃度をSIMSで測定し
たが、窒素は検出されず(1×1014atoms/cm
3 以下)、平衡偏析係数から窒素の濃度を計算すると、
結晶中に約4×1013atoms/cm3 となった。
3) Nitrogen in the melt of the raw material is 5 × 10 16 a
toms / cm 3 was added, A crystal was grown at a pulling speed of 1mm / min. V / G at this time is 0.15 (mm 2 /
° C min). The nitrogen concentration of the crystal was measured by SIMS, but no nitrogen was detected (1 × 10 14 atoms / cm).
3 or less), and calculating the nitrogen concentration from the equilibrium segregation coefficient,
It was about 4 × 10 13 atoms / cm 3 in the crystal.

【0031】4) 原料の融液中に窒素を3×1017
toms/cm3 添加し、引上速度1mm/minで結
晶を育成した。このときのV/Gは0.15(mm2
℃min)である。平衡偏析係数から窒素の濃度を計算
すると、結晶中に約2×10 14atoms/cm3 とな
った。結晶の窒素濃度をSIMSで測定すると、窒素を
定量することはできなかったが、窒素のバックグラウン
ドレベルの2倍以上の強度で局所的な窒素信号の増大が
認められた。
4) Nitrogen in the melt of the raw material is 3 × 1017a
toms / cmThreeAt a pulling speed of 1 mm / min.
A crystal was grown. V / G at this time is 0.15 (mmTwo/
° C min). Calculate nitrogen concentration from equilibrium segregation coefficient
Then, about 2 × 10 14atoms / cmThreeTona
Was. When the nitrogen concentration of the crystal was measured by SIMS,
Quantification was not possible, but nitrogen background
Increase of local nitrogen signal at twice the intensity of
Admitted.

【0032】5) 原料の融液中に窒素を5×1017
toms/cm3 添加し、引上速度1mm/minで結
晶を育成した。このときのV/Gは0.15(mm2
℃min)である。結晶の窒素濃度をSIMSで測定し
た結果、結晶中の窒素濃度は約5×1014atoms/
cm3 であった。またこのSIMS測定の際、平均的な
窒素の信号に対して、2倍以上に局所的に増加する窒素
濃度の増大が認められた。
5) Nitrogen in the melt of the raw material is 5 × 10 17 a
toms / cm 3 was added, A crystal was grown at a pulling speed of 1mm / min. V / G at this time is 0.15 (mm 2 /
° C min). As a result of measuring the nitrogen concentration of the crystal by SIMS, the nitrogen concentration in the crystal was about 5 × 10 14 atoms /
cm 3 . At the time of this SIMS measurement, an increase in the nitrogen concentration that was locally increased twice or more with respect to the average nitrogen signal was observed.

【0033】6) 原料の融液中に窒素を5×1017
toms/cm3 添加し、引上速度2mm/minで結
晶を育成した。このときのV/Gは0.3(mm2 /℃
min)である。結晶の窒素濃度をSIMSで測定した
結果、結晶中の窒素濃度は約5×1014atoms/c
3 であった。またこのSIMS測定の際、平均的な窒
素の信号に対して、2倍以上に局所的に増加する窒素濃
度の増大が認められた。
6) Nitrogen in the melt of the raw material is 5 × 10 17 a
toms / cm 3 was added, A crystal was grown at a pulling speed of 2mm / min. V / G at this time is 0.3 (mm 2 / ° C.)
min). Result of nitrogen concentration in the crystal was measured by SIMS, the nitrogen concentration in the crystal is about 5 × 10 14 atoms / c
m 3 . At the time of this SIMS measurement, an increase in the nitrogen concentration that was locally increased twice or more with respect to the average nitrogen signal was observed.

【0034】7) 原料の融液中に窒素を5×1018
toms/cm3 添加し、引上速度1mm/minで結
晶を育成した。このときのV/Gは0.15(mm2
℃min)である。結晶の窒素濃度をSIMSで測定し
た結果、結晶中の窒素濃度は約5×1015atoms/
cm3 であった。またこのSIMS測定の際、平均的な
窒素の信号に対して、2倍以上に局所的に増加する窒素
濃度の増大が認められた。
7) Nitrogen in the melt of the raw material is 5 × 10 18 a
toms / cm 3 was added, A crystal was grown at a pulling speed of 1mm / min. V / G at this time is 0.15 (mm 2 /
° C min). As a result of measuring the nitrogen concentration of the crystal by SIMS, the nitrogen concentration in the crystal was about 5 × 10 15 atoms /
cm 3 . At the time of this SIMS measurement, an increase in the nitrogen concentration that was locally increased twice or more with respect to the average nitrogen signal was observed.

【0035】8) 原料の融液中に窒素を2×1019
toms/cm3 添加し、引上速度1mm/minで結
晶を育成した。途中結晶がポリ化したが、インゴットの
上部から無転位の単結晶が得られた。結晶の窒素濃度を
SIMSで測定した結果、結晶中の窒素濃度は約1.5
×1016atoms/cm3 であった。またこのSIM
S測定の際、平均的な窒素の信号に対して、2倍以上に
局所的に増加する窒素濃度の増大が認められた。
8) Nitrogen is added to the raw material melt at 2 × 10 19 a
toms / cm 3 was added, A crystal was grown at a pulling speed of 1mm / min. The crystal was polycrystallized on the way, but a dislocation-free single crystal was obtained from the upper part of the ingot. As a result of measuring the nitrogen concentration of the crystal by SIMS, the nitrogen concentration in the crystal was about 1.5.
× 10 16 atoms / cm 3 . Also this SIM
At the time of the S measurement, an increase in the nitrogen concentration which was locally increased twice or more with respect to the average nitrogen signal was observed.

【0036】以上の各結晶から作成したウエハのCOP
密度を測定したところ表1のようになった。
The COP of a wafer prepared from each of the above crystals
Table 1 shows the measured densities.

【0037】(実施例1)参考例5)および参考例7)
のウエハを本発明の熱処理条件により処理を行った。8
00℃で炉内に挿入し、挿入後10℃/minで昇温し
1100℃で8時間保持した後、−10℃/minで降
温し800℃で基板を取り出した。熱処理に用いたガス
はコールドエバポレーターにより供給されたアルゴンガ
スをユースポイントで純化装置により生成したガスを用
いた。ガス中の不純物濃度は5ppm以下であった。こ
のガスを上記熱処理を通して雰囲気として用いた。また
基板の挿入時には炉前に設けられたパージボックスによ
りパージを行い、試料を待機させている炉前の雰囲気が
不純物5ppm以下のアルゴン雰囲気になったことを確
認した後、炉口を開け、基板を挿入した。
(Example 1) Reference examples 5) and 7)
Was processed under the heat treatment conditions of the present invention. 8
After being inserted into the furnace at 00 ° C., the temperature was raised at 10 ° C./min after the insertion and maintained at 1100 ° C. for 8 hours, then lowered at −10 ° C./min, and the substrate was taken out at 800 ° C. As a gas used for the heat treatment, a gas produced by a purifier at a use point using argon gas supplied by a cold evaporator was used. The impurity concentration in the gas was 5 ppm or less. This gas was used as an atmosphere throughout the heat treatment. At the time of inserting the substrate, purging was performed by a purge box provided in front of the furnace, and after confirming that the atmosphere in front of the furnace in which the sample was on standby was an argon atmosphere with impurities of 5 ppm or less, the furnace port was opened and the substrate was opened. Was inserted.

【0038】熱処理後の基板厚み中心の窒素濃度は、基
板を劈開してSIMSで測定したところ、約5×1014
atoms/cm3 であった。
The nitrogen concentration of the substrate thickness center after heat treatment was measured by SIMS and cleaving the substrate, about 5 × 10 14
atoms / cm 3 .

【0039】熱処理後の基板表面のDZ層の品質を評価
するために、熱処理後の各基板表面に1000℃の乾燥
酸素雰囲気で25nmの酸化膜を形成し、酸化膜耐圧を
測定した。耐圧測定に用いた電極は20mm2 のポリシ
リコン電極であり、判定電流は1μAである。結果を表
3に示す。良品の割合を示す8MV以上の耐圧を示した
いわゆるCモード破壊を示した酸化膜の割合は99%と
ほぼ全ての酸化膜が良品であり、熱処理を行わなかった
場合の20%に比べ大幅な改善が認められた。また判定
電流100mAで11MV以上の耐圧を示したものの割
合は95%であった。
In order to evaluate the quality of the DZ layer on the substrate surface after the heat treatment, a 25 nm oxide film was formed on each substrate surface after the heat treatment in a dry oxygen atmosphere at 1000 ° C., and the oxide film breakdown voltage was measured. The electrode used for the breakdown voltage measurement was a 20 mm 2 polysilicon electrode, and the determination current was 1 μA. Table 3 shows the results. The percentage of oxide films showing so-called C-mode breakdown showing a breakdown voltage of 8 MV or more indicating the percentage of non-defective products is 99%, and almost all oxide films are non-defective products, which is much larger than 20% when no heat treatment is performed. Improvement was noted. Further, the ratio of those showing a withstand voltage of 11 MV or more at a judgment current of 100 mA was 95%.

【0040】さらに熱処理後の欠陥密度を調べるため、
改めて上記と同じ熱処理を行った基板を作成し、アンモ
ニア過酸化水素水洗浄を繰り返して表面を合計0.1μ
mエッチングし、この際に増加した直径換算0.1μm
以上のCOPの数より欠陥密度を算出した。結果を表2
に示す。熱処理後の表面のCOP密度は14個/ウエハ
であり、約0.1個/cm2 であった。さらにアンモニ
ア過酸化水素水洗浄を繰り返してもCOPの数は14個
/ウエハであり、COPの増加は認められなかった。こ
のことから、直径換算で0.1μm以上の結晶欠陥の密
度は103 個/cm3 未満であることがわかった。
Further, to examine the defect density after the heat treatment,
Create a substrate that has been subjected to the same heat treatment as above, and repeat the ammonia hydrogen peroxide solution cleaning to make the surface a total of 0.1 μm.
m, and the diameter is increased by 0.1 μm
The defect density was calculated from the above number of COPs. Table 2 shows the results
Shown in The COP density on the surface after the heat treatment was 14 / wafer, and was about 0.1 / cm 2 . Furthermore, the number of COPs was 14 / wafer even when the ammonia hydrogen peroxide water cleaning was repeated, and no increase in COP was observed. From this, it was found that the density of crystal defects having a diameter of 0.1 μm or more was less than 10 3 / cm 3 .

【0041】このウエハのDZ層内の欠陥の密度を調べ
るため、この基板の表面を鏡面研磨により1μm研磨
し、COPの測定を行った。鏡面研磨後には0.1μm
以上のCOPは20個/ウエハであったが、アンモニア
過酸化水素水洗浄を繰り返すことにより表面を0.1μ
mエッチングした後に0.1μm以上のCOPを測定す
ると25個/ウエハであり、直径換算で0.1μm以上
の結晶欠陥の密度は約3×103 個/cm3 であった。
In order to examine the density of defects in the DZ layer of the wafer, the surface of the substrate was polished by mirror polishing to 1 μm, and the COP was measured. 0.1 μm after mirror polishing
The above COP was 20 wafers / wafer, but the surface was reduced to 0.1 μm by repeating washing with aqueous ammonia and hydrogen peroxide.
When the COP of 0.1 μm or more was measured after m etching, the number was 25 / wafer, and the density of crystal defects of 0.1 μm or more in diameter conversion was about 3 × 10 3 / cm 3 .

【0042】この1μm研磨した状態での酸化膜耐圧を
測るために、上記と同様な酸化膜耐圧測定を行った。判
定電流は1μAで8MV以上の耐圧を示した酸化膜の割
合は95%と99%であり、判定電流100mAで11
MV以上の耐圧を示したものの割合はいずれも92%で
あった。
In order to measure the withstand voltage of the oxide film in the polished state of 1 μm, the withstand voltage of the oxide film was measured in the same manner as described above. The ratio of the oxide film showing a withstand voltage of 8 MV or more at 1 μA was 95% and 99%, and 11% at a determination current of 100 mA.
The ratio of those showing a withstand voltage of MV or more was 92%.

【0043】さらに深いところのCOPの密度を測定す
るためにさらに2μm鏡面研磨を行い(元の表面から計
3μm)、0.1μm以上のCOPの密度を測定すると
20個/ウエハであった。前節と同様に、アンモニア過
酸化水素洗浄を繰り返し0.1μmエッチングした後C
OPを測定するとの70個/ウエハであった。このこと
から表面下3μmの直径換算で0.1μm以上の結晶欠
陥の密度は3×104個/cm3 と見積もられた。
In order to measure the density of the COP at a deeper place, mirror polishing was further performed for 2 μm (total 3 μm from the original surface), and the density of the COP of 0.1 μm or more was 20 / wafer. As described in the previous section, cleaning with ammonia and hydrogen peroxide is repeated, and after etching 0.1 μm, C
The OP was 70 / wafer when measured. From this, the density of crystal defects having a diameter of 0.1 μm or more in terms of a diameter of 3 μm below the surface was estimated to be 3 × 10 4 / cm 3 .

【0044】基板内部での欠陥密度を測定するために、
赤外トモグラフにより基板厚み中心の直径換算で0.2
μm以上の欠陥の密度を測定したところ7x106個/
cm3 であり、0.1μm以上の欠陥密度はさらに多く
なる。この基板の表面から深さ0.1μmにおける欠陥
密度は103 個/cm3 未満であることから、基板内部
に比べ1%以下の欠陥密度であることがわかった。
In order to measure the defect density inside the substrate,
0.2 in terms of diameter at substrate thickness center by infrared tomography
When the density of defects having a size of μm or more was measured, 7 × 106Pieces/
cmThree And the defect density of 0.1 μm or more is more
Become. Defects at a depth of 0.1 μm from the surface of this substrate
Density is 10ThreePieces / cmThreeLess than
It was found that the defect density was 1% or less as compared with.

【0045】なお、このウエハは、基板内部においても
積層欠陥等の別種の欠陥も認められず、高品質なシリコ
ンウエハであることが確認された。
This wafer did not show any other kind of defects such as stacking faults inside the substrate, and was confirmed to be a high quality silicon wafer.

【0046】(実施例2)参考例6)のウエハを本発明
の熱処理条件により処理を行った。実施例1の熱処理と
同等の熱処理を参考例6)の結晶から作成したウエハに
施した。熱処理後基板を劈開しSIMSにより基板厚み
中心の窒素濃度を測定したところ約5×1014atom
s/cm3 であった。
Example 2 The wafer of Reference Example 6) was processed under the heat treatment conditions of the present invention. A heat treatment equivalent to the heat treatment of Example 1 was performed on the wafer prepared from the crystal of Reference Example 6). After the heat treatment, the substrate was cleaved, and the nitrogen concentration at the center of the substrate thickness was measured by SIMS to be about 5 × 10 14 atoms.
s / cm 3 .

【0047】同様に熱処理を行ったウエハの表面の0.
1μm以上のCOPを測定した(表2)ところ12個/
ウエハであり、約0.1個/cm2 であった。さらにア
ンモニア過酸化水素水洗浄を繰り返し、表面を0.1μ
mエッチングした後測定を行っても数は変化せず12個
/ウエハであった。このことから、熱処理によりウエハ
表面の直径換算で0.1μm以上の結晶欠陥の密度は1
×103 個/cm3 未満であることがわかった。
Similarly, the surface of the wafer subjected to the heat treatment was treated with a.
When COPs of 1 μm or more were measured (Table 2), 12
The number of wafers was about 0.1 / cm 2 . Repeat the washing with ammonia and hydrogen peroxide solution to make the surface 0.1μ
The number did not change even when the measurement was performed after m etching, and the number was 12 / wafer. From this, the density of crystal defects of 0.1 μm or more in terms of the diameter of the wafer surface due to the heat treatment is 1%.
It was found to be less than × 10 3 pieces / cm 3 .

【0048】実施例1と同様に熱処理後の酸化膜耐圧を
調べた(表3)ところ、判定電流1μAで8MV以上の
割合が99%であり、判定電流100mAで11MV以
上の耐圧を示したものの割合は95%であった。
The breakdown voltage of the oxide film after the heat treatment was examined in the same manner as in Example 1 (Table 3). As a result, the ratio of 8 MV or more at a judgment current of 1 μA was 99%, and the breakdown voltage of 11 MV or more was shown at a judgment current of 100 mA. The proportion was 95%.

【0049】このウエハのDZ層内の欠陥の密度を調べ
るため、この基板の表面を鏡面研磨により1μm研磨
し、COPの測定を行った。鏡面研磨後には0.1μm
以上のCOPは10個/ウエハであったが、アンモニア
過酸化水素水洗浄を繰り返すことにより表面を0.1μ
mエッチングした後0.1μm以上のCOPを測定する
と10個/ウエハであり、深さ1μmの領域でも直径換
算で0.1μm以上の結晶欠陥の密度は1×103 個/
cm3 未満であった。
To examine the density of defects in the DZ layer of this wafer, the surface of this substrate was polished by mirror polishing to 1 μm, and the COP was measured. 0.1 μm after mirror polishing
The above COP was 10 wafers / wafer, but the surface was reduced to 0.1 μm by repeating washing with aqueous ammonia and hydrogen peroxide.
After etching, the number of COPs of 0.1 μm or more is 10 / wafer, and the density of crystal defects of 0.1 μm or more in terms of diameter is 1 × 10 3 / wafer even in the region of 1 μm.
cm 3 .

【0050】1μm研磨の状態での酸化膜耐圧を調べた
ところ、判定電流1μAで8MV以上の割合が99%で
あり、判定電流100mAで11MV以上の耐圧を示し
たものの割合は95%であった。このことから、酸化膜
耐圧の観点からも熱処理後の最表面と深さ1μmでの結
晶の状態がほぼ同等であることがわかった。
When the oxide film breakdown voltage in the state of 1 μm polishing was examined, the ratio of 8 MV or more at a decision current of 1 μA was 99%, and the ratio of those showing a breakdown voltage of 11 MV or more at a decision current of 100 mA was 95%. . From this, it was found that the state of the crystal at the depth of 1 μm was almost the same as the outermost surface after the heat treatment from the viewpoint of the oxide film breakdown voltage.

【0051】さらに、DZ内部の欠陥の状態を調べるた
めに鏡面研磨によりさらに2μm(最初の表面より3μ
m)を研磨し、研磨後の0.1μm以上のCOPを測定
すると16個/ウエハであった。アンモニア過酸化水素
水洗浄を繰り返し、表面を0.1μmエッチングした後
測定を行うと21個/ウエハであり、直径換算で0.1
μm以上の結晶欠陥の密度は3×103 個/cm3 と見
積もられた。また酸化膜耐圧の値は判定電流1μAで8
MV以上の割合が95%であり、判定電流100mAで
11MV以上の耐圧を示したものの割合は90%であっ
た。従って、実施例1の結果と比較すると、結晶育成時
の引上速度を速めることにより表面からより深くまで欠
陥を消滅させることができることが示された。
Further, in order to examine the state of the defect inside the DZ, a further 2 μm (3 μm from the initial surface) was obtained by mirror polishing.
m) was polished, and the measured COP of 0.1 μm or more after polishing was 16 / wafer. Repeating the washing with an aqueous solution of ammonia and hydrogen peroxide and etching the surface to 0.1 μm, the measurement is 21 / wafer, which is 0.1 in terms of diameter.
The density of crystal defects of μm or more was estimated to be 3 × 10 3 / cm 3 . The oxide film breakdown voltage is 8 at a judgment current of 1 μA.
The ratio of MV or higher was 95%, and the ratio of those showing a withstand voltage of 11 MV or higher at a judgment current of 100 mA was 90%. Therefore, as compared with the result of Example 1, it was shown that the defects can be eliminated deeper from the surface by increasing the pulling speed during crystal growth.

【0052】基板内部での欠陥密度を測定するために、
赤外トモグラフにより基板厚み中心の直径換算で0.2
μm以上の欠陥の密度を測定したところ9x106個/
cm3 であり、0.1μm以上の欠陥密度はさらに多く
なる。この基板の表面から深さ0.1μmにおける欠陥
密度は1×103 個/cm3 未満であることから、基板
内部に比べ1%以下の欠陥密度であることがわかった。
In order to measure the defect density inside the substrate,
0.2 in terms of diameter at substrate thickness center by infrared tomography
When the density of the defects of μm or more was measured, it was 9 × 106Pieces/
cmThree And the defect density of 0.1 μm or more is more
Become. Defects at a depth of 0.1 μm from the surface of this substrate
Density is 1 × 10ThreePieces / cmThreeLess than the substrate
It was found that the defect density was 1% or less as compared with the inside.

【0053】なお、このウエハは、実施例1と同様に基
板内部においても積層欠陥等の別種の欠陥も認められ
ず、高品質なシリコンウエハであることが確認された。
It should be noted that, as in Example 1, no other kinds of defects such as stacking faults were found inside the substrate as in Example 1, and it was confirmed that the wafer was a high quality silicon wafer.

【0054】(参考例9)参考例6)の結晶から作成し
たシリコン基板を800℃で炉内に挿入し、挿入後10
℃/minで昇温し1100℃で8時間保持した後、−
10℃/minで降温し800℃で基板を取り出した。
但し、実施例1と異なり、挿入時以降の熱処理雰囲気を
5%の酸素を含むアルゴン雰囲気とした。熱処理後の基
板の厚み中心の窒素濃度を実施例1と同様に測定したと
ころ約5×1014atoms/cm 3 であった。
(Reference Example 9) Prepared from the crystal of Reference Example 6)
Inserted silicon substrate into furnace at 800 ° C.
After raising the temperature at 1100 ° C and holding at 1100 ° C for 8 hours,
The temperature was lowered at 10 ° C./min, and the substrate was taken out at 800 ° C.
However, unlike the first embodiment, the heat treatment atmosphere after the insertion is changed to
An argon atmosphere containing 5% oxygen was used. Base after heat treatment
The nitrogen concentration at the center of the thickness of the plate was measured in the same manner as in Example 1.
Roller about 5 × 1014atoms / cm ThreeMet.

【0055】熱処理後の基板表面のDZ層の品質を評価
するために、上記と同様な酸化膜耐圧の測定を行った
(表3)ところ、判定電流1μAでは8MV以上の耐圧
を示した割合は90%であり、実施例1に記載の非酸化
性雰囲気で熱処理した場合に比べ劣っていた。また判定
電流100mAで11MV以上の耐圧を示したものは1
7%であった。
In order to evaluate the quality of the DZ layer on the substrate surface after the heat treatment, the oxide film breakdown voltage was measured in the same manner as described above (Table 3). 90%, which was inferior to the case of heat treatment in the non-oxidizing atmosphere described in Example 1. In addition, one showing a withstand voltage of 11 MV or more at a judgment current of 100 mA is 1
7%.

【0056】熱処理後の0.1μm以上のCOPを調べ
るために、改めて上記と同じ熱処理を行った基板を作成
した。熱処理後の表面のCOP密度は約6000個/ウ
エハであり、40個/cm2 であった。さらに、アンモ
ニア過酸化水素水洗浄を繰り返すことにより表面を0.
1μmエッチングしたのち0.1μm以上のCOPを測
定してもCOPの増加は誤差の範囲内であり、欠陥はほ
ぼ消滅していると考えられるものの、繰り返し洗浄前で
も存在していた6000個/ウエハのCOPのために正
確なCOP体積密度を求めることはできなかった。
In order to examine the COP of 0.1 μm or more after the heat treatment, a substrate which was subjected to the same heat treatment as above was prepared again. The COP density on the surface after the heat treatment was about 6000 / wafer, and was 40 / cm 2 . Further, the surface is reduced to 0. 0 by repeating washing with ammonia hydrogen peroxide solution.
Even if a COP of 0.1 μm or more is measured after the etching of 1 μm, the increase in the COP is within the range of the error, and the defect is considered to have almost disappeared. It was not possible to determine the exact COP volume density for the COP.

【0057】このように酸素を含む雰囲気で熱処理を施
したままの基板表面には、結晶欠陥痕が発生するため、
十分な品質を確保できないことがわかる。
As described above, since crystal defect marks are generated on the surface of the substrate which has been subjected to the heat treatment in the atmosphere containing oxygen,
It turns out that sufficient quality cannot be secured.

【0058】(実施例3)参考例9で得られた基板につ
いて、表面の欠陥痕を取り除くため熱処理後表面を1μ
m鏡面研磨した基板を作成した。研磨後の表面の0.1
μm以上のCOPは14個/ウエハであり、約0.1個
/cm2 であった。さらにアンモニア過酸化水素水洗浄
を同様に繰り返してCOPの体積密度を測定すると1×
103 個/cm3 であった(表2)。1μm研磨後のウ
エハに作成した酸化膜の耐圧を調べた(表3)ところ、
判定電流1μAでの8MV以上の割合が95%、100
mAで11MV以上のものが90%であった。
(Example 3) The substrate obtained in Reference Example 9 was heat treated to remove 1 μm of the surface in order to remove surface defect marks.
A mirror-polished substrate was prepared. 0.1 after polishing
The number of COPs of μm or more was 14 / wafer, and was about 0.1 / cm 2 . Further, the washing with ammonia hydrogen peroxide was repeated in the same manner to measure the volume density of COP.
10 was 3 / cm 3 (Table 2). The breakdown voltage of the oxide film formed on the wafer after polishing by 1 μm was examined (Table 3).
The ratio of 8 MV or more at a judgment current of 1 μA is 95%, 100
90% were those with 11 MV or more in mA.

【0059】この熱処理後1μm研磨した基板の深さ方
向の欠陥分布を調べるため、さらに、表面を1μm追加
研磨をおこなった(熱処理前の基板表面から合計2μm
の研磨)。この基板の直径換算で0.1μm以上の結晶
欠陥の密度をアンモニア過酸化水素水の繰り返し洗浄に
より測定すると、9×103 個/cm3 であった。酸化
膜の耐圧を調べたところ、判定電流1μAでの8MV以
上の割合が90%、100mAで11MV以上のものが
85%であった。
In order to examine the defect distribution in the depth direction of the substrate polished 1 μm after this heat treatment, the surface was further polished by 1 μm (total 2 μm from the substrate surface before the heat treatment).
Polishing). When the density of crystal defects having a diameter of 0.1 μm or more in terms of the diameter of this substrate was measured by repeated washing with aqueous ammonia and hydrogen peroxide, it was 9 × 10 3 / cm 3 . When the breakdown voltage of the oxide film was examined, the ratio of 8 MV or more at a judgment current of 1 μA was 90%, and the ratio of 11 MV or more at 100 mA was 85%.

【0060】基板内部での欠陥密度を測定するために、
赤外トモグラフにより基板厚み中心の直径換算で0.2
μm以上の欠陥の密度を測定したところ9x106個/
cm3 であり、0.1μm以上の欠陥密度はさらに多く
なる。この基板の表面から深さ0.1μmにおける欠陥
密度は1×103 個/cm3 であることから、基板内部
に比べ1%以下の欠陥密度であることがわかった。
In order to measure the defect density inside the substrate,
0.2 in terms of diameter at substrate thickness center by infrared tomography
When the density of the defects of μm or more was measured, it was 9 × 106Pieces/
cmThree And the defect density of 0.1 μm or more is more
Become. Defects at a depth of 0.1 μm from the surface of this substrate
Density is 1 × 10ThreePieces / cmThreeFrom the inside of the board
It was found that the defect density was 1% or less as compared with.

【0061】以上の結果から、熱処理後のウエハを1μ
m研磨して表面のCOPを除去することにより、直径換
算で0.1μm以上の結晶欠陥の密度が1×104 個/
cm 3 以下である無欠陥層の深さが1μm以上であるウ
エハが作成できることがわかった。
From the above results, the wafer after heat treatment was 1 μm.
By removing the COP on the surface by polishing,
Calculated that the density of crystal defects of 0.1 μm or more is 1 × 10FourPieces/
cm ThreeC) where the depth of the defect-free layer is 1 μm or more
It turns out that Eha can be created.

【0062】なお、このウエハも、基板内部において積
層欠陥等の別種の欠陥も認められず、高品質なシリコン
ウエハであることが確認された。
Further, this wafer did not show any other kind of defects such as stacking faults inside the substrate, and was confirmed to be a high quality silicon wafer.

【0063】(参考例10)実施例3の基板をさらに1
μm研磨(熱処理前の基板表面から3μm)後、同様に
直径換算で0.1μm以上の結晶欠陥の密度を測定する
と7×105 個/cm3 であり(表2)、酸化膜耐圧は
判定電流1μAでの8MV以上の割合が75%、100
mAで11MV以上のものが30%であり(表3)、過
剰な研磨を施すと、特性が劣化することもわかった。
Reference Example 10 The substrate of Example 3
After polishing by μm (3 μm from the surface of the substrate before heat treatment), similarly, the density of crystal defects having a diameter of 0.1 μm or more was measured to be 7 × 10 5 / cm 3 (Table 2). The ratio of 8 MV or more at a current of 1 μA is 75%, 100%
30% was obtained at 11 MV or more in mA (Table 3), and it was also found that the property was deteriorated when excessive polishing was performed.

【0064】(比較例1)参考例の結晶の酸化膜耐圧の
特性を上記と同様な方法で評価した。その結果を表4に
示す。
Comparative Example 1 The oxide film breakdown voltage characteristics of the crystal of the reference example were evaluated in the same manner as described above. Table 4 shows the results.

【0065】(比較例2)参考例1)、2)の結晶に対
して実施例1の熱処理を行い、表面及び深さ1μm、3
μmのCOP密度及び酸化膜耐圧の測定した結果を表
5、6に示す。いずれの場合も深さ1μmでの直径換算
で0.1μm以上の結晶欠陥の密度が1×104 個/c
3 をこえており、また酸化膜耐圧の値も実施例に比べ
悪くなっていることがわかる。
(Comparative Example 2) The crystals of Reference Examples 1) and 2) were subjected to the heat treatment of Example 1 to obtain a surface and a depth of 1 μm.
Tables 5 and 6 show the measurement results of the COP density of μm and the withstand voltage of the oxide film. In each case, the density of crystal defects having a diameter of 0.1 μm or more in terms of diameter at a depth of 1 μm is 1 × 10 4 / c.
m 3 , and the value of the oxide film breakdown voltage is lower than that of the example.

【0066】(比較例3)参考例8)の結晶に対し実施
例1の熱処理を行い、表面及び深さ1μm、3μmのC
OP密度及び酸化膜耐圧の測定した結果を表5、6に示
す。直径換算で0.1μm以上のCOP密度は本発明の
範囲であり、また実施例1にくらべ酸化膜耐圧もほぼ同
等であったものの、結晶内部に発生した直径約10μm
の積層欠陥が基板内部より表面まで突き出していて、基
板表面における直径換算0.1μm以上の結晶欠陥の面
密度が5個/cm2 であり、深さ1μmまでの直径換算
0.1μm以上の結晶欠陥の体積密度としては5×10
4 個/cm3 となり、デバイスの作成には適さない基板
となっていた。
(Comparative Example 3) The crystal of Reference Example 8) was subjected to the heat treatment of Example 1, and the surface and the depth of 1 μm and 3 μm of C
Tables 5 and 6 show the measurement results of the OP density and the oxide film breakdown voltage. A COP density of 0.1 μm or more in terms of diameter is within the scope of the present invention, and although the oxide film breakdown voltage is almost the same as in Example 1, a diameter of about 10 μm generated inside the crystal is obtained.
Stacking faults protrude from the inside of the substrate to the surface, the surface density of crystal defects with a diameter of 0.1 μm or more on the substrate surface is 5 / cm 2 , and a crystal with a diameter of 0.1 μm or more up to a depth of 1 μm. The volume density of defects is 5 × 10
It was 4 wafers / cm 3 , making the substrate unsuitable for device fabrication.

【0067】(実施例4)参考例3)、4)の結晶を実
施例1の熱処理を行い、表面及び深さ1μm、3μmの
COP密度及び酸化膜耐圧の測定した結果を表7、8に
示す。熱処理後に基板を劈開しSIMSにより基板厚み
中心の窒素濃度を測定したが、参考例3)、4)いずれ
の結晶も、窒素の定量はできなかった。しかしながら、
バックグラウンドの信号強度の2倍以上の信号強度で窒
素の局所的な信号の増大が認められた。
(Example 4) The crystals of Reference Examples 3) and 4) were subjected to the heat treatment of Example 1 and the results of measuring the surface and COP densities of 1 μm and 3 μm in depth and oxide film breakdown voltage are shown in Tables 7 and 8. Show. After the heat treatment, the substrate was cleaved and the nitrogen concentration at the center of the substrate thickness was measured by SIMS. However, nitrogen could not be quantified in any of Reference Examples 3) and 4). However,
At a signal intensity more than twice the background signal intensity, a local increase in the nitrogen signal was observed.

【0068】[0068]

【表1】 [Table 1]

【0069】[0069]

【表2】 [Table 2]

【0070】[0070]

【表3】 [Table 3]

【0071】[0071]

【表4】 [Table 4]

【0072】[0072]

【表5】 [Table 5]

【0073】[0073]

【表6】 [Table 6]

【0074】[0074]

【表7】 [Table 7]

【0075】[0075]

【表8】 [Table 8]

【0076】[0076]

【発明の効果】本発明のシリコン半導体基板は、デバイ
ス形成領域の結晶欠陥が極めて少ないので、基板上に作
成される半導体デバイスの歩留りが向上するとともに、
その信頼性も高まるため、デバイス作成プロセスにおけ
る生産性向上並びにコスト低減に寄与すると言う効果を
有する。
The silicon semiconductor substrate of the present invention has very few crystal defects in the device formation region, so that the yield of semiconductor devices formed on the substrate can be improved,
Since the reliability is also improved, there is an effect that the productivity is improved and the cost is reduced in the device creation process.

【0077】また、本発明のシリコン半導体基板の製造
方法によれば、シリコン半導体基板中の空孔欠陥を効果
的に消滅させることができるとともに、酸素析出物もそ
の大きさが小さいために簡便な熱処理によって容易に消
滅できることから、半導体デバイス作成に必要な高品質
な単結晶表面層を有するシリコン半導体基板を生産性良
く製造することが可能となった。
Further, according to the method for manufacturing a silicon semiconductor substrate of the present invention, vacancy defects in the silicon semiconductor substrate can be effectively eliminated, and the size of the oxygen precipitate is small, so that the method is simple. Since it can be easily eliminated by heat treatment, it has become possible to manufacture a silicon semiconductor substrate having a high-quality single-crystal surface layer required for manufacturing a semiconductor device with high productivity.

───────────────────────────────────────────────────── フロントページの続き (72)発明者 坂本 光 神奈川県川崎市中原区井田3−35−1 新 日本製鐵株式会社技術開発本部内 (72)発明者 中居 克彦 神奈川県川崎市中原区井田3−35−1 新 日本製鐵株式会社技術開発本部内 (72)発明者 星野 泰三 山口県光市島田3434番地 ニッテツ電子株 式会社内 ────────────────────────────────────────────────── ─── Continuing from the front page (72) Inventor Hikaru Sakamoto 3-35-1, Ida, Nakahara-ku, Kawasaki-shi, Kanagawa Prefecture Inside the Technology Development Division of Nippon Steel Corporation (72) Inventor Katsuhiko Nakai Ida, Nakahara-ku, Kawasaki-shi, Kanagawa Prefecture 3-35-1 New Nippon Steel Corporation Technology Development Division (72) Inventor Taizo Hoshino 3434 Shimada, Hikari-shi, Yamaguchi Prefecture Nittetsu Electronics Co., Ltd.

Claims (9)

【特許請求の範囲】[Claims] 【請求項1】 チョクラルスキー法又は磁場印加チョク
ラルスキー法により育成したシリコン単結晶から得たシ
リコン半導体基板であって、少なくとも基板表面から深
さ1μmまでの領域において、直径換算で0.1μm以
上の結晶欠陥の密度が104 個/cm3 以下であること
を特徴とするシリコン半導体基板。
1. A silicon semiconductor substrate obtained from a silicon single crystal grown by a Czochralski method or a magnetic field application Czochralski method, wherein at least a region from the substrate surface to a depth of 1 μm has a diameter of 0.1 μm. A silicon semiconductor substrate, wherein the density of the above crystal defects is 10 4 / cm 3 or less.
【請求項2】 シリコン半導体基板の厚み中心における
窒素含有量が1×1013atoms/cm3 以上1×1
16atoms/cm3 以下である請求項1記載のシリ
コン半導体基板。
2. The method according to claim 1, wherein the nitrogen content at the center of the thickness of the silicon semiconductor substrate is 1 × 10 13 atoms / cm 3 or more and 1 × 1.
2. The silicon semiconductor substrate according to claim 1, wherein said silicon semiconductor substrate is at most 0 16 atoms / cm 3 .
【請求項3】 シリコン半導体基板の窒素含有量が1×
1016atoms/cm3 以下であり、かつ該基板中を
二次イオン質量分析法で測定した窒素濃度が、平均信号
強度の2倍以上の信号強度を示す窒素偏析による局所濃
化部を有する請求項1記載のシリコン半導体基板。
3. The silicon semiconductor substrate has a nitrogen content of 1 ×.
A local concentration portion due to nitrogen segregation that has a signal intensity of 10 16 atoms / cm 3 or less and the signal intensity of the substrate measured by secondary ion mass spectrometry is at least twice the average signal intensity. Item 2. The silicon semiconductor substrate according to Item 1.
【請求項4】 シリコン半導体基板の厚み中心における
窒素含有量が1×1013atoms/cm3 以上1×1
16atoms/cm3 以下であり、かつ該基板中を二
次イオン質量分析法で測定した窒素濃度が、平均信号強
度の2倍以上の信号強度を示す窒素偏析による局所濃化
部を有する請求項1記載のシリコン半導体基板。
4. The method according to claim 1, wherein the nitrogen content at the center of the thickness of the silicon semiconductor substrate is not less than 1 × 10 13 atoms / cm 3 and not more than 1 × 1.
A local concentration portion due to nitrogen segregation, which has a signal intensity of 0 16 atoms / cm 3 or less, and a nitrogen concentration in the substrate measured by secondary ion mass spectrometry is twice or more the average signal intensity. Item 2. The silicon semiconductor substrate according to Item 1.
【請求項5】 チョクラルスキー法又は磁場印加チョク
ラルスキー法により育成したシリコン単結晶から得たシ
リコン半導体基板であって、基板厚み中心から表面に向
かって結晶欠陥が減少する密度分布を有し、基板表面に
おける直径換算で0.1μm以上の結晶欠陥の面密度が
1個/cm2 以下であり、かつ基板表面から深さ0.1
μmにおける直径換算で0.1μm以上の結晶欠陥の体
積密度が基板厚み中心に比べ1%以下であり、さらに基
板厚み中心における窒素含有量が1×1013atoms
/cm3 以上1×1016atoms/cm3 以下である
ことを特徴とするシリコン半導体基板。
5. A silicon semiconductor substrate obtained from a silicon single crystal grown by a Czochralski method or a Czochralski method applying a magnetic field, having a density distribution in which crystal defects decrease from the center of the substrate thickness toward the surface. The surface density of crystal defects having a diameter of 0.1 μm or more on the substrate surface is 1 / cm 2 or less, and a depth of 0.1 μm or less from the substrate surface.
The volume density of crystal defects of 0.1 μm or more in terms of diameter in μm is 1% or less as compared with the center of the substrate thickness, and the nitrogen content at the center of the substrate thickness is 1 × 10 13 atoms.
/ Cm 3 or more and 1 × 10 16 atoms / cm 3 or less.
【請求項6】 1×1016atoms/cm3 以上1.
5×1019atoms/cm3 以下の窒素を含有するシ
リコン融液を用いてチョクラルスキー法又は磁場印加チ
ョクラルスキー法により育成したシリコン単結晶から得
たシリコン半導体基板を、1000℃以上1300℃以
下の温度で1時間以上熱処理することを特徴とするシリ
コン半導体基板の製造方法。
6. 1 × 10 16 atoms / cm 3 or more.
A silicon semiconductor substrate obtained from a silicon single crystal grown by a Czochralski method or a Czochralski method with the application of a magnetic field using a silicon melt containing nitrogen of 5 × 10 19 atoms / cm 3 or less is heated at 1000 ° C. to 1300 ° C. A method for manufacturing a silicon semiconductor substrate, comprising performing heat treatment at the following temperature for at least one hour.
【請求項7】 シリコン単結晶をチョクラルスキー法又
は磁場印加チョクラルスキー法により育成する際に、引
上速度をV(mm/min)、シリコンの融点から13
00℃までの温度範囲における引上軸方向の結晶内温度
勾配の平均値をG(℃/mm)とするとき、V/G≧
0.2(mm2 /℃min)を満足する条件で育成する
請求項6記載のシリコン半導体基板の製造方法。
7. When growing a silicon single crystal by the Czochralski method or the Czochralski method with a magnetic field applied, the pulling speed is set to V (mm / min) and the melting point of silicon is increased by 13%.
When the average value of the temperature gradient in the crystal in the pulling axis direction in the temperature range up to 00 ° C. is G (° C./mm), V / G ≧
7. The method for manufacturing a silicon semiconductor substrate according to claim 6, wherein the silicon semiconductor substrate is grown under a condition satisfying 0.2 (mm 2 / ° C. min).
【請求項8】 非酸化性ガス雰囲気中で熱処理する請求
項6又は請求項7記載のシリコン半導体基板の製造方
法。
8. The method according to claim 6, wherein the heat treatment is performed in a non-oxidizing gas atmosphere.
【請求項9】 酸素を0.01vol%以上100vo
l%以下含有するガス雰囲気中で熱処理した後、さらに
基板表面を0.5μm以上1.0μm以下研磨して、基
板表面を鏡面とする請求項6又は請求項7記載のシリコ
ン半導体基板の製造方法。
9. Oxygen is contained in an amount of 0.01 vol% or more and 100 vol.
8. The method for manufacturing a silicon semiconductor substrate according to claim 6, wherein after heat-treating in a gas atmosphere containing 1% or less, the substrate surface is further polished from 0.5 μm to 1.0 μm to make the substrate surface a mirror surface. .
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JP2002076007A (en) * 2000-08-31 2002-03-15 Mitsubishi Materials Silicon Corp Method of manufacturing epitaxial wafer and epitaxial wafer manufactured by the method
JP2003086596A (en) * 2001-09-14 2003-03-20 Wacker Nsce Corp Silicon semiconductor substrate and method for manufacturing the same
JP2003086597A (en) * 2001-09-14 2003-03-20 Wacker Nsce Corp Silicon semiconductor substrate and method for manufacturing the same
US6843848B2 (en) * 2000-03-24 2005-01-18 Siltronic Ag Semiconductor wafer made from silicon and method for producing the semiconductor wafer
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