531847 A7 B7 五、發明說明（/ ) 本發明係關於一種電極之製造方法，特別是積體電路中 電極之製造方法。 在最近25年中DRAM記憶體模組之記憶體密度由一個 時代至下一個時代.已增加爲4倍。基本記憶胞之原理上 之設計方式以及構成記憶胞所用之材料基本上並未改 變。DRAM記憶胞就像25年前一樣由電晶體和電容器所 構成，電容器儲存著資訊表示時所需之電荷。記憶胞之電 容器具有：由摻雜之矽或多晶矽所構成之電極以及一種配 置於電極之間的介電質層（由二氧化矽及/或氮化矽所構 成）。 爲了能可再生性地讀出此種儲存在電容器中之電荷，則 電容器之電容至少需具有30Ff之値。同時此電容器之橫 向尺寸須持續地變小，以便可提高記憶體密度。對記憶胞 之電容器之與此相對之需求會使電容器之構造複雜化 (“溝渠式電容器”），”堆疊電容器”，”皇冠式電容器”），使 電容器之橫向尺寸變小時仍然可提供一種足夠大之電齊 器面積。但電容器之製造通常是昂費的。 確保此電容器有足夠之電容所用之另一方式是在電容 器電極之間使用其它材料。最近在記憶胞之電容器電極 請 先 閱 面 之 注- 意 事 項 再 填531847 A7 B7 V. Description of the Invention (/) The present invention relates to a method for manufacturing an electrode, especially a method for manufacturing an electrode in a integrated circuit. In the last 25 years, the memory density of DRAM memory modules has increased four times from one era to the next. The basic design of the basic memory cell and the materials used to form the memory cell have remained largely unchanged. DRAM memory cells, like 25 years ago, consist of transistors and capacitors. Capacitors store the charge required for information presentation. The memory cell capacitor has an electrode composed of doped silicon or polycrystalline silicon and a dielectric layer (consisting of silicon dioxide and / or silicon nitride) placed between the electrodes. In order to read the charge stored in the capacitor reproducibly, the capacitance of the capacitor must be at least 30Ff. At the same time, the lateral dimension of the capacitor must be continuously reduced in order to increase the memory density. The relative demand for capacitors of memory cells will complicate the structure of capacitors ("ditch capacitors"), "stacked capacitors", "crown capacitors"), and when the lateral dimension of the capacitor is small, it still provides a sufficient Large electric homogenizer area. But the manufacture of capacitors is usually expensive. Another way to ensure that this capacitor has sufficient capacitance is to use other materials between the capacitor electrodes. Capacitor electrodes in memory cells recently, please read the note above-note items
訂 經濟部智慧財產局員工消費合作社印製 矽 化 氧 之 統 傳 用 使 不 此 因 間料數 之材常 是較 ο ) 另 ο 特>2 質 電 鐵 和 質 電 順 矽 化 氧 之 統 傳 式電 新介 些對 一 相 用之 使料 是材 而式 砂新 化些 氮這 者 矽 化 氮 此 因 ο 多 很 大 向需 橫所 之構 同結 相器 和容 容電 電I 同 $ 目減 地 大 大 積 記面 在器 可容 料電 材之 些需 這所 用使 使時 由寸 藉尺 有 胞 憶 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 531847 A7 B7 > 五、發明說明（ 之複雜性因此亦大大地減小。例如，可使用鈦酸緦鋇 (BST，（Ba，Sr )Ti03,鈦酸鍩鉛（pzt，Pb(Zi，，Ti )03)或以鑭 來摻雜之鈦酸錐.鉛。 除了傳統之DRAM記憶體模組外，鐵電質記億體配置（所 謂FRAM’S)將來亦扮演重要之角色。鐵電質記憶體配置較 傳統之記憶體配置（例如，DRAMs和SRAMs )所具有之優點 是：所儲存之資訊在電壓或電流中斷時亦不會消失而仍儲 存著。鐵電質記憶體配置之此種儲存性是與下述事實有 關：在鐵電質材料中此種由外部電場所施加之極化在此種 外部電極消失後仍然保持著。就鐵電質記憶體配置而言， 就可使用上述之新式材料，例如，鈦酸緦鋇 (BST，（Ba,Sr)Ti03)，鈦酸锆鉛（？21，？13(61*，1^)03)或鑭-摻雜之鈦酸锆鉛或鉅酸鉍緦（SBT，SrBi2Ta 20 9 )。 可惜這些新式順電質或鐵電質之使用亦與新式電極材 料之使用有關。新式順電質或鐵電質通常是沈積在現有 之電極（底部電極）上。此種過程是在高溫下進行，此時這 些通常構成電容器電極所用之材料（例如，摻雜之多晶矽） 可輕易地被氧化而其導電性消失，這樣會使記憶胞失效。 4d和5d過渡金屬，特別是鉑族金屬（Ru，Rh,Pd，Os，Ir， I I 背 之 L 頁 訂 經濟部智慧財產局員工消費合作社印製 及 以 身 本 舶 是 別 特 且 而 成 形 之 物 化 氧 性 電 導 或 及料 性材 化選 氧優 耐之 之望 好希 良有 有極 具作 於用 由合 來適 ί 。中 料路 材電 極體 電積 作在 用用 可述 矽上 晶： 多實 /證 矽已 之惜 雜可 摻 料 材 之 刻 蝕 可 不 或 刻 蝕 易 不 於 屬 只 上在 學蝕 化剝 在式 料新 材刻 式蝕 新中 之其 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 531847 A7 B7 五、發明說明（4 ) 使用”反應性氣體”時主要是或幾乎只與此蝕刻之物理成 份有關。 · 目前所用材料之結構化通常是藉由所謂電漿促進式之 非等向性餽刻來進.行。因此通常是使用物理-化學方法， 其中使用由一種或多種反應性氣體所構成之氣體混合物， 例如，使用由氧，氯，溴，氫化溴，氯化溴或鹵化之氫化碳所 構成之氣體混合物或稀有氣體（例如，A r , H e )所構成之氣 體混合物。這些氣體混合物通常在電磁交變場中在小之 壓力下受到激發，使此種氣體混合物轉換成電漿。 電漿之正離子幾乎垂直地擊中此種待結構化之層，這樣 可使此種位在待結構化之層上之遮罩達成一種良好之成 像作用。通常是使用光阻作爲遮罩材料，這是因爲此種材 料較容易藉由曝光步驟和顯影步驟而被結構化。蝕刻之 物理成份是藉由脈衝和所打入之離子（例如，C 12+ , A r +)之 動能而造成。此外，在形成揮發性反應性產物之情況下在 此種待結構化之層和反應性氣體微粒（離子，分子，原子， 基（r a d i c a 1 ))之間可因此而起動或放大化學反應（蝕刻之 化學成份）。此種在基板微粒和氣體微粒之間的化學反應 即爲此種蝕刻過程具有高的蝕刻選擇性之原因。 經濟部智慧財產局員工消費合作社印製 在鈾刻上述材料（特別是電極材料）時由於較小之（或不 具有）化學成份，則此種待結構化之層之蝕刻剝蝕度是和 該遮罩或底層（蝕刻停止層）之蝕刻剝蝕度之大小相同的， 即，此種對該蝕刻遮罩或底層之蝕刻選擇性通常是很小的 (大約在0 · 3和3 . 0之間）。這樣所造成之結果是：由於遮 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 531847 Α7 Β7 五、發明說明（4 罩隨著傾斜之側面而磨損以及不可避免地會形成多角形 平面，則只能確保此種結構化可達成一種很小之尺寸精確 性。此外，特別是在過（ο V e r )蝕刻步驟時底層會受到強烈 地蝕刻且使各蝕刻.側面有一種不易控制之傾斜度。其結 果是只能以很昂費之費用才可產生很小之電極（電極之基 本面積=F2，F=藉由一定之技術所可製成之最小之結構大 小）。 此外，在製造一般所使用之堆疊式電容器時會產生以下 問題：此電容器之下部電極必須與電性終端相重疊。若此 電極之終端（通常是所謂”插頭”）是以可製成之最小之結 構大小F2來製成，則在傳統之製造方法中此電極之基本 面積必須選擇成較F2大很多，以便確保可達成上述之”重 疊”。若在傳統之製造方法中此電極之基本面積未選擇成 較F2大很多，則在相對應之遮罩對準時之不準確性會使 電極和插頭之間不會”重疊”。這樣所造成之結果是：電極 不能被連接而使此記憶胞失效。因此，使用一種堆疊式電 容器之此種記憶胞具有較之面積需求，這樣對所可達成之 記憶體密度不利。 本發明之目的是提供一種電極之製造方法，其可大大地 減小或防止上述問題。 此目的是藉由申請專利範圍第1項之電極之製造方法 以及第1 1項之電極來達成。本發明其它有利之實施形式， 構造及外觀描述在申請專利範圍各附屬項及各附圖中。 •依據本發明，製備一種對準其終端之電極，特別是製備 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 請 先 閲 讀 背 面 之 注 項 再 填 訂 經濟部智慧財產局員工消費合作社印製 531847 A7 B7 五、發明說明（6 ) 依據本發明之較佳實施例形式，在步驟d )中以導電性材 料塡入此接觸孔中，較佳是以多晶矽完全塡滿且選擇性地 對此隔離層來對此導電性材料進行回（back)蝕刻直至一 預定之高度爲止。.這樣所具有之優點是：此導電性材料可 塡入此接觸孔中直至一預定之高度爲止，在此預定高度之 上方在接觸孔之側壁上此導電性材料之一部份不會形成 一種薄的導電層。此外，爲了使接觸孔中可塡料至一預定 之高度，則可使用一些已存在之過程來對此接觸孔進行塡 料而不必大大地改變各製程參數。此外，在該選擇性回蝕 刻之前進行一種CMP步驟是較佳的。 依據其它較佳之實施形式，在步驟e )之前在接觸孔中之 導電性材料之產生一種位障層。此位障層例如可藉由金 屬（較佳是Co)之濺鍍或蒸發以及隨後之退火以形成一種 金屬矽化物層而產生。因此，若在此位障層產生之後進行 一種等向性蝕刻是特別有利的。藉由此種等向性蝕刻可 由接觸孔之側壁去除此位障層之一部份或去除這些製造 此位障層時所用之金屬。 較佳是使用4d和5d過渡金屬，特別是鉑族金屬（Ru,Rh， Pd , 0 s，I r，P t ),特別是鉑或鍊，作爲電極材料。 依據其它較佳之實施形式，此種電極材料是藉由濺鍍 (較佳是已對準之濺鍍）而沈積在整面上且在步驟f )之前 進行一種CMP步驟。若在此種CMP步驟中使用一種單晶 奈米（1 (T9m )微粒（特別是A 1 20 3奈米微粒）懸浮液則這樣 是特別有利的。此外，若添加一些材料（特別是甘油或多 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 請 先 閱 讀 r 之 注_ 項 再 填 I# 頁 訂 經濟部智慧財產局員工消費合作社印製 531847 Α7 Β7 五 、發明說明（， 經濟部智慧財產局員工消費合作社印製 料7塡入且在此矽基板1之上側上形成一種連續之導電 層。這樣所形成之結構顯示在第3圖中。 然後進行一種 CMP(Chemical Mechanical Polishing) 步驟，其可去除此矽基板1之上側上之連續之導電層且產 生一種平坦之表面。此外，藉由一種選擇性地對此隔離層 5來進行之蝕刻過程而對此接觸孔6中之導電性材料7 進行回蝕刻一段期間直至這些接觸孔6以導電性材料7 塡入至只到一預定之高度爲止。以此種方式可確保：此導 電性材料7可塡入各接觸孔6中直至一預定之高度爲止， 使得此導電性材料7之一部份在此預定高度上方之接觸 孔之側壁上不會形成薄的導電層。這樣所形成之結構顯 示在第4圖中。 現在藉由濺鍍或蒸發在接觸孔6中之導電性材料7上 產生一種位障層8。例如，藉由濺鍍或蒸發而沈積一種金 屬層（例如，Co )且藉由隨後之退火過程使金屬擴散至摻雜 之矽7中而形成一種金屬矽化物層（例如，CoSix)以作爲 位障層8。接觸孔6之側壁上以及導電性材料7上之未 轉換成矽化金屬之此種金屬藉由等向性之蝕刻（例如，濕 式化學蝕刻）選擇性地對矽化物而被去除。這樣所形成之 結構顯示在第5圖中。 然後沈積此電極所用之材料。須沈積此種電極材料（例 如，鉑），使各接觸孔6被完全塡滿。這例如可藉由已對準 之濺鍍法或藉由蒸發法而達成。但此種沈積通常不只在 接觸孔6中進行而是在整個表面上進行。這樣所形成之 -1 0 _ 請 先 閱 讀-背 面 之 注， 意 事 項 再 填二ί零 頁 訂 線 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 531847 A7 B7 五、發明說明（9 ) 糸口構顯不在第6圖中。 爲了由此表面去除此電極材料，隨後須進行一種CMP步 驟。在拋光時爲了提高機械上之剝蝕度，須使用單晶奈米 破fii (例如，A 12 〇 3 -奈米微粒）之懸浮液。爲了防止這些微 粒聚集而形成一種刮痕，則須添加一些材料（特別是有機 流體，例如，甘油或多醇類）至此種懸浮液中以便防止各種 聚集現象。此電極材料9藉由CMP步驟而由表面去除，但 各接觸孔6仍保持著完全以此電極材料塡入之情況。一 種特別適用於舶之CMP方法描述在I.Haisma et al.， Philips J.Res.49(1995)，page 23-46 之專業論文中，其 所揭示之內容在此處完全被採用。 然後藉由一種選擇性地對此電極材料之蝕刻過程而去 除該隔離層5直至一預定之深度爲止。須選取此種預定 之深度，使只有電極材料之一部份裸露出來，但位障層及/ 或此導電性材料7未裸露出來。這樣所形成之結構顯示 在第7圖中。 因此產生一些橫向範圍很小之電極1 0而不必對通常不 易蝕刻之電極材料直接進行結構化。所期望之結構是以 容易蝕刻之可結構化之隔離層來產生。對電極材料之直 接蝕刻所發生之所有上述問題即可避免。此電極1 0之側 面傾斜度因此亦不再與困難之電極蝕刻過程有關。而是 由開始時已蝕刻之接觸孔i 6 .1之側面傾斜度所決定。但開 始時已蝕刻之這些接觸孔6之側面傾斜度可很容易地被 調整及控制。 -1 1 - 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 請 先 閱 讀 背 S 之 注 意 事 項 再 填Order the general transmission of silicic oxide printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs, so the number of materials is often relatively small. Ο) ο Special > 2 The general transmission of high-quality electric iron and high-quality electric silicon silicide Dianxin uses some materials for one phase to make the material new. Nitrogen is the reason for this. The reason is that it is very large and needs to be constructed. The phase coupler and the capacity capacitor are the same. Greatly keep in mind that the surface of the device can accommodate the need for electrical materials. This is used so that the time can be measured by inches. The paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 531847 A7 B7 > The description of the invention (the complexity of the invention is also greatly reduced. For example, barium hafnium titanate (BST, (Ba, Sr) Ti03, lead hafnium titanate (pzt, Pb (Zi ,, Ti) 03) or Lanthanum-doped titanate cone. Lead. In addition to traditional DRAM memory modules, the ferroelectric mass memory configuration (the so-called FRAM'S) will also play an important role in the future. The ferroelectric memory configuration is more traditional than that of the memory. Configurations (eg, DRAMs and SRAMs) have the following advantages: The stored information does not disappear when the voltage or current is interrupted, but it is still stored. This storage of the ferroelectric memory configuration is related to the fact that in ferroelectric materials, this is applied by an external electrical field. The polarization remains after the external electrode disappears. As far as the ferroelectric memory configuration is concerned, the new materials mentioned above can be used, such as barium hafnium titanate (BST, (Ba, Sr) Ti03), titanic acid Lead zirconium (? 21,? 13 (61 *, 1 ^) 03) or lanthanum-doped zirconium lead titanate or rhenium bismuth giant (SBT, SrBi2Ta 20 9). Unfortunately these new paraelectric or ferroelectric The use is also related to the use of new electrode materials. New paraelectrics or ferroelectrics are usually deposited on existing electrodes (bottom electrodes). This process is performed at high temperatures. At this time, these are usually used for capacitor electrodes. Materials (for example, doped polycrystalline silicon) can be easily oxidized and their electrical conductivity disappears, which can invalidate memory cells. 4d and 5d transition metals, especially platinum group metals (Ru, Rh, Pd, Os, Ir, II) Back page L Orders Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs It is a special and shaped physical and chemical oxygen conductivity or material material that has a good hope of oxygen selection and good resistance. Xiliang has a very useful and suitable application. The electrode body can be described in use as a crystal on silicon: It is a pity that silicon has been miscellaneous. The material can be etched with or without etching. The size of the paper used in etch etching is applicable to the Chinese National Standard (CNS) A4 (210 X 297 mm) 531847 A7 B7 V. Description of the invention (4) When using "reactive gas", it is mainly or almost only The physical composition of etching is related. · The structuring of materials currently used is usually performed by so-called plasma-promoted non-isotropic feeding. Therefore, it is common to use a physico-chemical method in which a gas mixture composed of one or more reactive gases is used, for example, a gas mixture composed of oxygen, chlorine, bromine, hydrogen bromide, bromine chloride or halogenated carbon hydrogen Or a gas mixture of noble gases (for example, Ar, He). These gas mixtures are usually excited under a small pressure in an electromagnetic alternating field to convert this gas mixture into a plasma. The positive ion of the plasma hits the layer to be structured almost vertically, so that the mask on the layer to be structured can achieve a good imaging effect. A photoresist is usually used as a mask material because such a material is easier to be structured by an exposure step and a development step. The physical composition of the etch is caused by the pulse and the kinetic energy of the incoming ions (for example, C 12+, A r +). In addition, in the case of the formation of volatile reactive products, a chemical reaction (etching) can be initiated or amplified between such a layer to be structured and reactive gas particles (ions, molecules, atoms, radicals 1). Chemical composition). Such a chemical reaction between the substrate particles and the gas particles is the reason for the high etching selectivity of this etching process. The consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs printed the above materials (especially electrode materials) when the uranium was engraved due to the relatively small (or no) chemical composition. The mask or bottom layer (etch stop layer) has the same degree of etch ablation, that is, the etch selectivity to the mask or bottom layer is usually small (about between 0.3, 3.0 and 3.0). . The result of this is: because the paper size of the cover paper applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 531847 Α7 Β7 V. Description of the invention (4 The cover wears with the inclined side and inevitably will The formation of a polygonal plane can only ensure that this structuring can achieve a small dimensional accuracy. In addition, the bottom layer will be strongly etched and etched especially during the (ο V) etching step. A kind of difficult-to-control tilt. As a result, very small electrodes can only be produced at a very expensive cost (basic area of the electrode = F2, F = the smallest structure size that can be made by a certain technology) In addition, the following problems arise when manufacturing stacked capacitors generally used: the lower electrode of the capacitor must overlap the electrical terminal. If the terminal of this electrode (usually the so-called "plug") is made The smallest structure size F2 is made. In the traditional manufacturing method, the basic area of this electrode must be selected to be much larger than F2 in order to ensure that the above-mentioned "overlap" can be achieved. In the traditional manufacturing method, the basic area of this electrode is not selected to be much larger than F2, and the inaccuracy in the corresponding mask alignment will not cause "overlap" between the electrode and the plug. The result of this Yes: The electrode cannot be connected to invalidate this memory cell. Therefore, such a memory cell using a stacked capacitor has a relatively small area requirement, which is not conducive to the achievable memory density. The object of the present invention is to provide an electrode The manufacturing method can greatly reduce or prevent the above problems. This purpose is achieved by the manufacturing method of the electrode of the first item of the patent application scope and the electrode of the first item. Other advantageous implementation forms and structures of the present invention And the appearance description is in the appended items and the accompanying drawings of the scope of patent application. • According to the present invention, an electrode aligned with its terminal is prepared, especially the paper size applicable to the Chinese National Standard (CNS) A4 specification (210 X 297) Li) Please read the note on the back before filling in the printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 531847 A7 B7 V. Description of the invention 6) According to a preferred embodiment of the present invention, in step d), a conductive material is inserted into the contact hole, and the conductive material is preferably filled with polycrystalline silicon and the isolation layer is selectively filled with the conductive material. Back etching is performed until a predetermined height. This has the advantage that the conductive material can be inserted into the contact hole up to a predetermined height, and a portion of the conductive material on the side wall of the contact hole above the predetermined height will not form a kind of Thin conductive layer. In addition, in order to make the contact hole to a predetermined height, some existing processes can be used to materialize the contact hole without greatly changing the process parameters. In addition, it is preferable to perform a CMP step before the selective etch-back. According to other preferred embodiments, a barrier layer is formed in the conductive material in the contact hole before step e). This barrier layer can be produced, for example, by sputtering or evaporation of metal (preferably Co) and subsequent annealing to form a metal silicide layer. Therefore, it is particularly advantageous to perform an isotropic etching after the formation of the barrier layer. By this isotropic etching, a part of the barrier layer can be removed from the side wall of the contact hole or the metal used for manufacturing the barrier layer can be removed. It is preferred to use 4d and 5d transition metals, especially platinum group metals (Ru, Rh, Pd, 0 s, Ir, P t), especially platinum or chains, as electrode materials. According to other preferred embodiments, this electrode material is deposited on the entire surface by sputtering (preferably aligned sputtering) and a CMP step is performed before step f). This is particularly advantageous if a single crystal nano (1 (T9m)) particle (especially A 1 20 3 nano particle) suspension is used in this CMP step. In addition, if some materials (especially glycerin or Many paper sizes are in accordance with Chinese National Standard (CNS) A4 (210 X 297 mm) Please read the note of r first and fill in the I # page to order printed by the Intellectual Property Bureau Employee Consumer Cooperative of the Ministry of Economic Affairs 531847 Α7 Β7 V. Invention Explanation (The employee's cooperative printed material 7 of the Intellectual Property Bureau of the Ministry of Economics entered and formed a continuous conductive layer on the upper side of this silicon substrate 1. The structure thus formed is shown in Figure 3. Then a CMP ( Chemical Mechanical Polishing) step, which can remove the continuous conductive layer on the upper side of the silicon substrate 1 and produce a flat surface. In addition, this is contacted by an etching process selectively performed on the isolation layer 5 The conductive material 7 in the holes 6 is etched back for a period of time until the contact holes 6 are penetrated with the conductive material 7 to only a predetermined height. In this way, it can be ensured that: The conductive material 7 can be inserted into each contact hole 6 up to a predetermined height, so that a part of the conductive material 7 does not form a thin conductive layer on the side wall of the contact hole above the predetermined height. The formed structure is shown in Figure 4. A barrier layer 8 is now produced on the conductive material 7 in the contact hole 6 by sputtering or evaporation. For example, a metal layer (such as Co) and a metal is diffused into the doped silicon 7 by a subsequent annealing process to form a metal silicide layer (for example, CoSix) as the barrier layer 8. The sidewalls of the contact hole 6 and the conductive material 7 The above-mentioned metal that has not been converted into a silicide metal is selectively removed by an isotropic etching (for example, wet chemical etching). The structure thus formed is shown in Figure 5. Then deposited The material used for this electrode. This electrode material (for example, platinum) must be deposited so that each contact hole 6 is completely filled. This can be achieved, for example, by aligned sputtering or by evaporation. But this This type of deposition is usually not limited to It is carried out in the contact hole 6 but on the entire surface. -1 0 _ formed in this way, please read the note on the back, and then fill out the two items. Zero page alignment. The paper size applies Chinese National Standard (CNS) A4. Specifications (210 X 297 mm) 531847 A7 B7 V. Description of the invention (9) The gate structure is not shown in Figure 6. In order to remove this electrode material from this surface, a CMP step must be performed subsequently. In order to improve the mechanical properties during polishing For the degree of erosion, a suspension of single crystal nanometer fii (e.g., A1203-nanometer particles) must be used. To prevent these particles from agglomerating and forming a scratch, some materials (especially organic fluids, (Eg, glycerol or polyols) to such suspensions in order to prevent various aggregation phenomena. This electrode material 9 is removed from the surface by the CMP step, but each contact hole 6 remains completely infiltrated with this electrode material. A CMP method that is particularly suitable for shipping is described in a professional paper by I. Haisma et al., Philips J. Res. 49 (1995), pages 23-46, whose disclosure is fully adopted here. The isolation layer 5 is then removed by a selective etching process of the electrode material to a predetermined depth. It is necessary to select such a predetermined depth so that only a part of the electrode material is exposed, but the barrier layer and / or the conductive material 7 is not exposed. The structure thus formed is shown in FIG. Therefore, some electrodes 10 with a small lateral range are generated without having to directly structure electrode materials that are usually not easily etched. The desired structure is created with a structured isolation layer that is easy to etch. All of the above problems that occur with direct etching of electrode materials can be avoided. The side slope of this electrode 10 is therefore no longer related to the difficult electrode etching process. It is determined by the inclination of the side of the contact hole i 6 .1 that has been etched at the beginning. However, the inclination of the sides of the contact holes 6 which have been etched at the beginning can be easily adjusted and controlled. -1 1-This paper size is in accordance with China National Standard (CNS) A4 (210 X 297 mm).
叮 經濟部智慧財產局員工消費合作社印製 531847 Α7 Β7 i、發明說明（ 此外，藉由本方法須選取此電極1 〇使其和其終端7，8 一樣小，因爲在.製成此電極1 0時須使用此隔離層5中之 相同結構，其亦用來製成此終端7，8。電極1 0因此以自 我對準其終端7 , 8 .之方式而產生。此電極1 0因此不需違 反本意地擴大，這在先前技藝中是需要的，以便補償位置 上之誤差。此電極1 〇之空間需求因此較小。由於製成此 電極1 0時須使用該隔離層5中之相同結構，其亦用來製 成此終端7 , 8，則可另外節省一種遮罩平面。先前技藝中 產生此終端及產生此電極所用之各種不同之遮罩可組合 成一個遮罩，這樣就可大大地降低此製造成本。 然後產生一種介電質層及/或鐵電質層11以及沈積另 一層1 2以便形成上部電極。這樣所形成之結構顯示在第 8圖中。層1 1和1 2通常一起被結構化，使記億胞可由選 擇電晶體4和電容器1 0，1 1，1 2所製成。 符號之說明 1 ...矽基板 2.. .擴散區 3.. .閘極電極 4.. .選擇電晶體 5.. .隔離層 6.. .接觸孔 7.. .導電性材料 8 ...位障層 9.. .電極材料 -12- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 請 先 閱 讀 背· 之 注- 項 再 填 寫 本 頁 經濟部智慧財產局員工消費合作社印製Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 531847 Α7 Β7 i. Invention description (In addition, by this method, this electrode 1 must be selected to be as small as its terminal 7, 8 because this electrode is made in 0. It is necessary to use the same structure in this isolation layer 5, which is also used to make the terminals 7, 8. The electrode 10 is therefore produced by self-aligning its terminals 7, 8 .. This electrode 10 is therefore not required Expansion against the original intention, which is needed in the prior art in order to compensate for positional errors. The space requirement of this electrode 10 is therefore smaller. Since the same structure in the isolation layer 5 must be used when making this electrode 10 It is also used to make the terminals 7, 8, which can save another kind of mask plane. In the previous technology, the different masks used to generate this terminal and this electrode can be combined into a mask, which can greatly This reduces the manufacturing cost. Then a dielectric layer and / or ferroelectric layer 11 and another layer 12 are deposited to form the upper electrode. The structure thus formed is shown in Figure 8. Layers 1 1 and 1 2 Usually structured together In order to make the memory cell can be made of the selection transistor 4 and the capacitors 10, 1 1, 12 2. Explanation of the symbols 1 ... silicon substrate 2.... Diffusion region 3.... Gate electrode 4... Select transistor 5 ... Isolation layer 6 ... Contact hole 7 .. Conductive material 8 ... Barrier layer 9 ... Electrode material-12- This paper size applies to China National Standard (CNS) A4 specifications (210 X 297 mm) Please read the back · Note-before filling out this page Printed by the Employee Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs