TW408489B - The manufacture method of DRAM - Google Patents

Abstract

A kind of manufacture method of DRAM, which is to form one dielectrics layer on the substrate of formed field effect transistor, and to form the contact opening that exposes the source/drain region on the dielectrics. Then, cover one conductor layer of which the thickness could fill up the dielectrics opening. Then, define the conductor layer and remove part of the dielectrics uncovered by the dielectrics of the patterning conductor layer so that there forms the concave dent which surrounds the conductor layer on the dielectrics; then, form the conductor space wall on the sidewall of the concave dent and the sidewall sited on the conductor layer of the upper portion of the dielectrics to make it co-compose the bottom electrode of the capacitor with the above-mentioned conductor layer.

Description

4445twf.d〇c / 00 P8489 at B7 printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the Invention (I) The present invention relates to a method for manufacturing integrated circuits, and more particularly to a dynamic random access Manufacturing method of memory (Dynamic Random Access Memory, DRAM). As the functions of computer microprocessors gradually increase and the programs and calculations performed by software become more and more large, the capacitance requirements of memory will become higher and higher. With the increase of the dynamic random access memory volume concentration, the currently developed memory cell system consists of a transfer field effect transistor and a storage capacitor. Since the capacitor is the heart of the DRAM where the signal is stored, the more charge the capacitor stores, the less the sense amplifier will be affected by noise when reading data. The methods generally used to increase the charge storage capacity can be achieved by increasing the area of the capacitor, using a dielectric film layer with a high dielectric constant, or reducing the thickness of the dielectric film layer. Currently developed dielectric films with high dielectric constants include tantalum pentoxide (Ta205), Pb (Zr, Ti) 03 ', PZT and (Ba, Sr) Ti03, BST. The method of increasing the surface area of the capacitors is accompanied by the high accumulation of integrated circuit components, which has been required to use three-dimensional capacitors, such as the so-called Stacked Type or Trench Type capacitors. In today's more highly integrated memory devices, for example, DRAM with a capacity of 64M bits, the electrodes of the capacitor and the dielectric film layer are extended horizontally and stacked up to form a so-called fin type (Fin Type) stacked capacitors, or the electrodes and dielectric film layers of the capacitors are extended into a vertical structure to form a so-called cylindrical type stacked capacitor to achieve the purpose of increasing capacitance. This paper size is applicable to Chinese National Standard (CNS) A4 (2I0X297mm) (Please read the precautions on the back before filling in this f

4 4 4 5 t wf. D > i / ^ 2489 A7 B7 Printed by the Consumers ’Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of the invention (1) Figure 1 shows the dynamic random access memory of a cylindrical capacitor. Sectional view. The fabrication of a capacitor for a dynamic random access memory is 'formed after a field effect transistor 104' is formed on a substrate 100 having an isolation region 102 formed thereon, 'and a substrate 110 is first covered with a dielectric layer 110' and a dielectric layer is formed. A contact window opening 112 is formed in U0 to expose the source / drain regions 108. Thereafter, an amorphous silicon layer 114 'is formed on the substrate 100 to cover the surface of the dielectric layer 110 and fill the contact window opening 112. Next ’lithography and the worm

The I-cut procedure defines the pattern of the conductor layer 114 overlying the dielectric layer no as the main structure of the electrode under the capacitor. Thereafter, a selective hemispherical silicon grain (HSG) (not shown.) Is formed on the defined amorphous silicon layer 114 to increase the surface area of the lower electrode, and then a dielectric layer film 116 and Another polycrystalline silicon layer 118 is used as an electrode on the capacitor. In order to cope with the current demand for high-density dynamic random access memory, a conventional method is to increase the thickness of the above-mentioned amorphous silicon layer 114 to increase the surface area of the lower electrode by increasing the thickness, thereby increasing the charge storage of the capacitor. . However, the deposition rate of amorphous silicon is very low. For example, the currently manufactured dynamic random access memory has a thickness of 8000 angstroms and the amorphous silicon layer 114 must be deposited for more than 16 hours. Therefore, increasing the thickness of the amorphous silicon layer Π4 to increase the storage capacitance will not only take a long time to deposit, reduce manufacturing throughput, but also easily increase the operation cost of the furnace tube. In addition, the excessively thick amorphous silicon layer 114 may increase the difficulty of etching during the process of defining the pattern. This paper size applies to Chinese National Standard (CNS) A4 specification (210X297 mm)-β in (Please read the precautions on the back before filling this page)

ς 408489 Α7 4445twf. doc / 002 ......... B7_____ 5. Description of the Invention (,) Therefore, the present invention provides a method for manufacturing a dynamic random access memory, which can increase the storage capacity of a capacitor. The present invention provides a method for manufacturing a dynamic random access memory, which can increase the surface area of the electrodes under the capacitor to increase the storage capacity of the capacitor. The present invention provides a method for manufacturing a dynamic random access memory, which can reduce manufacturing time and increase manufacturing capacity. The present invention provides a method for manufacturing a dynamic random access memory, which can reduce the operation cost of the furnace tube. The present invention provides a method for manufacturing a capacitor of a dynamic random access memory. The method is briefly described as follows: a dielectric layer is formed on the substrate on which a field effect transistor has been formed, and an exposed source electrode is formed in the dielectric layer. / Drain region contact window opening, then cover the substrate with a conductive layer thick enough to fill the dielectric window opening, and then define the conductor layer and remove the dielectric layer not covered by the patterned conductor layer A part of the dielectric layer is engraved with a groove surrounding the conductor layer, and then a conductor gap wall is formed on the side wall of the groove and the side wall of the conductor layer above the dielectric layer so that it is in line with the above conductor. The electrode body structure under the layer group capacitor. Then, a dielectric film layer and another conductor layer are formed on the above-mentioned conductor layer and the conductor gap wall. According to the embodiment of the present invention, the steps of defining the conductor layer and forming a groove surrounding the conductor layer in the dielectric layer are to form a layer of silicon nitride and a photoresist layer on the conductor layer, and then 'the nitrogen The silicon layer and the photoresist layer are patterned, and then the silicon nitride is used as an etching hard mask layer, the conductor layer and the dielectric layer are etched, and then the silicon nitride layer and the photoresist layer are removed. 5 This paper size applies the Chinese National Standard (C.NS) M specification (210 > < 297 mm) (谙 Please read the notes on the back before filling out this page) Order the Intellectual Property Bureau of the Ministry of Economic Affairs and the Consumer Cooperatives to print the economy Printed by the Consumer Cooperatives of the Ministry of Intellectual Property Bureau 4445twf.d〇c / 002 A / _._ B7 __ — V. Description of the invention (f) Because the silicon nitride layer and the conductor layer and between the dielectric layer have A good etching selection ratio can be used as a hard mask curtain layer in the etching process. Therefore, the present invention does not need to form an excessively thick photoresist layer, and therefore, problems caused by excessively thick photoresist layers can be avoided. In addition, the thickness of the above-mentioned conductor layer and the conductor gap wall is very thin, which is very suitable for the fabrication of the electrodes under the amorphous silicon, which can reduce the time for depositing the polycrystalline silicon layer, increase the production capacity, and reduce the operation cost of the furnace tube. In addition, the above method can form a hemispherical silicon grain layer on the electrode body under the conductor layer and the conductor gap wall to increase the surface area of the lower electrode, thereby improving the storage capacity of the capacitor. The present invention proposes another method for manufacturing a capacitor of a dynamic random access memory. A brief description of this method is as follows: a dielectric layer is formed on a substrate on which a field effect transistor has been formed, and an exposed layer is formed in the dielectric layer. Contact window opening in the pole / drain region. Thereafter, a polycrystalline silicon layer is coated on the substrate to a thickness sufficient to fill the openings of the interlayer window, and a first barrier layer and a first metal layer are formed on the polycrystalline silicon layer. Next, a polycrystalline silicon layer, a first barrier layer and a first metal layer are defined. Thereafter, the portion of the dielectric layer not covered by the first metal layer is removed to form a groove in the dielectric layer surrounding the polycrystalline silicon layer. Then, a second barrier layer and a second metal layer are formed on the substrate, and an etch-back process is performed to form a conductor gap wall on the polycrystalline silicon layer, the first barrier layer, the first metal layer and the sidewall of the groove. . Next, a dielectric film layer is formed on the first metal layer and the bulk gap wall, and a conductive layer is covered on the dielectric film layer. According to the embodiment of the present invention, the above-mentioned definition of the polycrystalline silicon layer, the first barrier layer and the first metal layer, and the formation of a surrounding polycrystalline silicon in the dielectric layer 6 The paper size is applicable to Chinese national standards (CNS > A4 Specifications (210X297mm > (Please read the note on the back before filling in this page)

A7 B7 5. The step of the invention description (meeting) layer is to form a layer of silicon nitride and a photoresist layer on the first metal layer. After that, first pattern the silicon nitride layer and the photoresist layer. Using it as a uranium mask, the first metal layer, the first barrier layer, the polycrystalline silicon layer and the dielectric layer are etched, and then the silicon nitride layer and the photoresist layer are removed. Since the silicon nitride layer has a good etching selection ratio between the first metal layer, the first barrier layer, the polycrystalline silicon layer, and the dielectric layer, it can be used as a hard mask in the uranium etching process Therefore, the present invention does not need to form an excessively thick photoresist layer, and therefore, the problems caused by excessively thick photoresist layers can be avoided. Furthermore, according to the embodiment of the present invention, the above method can use ruthenium dioxide as the lower electrode to improve the performance of the capacitor, and because the polycrystalline silicon is implanted in the opening of the contact window, the metal layer and the source / drain can be avoided. Leakage from pole contact. In addition, the present invention can use a dielectric film layer having a high dielectric constant, including tantalum pentoxide, BST, and PZT 'to increase the storage capacity of the capacitor. In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, the preferred embodiments are described below in detail with the accompanying drawings as follows: A brief description of the drawings = FIG. 1 is known Cross-sectional view of a dynamic random access memory element of a columnar capacitor, FIG. 2A to FIG. 2E, which are cross-sectional views illustrating a manufacturing process of a dynamic random access memory according to the first preferred embodiment of the present invention ; And Figures .3A to 3G, which show the second best practice according to the present invention (please read the precautions on the back before filling in this purchase)

T 印 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 4 4 4 5 twf doc / 002. A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. A description of the invention (A), a kind of dynamic random storage. Sectional view of the manufacturing process. Description of graphical symbols: 100, 200, 300 substrates 102, 202, 302 isolation regions 104, 204, 304 field effect transistors 108 '208 source / drain regions 110' 210 '310 dielectric layers 112, 212, 312 contact Window opening 114 Amorphous silicon layer 116, 234, 334 Dielectric film layer 118 '314 Complex crystal sand layer 206 Gate 214, 236, 336 Conductor layer 220, 320 Hard cover curtain layer 222, 322 Photoresist layer 223' 323 Groove 230, 330 Conductor gap wall 23 2 Hemispherical sand grain layer 315 Metal silicide layer 316, 324 Barrier layer 318, 326 Metal layer Example 1 Please refer to FIGS. 2A to 2F, which shows a comparison according to the present invention. Manufacturing of a kind of columnar capacitor dynamic random access memory in the preferred embodiment (please read the precautions on the back before filling this page) This paper size is applicable to China National Standard (CMS) A4 specification (210X297 mm)

4 4 5 twf. Do I Record 84 8g / 002 A7 B7 V. Description of the invention (q) Process sectional view. First, please refer to FIG. 2A. On the surface of the substrate 200, for example, a p-type silicon substrate, an isolation region 202 is formed to define an active region of the device. Then, a field effect transistor of a dynamic random access memory is formed on the active region. 204 and bit line (not shown). The isolation region 202 is formed by, for example, a shallow trench isolation (STI) method or a local area oxidation method (LOCOS). The field effect transistor 204 includes a gate electrode 206 and a source / drain region 208. The gate electrode 206 may be, for example, a gate oxide layer, a doped polycrystalline layer, a silicided metal layer, such as tungsten alumina (WSi2), and a thickness of about 100 Angstroms, 1000 Angstroms, 1000 Angstroms, and 1000 Angstroms, respectively. The capping layer is composed of, for example, silicon nitride (SiNx). In addition, a gap wall is formed on the sidewall of the gate electrode 206, and the material thereof includes silicon nitride. The formation method can deposit a silicon nitride layer with a thickness of about 1500 angstroms on the substrate 200, and then perform etch-back to prepare it. Next, referring to FIG. 2A, a dielectric layer 210 is formed on the substrate 200 with a thickness of about 3 μm. The material of the dielectric layer 210 is, for example, silicon oxide deposited by chemical vapor deposition, borophospho-silicon glass separation (BPSG), or spin-on-glass (SOG) formed by coating. After that, the dielectric layer 210 is planarized by a chemical mechanical honing method (CMP), so that the dielectric layer 210 has a relatively flat surface, so as to facilitate subsequent processes. The element line is about 2 microns. Next, referring to FIG. 2B, a dielectric layer 210 is defined by a lithography imaging and etching process to form a contact window opening 212 in the dielectric layer 210 to expose the source / drain regions 208. Then, a conductive layer 214 'is formed on the substrate 200 with a thickness sufficient to fill the contact window opening 212 with the source / drain electrode 9 ^^ 1. Applicable to the Chinese National Standard (€ 邶) 8 4 specifications (210 乂 297 mm) Li Factory '(Please read the precautions on the back before filling this page) Order printed by the Intellectual Property Bureau of the Ministry of Economic Affairs and printed by the co-operative cooperative _48d A7 4445twf. Doc / 002 __ B7__ V. Description of the invention (?) Area 208 coupling The material of the conductor layer 214 is, for example, doped polycrystalline silicon or amorphous silicon, and the method of forming the conductor layer 214 is, for example, a chemical vapor deposition method with a thickness of about 1000 angstroms to 3000 angstroms. Next, a layer is formed on the conductive layer 214. The hard cover curtain layer 220 and a photoresist layer 222. The material of the hard cover curtain layer 22 and the dielectric layer 210 and the conductor layer 214 have a good etching selection ratio. For example, for the chemical vapor deposition method, (please read the note on the back 4 4 4 5 twf.doc / 〇〇2 printed by the staff consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. The invention description (7) on the substrate 200, and then To carry out an etch-back process so that the conductor layer 214 and the recess remain A polycrystalline silicon layer or an amorphous silicon layer on the side wall of 223 forms the above-mentioned conductive spacer 230 °. Then, referring to FIG. 2E, remove the hard cover curtain layer 22 ′ to expose it. The conductive layer 214 and the conductive spacer 230 The electrode body under the structure. The method for removing the hard cover curtain layer 220 includes wet etching, such as using hot phosphoric acid as an etching solution. Next, a layer of hemispherical silicon grains is formed on the surface of the conductor layer and the conductor spacer 230 ( Hemispherical-Grained Silicon (HSG-Si) layer 232 to increase the surface area of the lower electrode to increase the storage capacitance of the capacitor. The hemispherical sand grain layer 232 can be formed by chemical vapor deposition or selective hemispherical silicon The technology of crystal grains is formed. Since the thickness of the conductor layer 214 of the present invention can be reduced to fill the contact window opening 212, and the thickness of the conductor spacer 230 is not required to be too thick, the present invention is very suitable The fabrication of electrodes under amorphous silicon can reduce the time to deposit the amorphous sand layer, increase the production capacity, and reduce the operating cost of the furnace tube. In addition, due to the conductor gap wall 23 0 is formed by etch-back, and does not need to define its pattern by typical lithography imaging and etching procedures, so it can reduce the difficulty and cost of the process, and can avoid the thickness of the conductor layer being too thick. During the etching process The problem of easy fracture. Finally, please continue to refer to FIG. 2E to form a dielectric film layer and another conductive layer 236 on the hemispherical silicon grain layer 232. The material of the dielectric film layer 234 is, for example, a silicon oxide layer, nitrogen Silicon Dioxide / Silicon Oxide (N〇) Junction (Please read the precautions on the back before filling this page) -7 ^ · Order 11

JU The paper size is in accordance with the Chinese National Standard (CNS) A4 specification (210X297 mm) 408489 4445twf.doo / 002 A7 B7 V. Description of the invention (/ £;) Structure, silicon oxide / silicon nitride / silicon oxide layer (0N0) . The material of the conductive layer 236 is, for example, polycrystalline silicon, and a method of forming the conductive layer 236 is, for example, chemical vapor deposition. FIG. 3A to FIG. 3G are diagrams showing a manufacturing process of a dynamic random access memory according to a preferred embodiment of the present invention. FIG. 15 Please refer to FIG. An isolation region 202, a field effect transistor 304, a bit line (not shown in 7K), and a dielectric layer 310 are formed on 300. Next, referring to FIG. 3B, the dielectric layer 310 is defined by lithography and etching techniques to form a contact window opening 312 in the dielectric layer 310. Then, a polycrystalline silicon layer 314 is formed on the substrate 300 so as to fill the contact window openings 312 so as to be coupled to the source / drain regions 308. The polycrystalline silicon layer 314 has a dopant, such as arsenic or phosphorus, and is formed by, for example, a chemical vapor deposition method, and has a thickness of, for example, 1000 angstroms to 3,000 angstroms. Thereafter, a metal silicide layer 315, a barrier layer 316, and a metal layer 318 are formed on the polycrystalline silicon layer 314. The metal silicide layer 315 is, for example, titanium silicide, and is used as a contact layer of the polycrystalline silicon layer 314 and the barrier layer 316. The material of the barrier layer 316 is, for example, titanium nitride, or titanium nitride and ruthenium ( Ru) composed of a metal layer. The titanium nitride layer is used as a metal diffusion barrier (Metal Diffusion Barrier), and the ruthenium metal layer is used as an oxidation barrier (Oxidation Barrier). The metal layer 3 18 is a part of the lower electrode ', and the material is, for example, ruthenium dioxide (Ru02). Next, referring to FIG. 3C, a hard mask layer 32 and a photoresist layer 322 are formed on the metal layer 318. The material of the hard Qin curtain layer 320 is based on the Chinese paper standard (CNS) A4 size (210x297). (Please read the precautions on the back before filling this page.) Order the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs Print

40B48S 4445twf.d〇c / 002 pj ----: ---- B7 V. Description of the invention (//) (Please read the precautions on the back before filling this page). Electrical layer 310 and metal layer 318, resistance The barrier layer 3U and the polycrystalline silicon layer 314 have a good etching selectivity ratio. The material is, for example, silicon nitride, and the formation method is, for example, a chemical phase deposition method, and the thickness is about 1 Angstrom to 1,000 Angstroms. Then, referring to FIG. 3 (a), the photoresist layer 322 is patterned. The patterned photoresist layer 322 corresponds to the contact window opening 312, and its area is slightly larger than the contact window opening 3U. Then, the patterned photoresist layer 322 is used as a mask, and the hard mask layer 320 is etched. Next, using the patterned photoresist layer 322 and hard mask layer 320 as an etching mask, uranium is etched with a polycrystalline silicon layer 314, a metal silicide layer 315, a barrier layer 316, a metal layer 318, and a dielectric layer 31. So that the polycrystalline sand layer 314, the metal silicide layer 3 15, the barrier layer 3 16 and the metal layer 31S are patterned 'and a groove 323' surrounding the polycrystalline silicon layer 3 I4 is formed in the dielectric 餍 310, the depth of which is about It is 5000 angstroms to 1.5 μm. Since the nitrided sand layer 320 and the polycrystalline silicon layer 3, 4, the metal silicide layer 315, the barrier layer 316, the metal layer 318, or the dielectric layer 21 have a good etching selection ratio, it can be The process of etching the polycrystalline silicon layer 314, the metal silicide layer 315, the barrier layer 316, the metal layer 318, and the dielectric layer 310 is used as a hard mask layer. Therefore, the present invention does not need to form an excessively thick photoresist layer 322. Therefore, it is possible to avoid the printing problem of the consumer co-operatives of the Intellectual Property Bureau of the Ministry of Economics, which is caused by the photoresist layer 322 being too thick. Thereafter, please refer to FIG. 3E to remove the photoresist layer 322. Then, another barrier layer 3 and a metal layer 326 are formed on the substrate 300. The material of the barrier layer 324 is, for example, titanium nitride, or is composed of a titanium nitride and a ruthenium metal layer. The titanium nitride layer is used as a metal diffusion barrier, and the ruthenium metal layer is used as an oxidation barrier. The metal layer 326 is used as a part of the lower electrode. 13 The paper size is applicable to the Chinese national standard (CNS) A4 (210X297 mm) A7 B7 4445twf .doc ^ g ^ g ^ 5. Description of the invention (/ 2), The material is, for example, ruthenium dioxide. Then, referring to FIG. 3F, perform anisotropic etch-back to remove the barrier layer 324 and the metal layer 326 covering the dielectric layer 310, so that the polycrystalline silicon layer 314 and the metal silicide layer 3 I5 are left. The barrier layer 324, the barrier layer 316, the metal layer 318, and the sidewall of the groove 323 and the metal layer 326 form a conductor gap 330. Afterwards, please refer to FIG. 3G, remove the hard mask layer 320 to expose the electrode body under the structure of the polycrystalline silicon layer 314, the metal silicide layer 315, the barrier layer 316, the metal layer 318, and the conductive spacer 330. . The method for removing the hard mask layer 320 includes wet etching, such as using hot phosphoric acid as an etching solution. Next, a dielectric film layer 334 is formed on the substrate 300, and a conductive layer 336 is formed as an electrode on the capacitor. The material of the dielectric film layer 334 is, for example, pentoxide (Ta205), Pb (Zr, Ti) 03, that is, PZT and (Ba, Sr) Ti03, that is, high dielectric constant materials such as BST. The material of the conductive layer 336 is, for example, aluminum, and it is preferable to form a layer of titanium nitride as a barrier layer before forming aluminum. The method for forming metal aluminum and titanium nitride is, for example, a sputtering method. The capacitor according to the second embodiment of the present invention has a metal-insulator-metal (MIM) structure, and has a characteristic of low interfacial reaction, so the performance of the capacitor can be improved. Moreover, since the polycrystalline silicon is implanted in the opening of the contact window, the leakage phenomenon caused by the contact between the metal layer and the source / drain region can be avoided. In addition, the present invention can use a dielectric film layer with a high dielectric constant, including pentoxide, BST and PZT, to increase the storage capacity of the capacitor ° This paper size applies the Chinese National Standard (CNS) A4 specification (210X2,97 Mm) {Please read the notes on the back before filling this page) Order printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 4 44 5 twf .doc ^ oQP ^ '6 9 A7 B7 V. Description of Invention (P) As mentioned, the present invention has the following advantages: 1. The present invention utilizes the formation of grooves without the need to form a very thick amorphous silicon layer, so the time for depositing the amorphous silicon layer can be reduced, the production capacity can be improved, and Reduced furnace tube operating costs and difficulty in etching thick amorphous T silicon layers. 2. The present invention can increase the surface area of the electrodes below the capacitor to increase the storage capacity of the capacitor. 3. The present invention can be used for manufacturing a capacitor having a dielectric film layer having a high dielectric constant. 4. The capacitor of the present invention has a metal-insulation-metal structure, which can improve the performance of the capacitor. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and decorations without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application. (Please read the precautions on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs This paper applies the Chinese National Standard (CNS) A4 specification (210X297 mm)

Claims (1)

ABCD 408489 444 5twf.doc / 002 6. Scope of patent application (please read the precautions on the back before writing this page) 1. A method for manufacturing dynamic random access memory, in which a substrate provided has been formed There is a field effect transistor, and the field effect transistor includes a source / drain region. The method includes the following steps: forming a dielectric layer on the substrate; forming a contact window opening in the dielectric layer, the A contact window opening exposes the source / drain region; forming a first conductor layer on the substrate to fill the contact window opening; patterning the first conductor layer; A portion of the dielectric layer covered by the dielectric layer is removed to form a groove in the dielectric layer; a conductor gap is formed on a side wall of the groove and a side wall of the first conductor layer; A dielectric film layer is formed on the conductor gap wall; and a second conductor layer is formed on the dielectric film layer. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 2. The method for manufacturing a dynamic random access memory as described in item 1 of the scope of patent application, wherein the material of the first conductor layer and the gap between the conductors includes amorphous silicon. 3. The method for manufacturing a dynamic random access memory according to item 2 of the scope of the patent application, wherein after the conductor gap is formed on the sidewall of the groove and the sidewall of the first conductor layer, the first conductor layer is Before forming the dielectric film layer on the conductor gap wall, the method further includes forming a selective hemispherical silicon grain layer on the first conductor layer and the conductor gap wall. This paper size applies to Chinese National Standard (CNS) A4 specification (210X297 mm) ABCD 408488 4445twf.d〇c / 002 VI. Application for patent scope 4. The dynamic random access memory as described in item 1 of the scope of patent application The manufacturing method, wherein the steps of patterning the first conductor layer and forming a groove in the dielectric layer include: forming a hard mask layer on the first conductor layer; forming a hard mask layer on the hard mask layer; Photoresist layer; patterning the photoresist layer and the hard mask layer; using the photoresist layer and the hard mask layer as a mask, etching the first conductor layer and the dielectric layer; and removing the photoresist Layer and the hard cover curtain layer. 5. The method for manufacturing a dynamic random access memory as described in item 4 of the scope of patent application, wherein the material of the first conductor layer and the gap between the conductors includes amorphous silicon. 6. The method for manufacturing a dynamic random access memory according to item 5 of the scope of patent application, wherein after forming the conductor gap between the sidewall of the groove and the sidewall of the first conductor layer, the method is applied to the first conductor layer. Before forming the dielectric film layer on the conductor gap wall, the method further includes forming a selective hemispherical silicon grain layer on the first conductor layer and the conductor gap wall. 7. The method for manufacturing a dynamic random access memory according to item 1 of the scope of patent application, wherein after forming the conductor gap between the sidewall of the groove and the sidewall of the first conductor layer, the method is applied to the first conductor layer. Before the dielectric film layer is formed on the gap between the conductor and the conductor, the method further includes forming a hemispherical silicon grain layer on the first conductor layer and the gap between the conductor. 8. A method for manufacturing a dynamic random access memory, in which a field effect transistor has been formed on a substrate provided, and the field effect transistor includes the paper standard applicable to the Chinese National Standard (CNS) A4 specification (210 × 297) (Mm) ^ —-------- install— (please read the precautions on the back before filling this page). 1T printed by the Intellectual Property Bureau Employee Consumer Cooperatives of the Ministry of Economic Affairs 408489 as 4445twf, doc / 002 5g 6. Scope of patent application: A source / drain region, the method includes the following steps: forming a dielectric layer on the substrate; (please read the precautions on the back side before filling in this page) forming a dielectric layer in the dielectric layer A contact window opening, the contact window opening exposing the source / drain region; forming a polycrystalline silicon layer on the substrate to fill the contact window opening; forming a first biliary barrier on the polycrystalline silicon layer Forming a first metal layer on the first barrier layer; patterning the polycrystalline silicon layer, the first barrier layer, and the first metal layer; and covering the first metal layer without the first metal layer The dielectric layer is partially removed to form a layer in the dielectric layer. Forming a second barrier layer on the substrate; forming a second metal layer on the second barrier layer; etching back the second metal layer and the second barrier layer to form a second barrier layer A sidewall and the polycrystalline silicon layer, the first barrier layer and the sidewall of the first metal layer form a conductor gap; a dielectric film layer is formed on the first metal layer and the conductor gap; and the Ministry of Economic Affairs The Intellectual Property Bureau employee consumer cooperative prints a conductive layer on the dielectric film layer. 9. The method for manufacturing a dynamic random access memory according to item 8 of the scope of the patent application, wherein the material of the first metal layer and the second metal layer includes ruthenium dioxide. 10. The method for manufacturing a dynamic random access memory as described in item 9 of the scope of the patent application, wherein the material package of the first barrier layer and the second barrier layer is 1 S. This paper size is applicable to Chinese national standards (CNS ) A4 specification (210X297mm) 4 Hold 4SS 〇A8 4445twf.doc / 002 D8, the scope of patent application includes Nitrogen. (Read the precautions on the back before you fill in this page) Π. The method for manufacturing a dynamic random access memory as described in item 9 of the scope of patent application, wherein the first barrier layer and the first conductor layer It further includes a metal silicide layer, and the material of the first barrier layer and the second barrier layer includes a titanium nitride layer and a ruthenium metal layer. 12. The method for manufacturing a dynamic random access memory as described in item 8 of the scope of patent application, wherein the dielectric film layer includes one of pentoxide, BST, and PTZ. 13. The method of manufacturing a dynamic random access memory according to item 12 of the patent application, wherein the conductor layer includes a titanium nitride layer and an aluminum layer. 14. The method for manufacturing a dynamic random access memory as described in item 8 of the scope of patent application, wherein the conductor layer includes a titanium nitride layer and an aluminum layer. 15. The method for manufacturing a dynamic random access memory according to item 8 of the scope of patent application, wherein the polycrystalline silicon layer, the first barrier layer and the first metal layer are patterned and the dielectric layer is formed. The step of forming a groove in the method includes: forming a hard cover curtain layer on the first metal layer; forming a photoresist layer on the hard cover curtain layer; and printing the photoresist by a consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. Patterning the hard mask layer and the hard mask layer; using the photoresist layer and the hard mask layer as a mask, etching the polycrystalline silicon layer, the first barrier layer, the first metal layer, and the dielectric layer; And removing the photoresist layer and the hard mask curtain layer. 16. The method for manufacturing a dynamic random access memory as described in item 15 of the scope of the patent application, wherein the material of the first metal layer and the second metal layer 1 9 This paper size is applicable to China National Standards (CNS) Α4 Specifications (210 × 297 mm) 4 44 5twf, dc40d846S B8 D8 6. The scope of patent application includes ruthenium dioxide. 17. The method for manufacturing a dynamic random access memory according to item 16 of the scope of patent application, wherein the material of the first barrier layer and the second barrier layer includes titanium nitride. 18. The method for manufacturing a dynamic random access memory according to item 16 of the scope of patent application, wherein a metal silicide layer is further included between the first barrier layer and the first conductor layer, and the first resistor The material of the barrier layer and the second barrier layer includes a titanium nitride layer and a ruthenium metal layer. 19. The method for manufacturing a dynamic random access memory according to item 15 of the scope of patent application, wherein the dielectric film layer includes one of tantalum pentoxide, BST, and PZT. 20. The method for manufacturing a dynamic random access memory according to item 15 of the patent application, wherein the conductor layer includes a titanium nitride layer and an aluminum layer. (谙 Please read the notes on the back before filling this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs