531469531469
五、發明說明S 發明領域： 別3本發明係有關於一種化學機械研磨 疋有關於一種適用於半導體之銅金屬 ’可有效地防止銅金屬結構在研磨 發明背景： ^ ^者南性能積體電路之需求日增及 =日益縮小，多重金屬内連線已成為在 =電阻值的必要方式。多重金屬内連線 曰的内連線區隔，而上下層的金屬連線 相連。多重金屬連線是由一層金屬内連 方式層層疊疊形成，其中在金屬層與介 成一金屬擴散障礙層以防止金屬材/質的 力，金屬擴散障礙層的例子如TaN、Ta， 、及CoWP等。在整個製程中，每穿 一 圓起伏的表面加以平坦化的動作，以利 的製作能較精確且容易地進行。金屬内 平坦化通常以化學機械研磨 Polishing，CMP)的方式達成。 為了達到更好的傳輪效率，高效能 導電性的要求也相對提高。傳統上半導 遍以鋁金屬製成，然而鋁金屬偏高的電 之尺寸日益縮減’内連線導電性要求持 制了鋁金屬在新一代積體電路中之應用 金’銅金屬的高傳導性，高延展性了低 之方法。本發明特 化學機械研磨方法 受到破壞。 電路元件之尺寸設 縮小導線長度，減 系以介電層將不同 則經由插塞（plug) 線、一層介電層的 電層之間通常會形 擴散並增加附著 .TiN、TaSiN、WN 層即需要進行將晶 下一層金屬内連線 連線製程中各層的 卜mechanical 積體電路對内連線 體元件間的導線普 阻在積體電路元件 續提高的趨勢下限 。相對於鋁及其合 電阻常數、高電子V. Description of the invention S Field of the invention: No. 3 The present invention relates to a chemical mechanical polishing, and a copper metal suitable for semiconductors can effectively prevent the copper metal structure from being ground during the grinding. BACKGROUND OF THE INVENTION: The demand is increasing day by day and the value is shrinking. Multi-metal interconnects have become a necessary method for the resistance value. Multi-Metal Interconnects The interconnects are separated, while the upper and lower metal interconnects are connected. The multi-metal connection is formed by layer-by-layer metal interconnection, in which a metal diffusion barrier layer is interposed between the metal layer and the metal material / mass force. Examples of metal diffusion barrier layers such as TaN, Ta, and CoWP Wait. Throughout the entire process, each rounded undulating surface is flattened so that the production can be carried out more accurately and easily. In-metal planarization is usually achieved by chemical mechanical polishing (CMP). In order to achieve better transmission efficiency, the requirements for high-performance electrical conductivity are also relatively increased. Traditionally, semi-conductors are made of aluminum metal, but the high electrical size of aluminum metal is shrinking. The interconnect conductivity requires the application of aluminum metal in the new generation of integrated circuits. The high conductivity of copper metal The method with high ductility and low ductility. The special chemical mechanical polishing method of the present invention is damaged. The size of the circuit components is set to reduce the length of the wire, and the reduction is caused by the dielectric layer. The plug layer and the electrical layer of a dielectric layer usually diffuse in shape and increase adhesion. TiN, TaSiN, WN layers are It is necessary to carry out the mechanical resistance of each layer in the process of connecting the metal interconnects of the next layer to the lower limit of the trend of increasing the general resistance of the wires between the interconnect components. Relative to aluminum and its combined resistance constant, high electrons
531469 五、發明說明（2) 遷移阻抗等特性使得鋼金屬内連線具有較快的傳導速产， 非常符合高性能積體電路的需求，被視為未來金屬内&線 之主流。本發明即針對銅金屬内連線之CMP製程作研究改 良，然本發明之成果亦可應用於其它材料之CMp製程，並 不限於銅金屬之CMP製程。 CMP，基本上是利用一研磨墊（p〇1丨以丨叫配合適 當的研磨劑（slurry)把晶圓表面磨平的一個平坦化技術， 其研磨的方式可以為旋轉式（r〇tary)或線性式（Hnear)。 —以旋轉式CMP為例，請參見第j目，為一旋轉式cMp裝 置不思圖，其主要由研磨台（p〇Ushing 、研磨 墊12、研磨劑分佈系統14、及晶圓載具（wafer 16構成，其中的研磨墊22為非導體材質。CMp製程進行時 ，晶圓1 8由晶圓載具自背面抓住，使其正面朝向研磨墊！ 2 ，適當的研磨劑19經由研磨劑分佈系統14加到研磨墊”與 晶圓表面之間，藉著晶圓載具16和研磨台1〇朝一定的方^ 旋轉的力量及研磨劑1 9與晶圓丨8表面的作用而達到平坦化 晶圓表面的目的。 *利用上述傳統方式進行銅金屬内連線平坦化之晶圓表 面韦有銅導線遭到侵蝕（corrosion)以類似銹化的方式破 壞内連線結構的現象，其侵蝕深度可達3〇〇〇至4〇〇〇 A， =品良率造成極大的影響。銅内連線結構的侵蝕不但造成 更造成資源浪費，本發明即針對此—問題提出 發明之目的及概述： 第5頁 531469 五、發明說明（3) 為解決上述問題，本發明提供一籀 以有效解決傳統製程中晶圓結構遭受侵餘損^的肝方題[ 傳統CMP製程中係全程使用研磨劑、通 明方法之特徵在於配合一抗侵：之磨:1 制進二研咸磨,、’二本/ 結構侵蝕的問題。本發明之抑制劑為含 ^夕a曰圓表面 化效果並不會對半導體結構或製程造 ：=工防亡f 併三嗤（benZQtriaz〇le，_。成傷害的成份’如苯 實施例·· 接下來配合第2A至2D圖，以銅金屬内連線製程中 坦化，配合BTA抑制劑為例，對本發明化學機械研磨（cMp) 之方法作進一步說明。 一明參見第2A圖，首先在一具有任何所需之半導體元件 的半導體基底200，如一矽基底上進行銅金屬内連線製程 。在此半導體基底20 0上形成一介電層21()，並以適當的蝕 刻技術於介電層中形成具有内連線溝槽之鑲嵌式開口及/ 或具有内連線溝槽及接觸孔之雙鑲嵌式開口，在圖示中以 具有内連線溝槽220a及接觸孔220b之雙鑲嵌式開口220 表示之。 清參見第2B圖，接著形成一用來防止銅金屬擴散的金 屬擴散障礙層230，其材質可為如TaN、Ta、TiN、TaSiN、 W N、及C o W P專，本實施例以形成一 τ a N層為例，其覆蓋鑲 嵌式開口 /雙鑲嵌式開口 220之侧壁及内金屬介電層21 〇的 表面。 請參見第2C圖，在形成金屬擴散障礙層23〇後，形成531469 V. Description of the invention (2) The characteristics such as migration impedance make the steel-metal interconnects have a fast conduction and rapid production, which is in line with the requirements of high-performance integrated circuits, and is regarded as the mainstream of metal & wires in the future. The present invention is to improve the CMP process of copper metal interconnects, but the results of the present invention can also be applied to the CMP process of other materials, and is not limited to the CMP process of copper metal. CMP is basically a flattening technology that uses a polishing pad (p01) to smooth the surface of the wafer with a suitable slurry. The polishing method can be rotary. Or linear (Hnear). —Take rotary CMP as an example, see item j. It is a schematic diagram of a rotary cMp device, which is mainly composed of a polishing table (p0Ushing, polishing pad 12, abrasive distribution system 14). , And wafer carrier (wafer 16), where the polishing pad 22 is made of a non-conductive material. During the CMP process, the wafer 18 is held by the wafer carrier from the back side, so that the front side faces the polishing pad! 2, appropriate polishing The agent 19 is added to the polishing pad through the abrasive distribution system 14 and the surface of the wafer. The wafer carrier 16 and the polishing table 10 rotate in a certain direction ^ and the force of the abrasive 19 and the surface of the wafer 8 To achieve the purpose of flattening the wafer surface. * The surface of the wafer with copper metal interconnects flattened by the traditional method described above has copper conductors corroded to destroy the interconnect structure in a similar manner to rust. Phenomenon, its erosion depth can reach 300. To 4000A, = the yield rate has a great impact. The corrosion of the copper interconnect structure not only causes a waste of resources, the present invention aims at this problem. The purpose and summary of the invention are as follows: Page 5 531469 5. Explanation of the invention (3) In order to solve the above-mentioned problems, the present invention provides a solution to effectively solve the liver problem of traditional wafer processes that suffer from excess damage ^ The traditional CMP process uses abrasives throughout, and the clear method is characterized by coordination First anti-aggression: grinding: 1 system into the second research salt grinding, 'two books / structure erosion problem. The inhibitor of the present invention contains the surface effect of ^ Xi a said circle will not make semiconductor structures or processes: = Industrial protection f and benZQtriaz〇le, _. The ingredients that cause harm, such as the benzene embodiment. Next, with the 2A to 2D diagrams, the copper metal interconnect process is used to make it frank, and the BTA inhibitor is used as For example, the method of chemical mechanical polishing (cMp) of the present invention is further explained. Referring to FIG. 2A, first, a copper metal interconnection process is performed on a semiconductor substrate 200 having any desired semiconductor elements, such as a silicon substrate. A dielectric layer 21 () is formed on the semiconductor substrate 200, and a damascene opening having interconnecting trenches and / or having interconnecting trenches and contact holes are formed in the dielectric layer by an appropriate etching technique. Double inlay openings are shown in the figure as double inlay openings 220 with interconnecting grooves 220a and contact holes 220b. Refer to Figure 2B, and then form a metal diffusion barrier layer to prevent copper metal from diffusing. 230, whose material can be TaN, Ta, TiN, TaSiN, WN, and Co WP. This embodiment takes the formation of a τ a N layer as an example, which covers the sidewall of the mosaic opening / dual mosaic opening 220. And the surface of the inner metal dielectric layer 21 〇. Referring to FIG. 2C, after the metal diffusion barrier layer 23 is formed,
531469 五、發明說明（4) 一銅金屬層240以填滿具有金屬擴散障礙層23〇的 口 220並且延伸於介電層21〇表面。 鎮瓜式開 請參見第2D圖，接下來進行晶圓表面之平坦 二使Λ研磨劑及抑制劑的方式進行CMp，將延伸於介電/ 21〇表面及*需要之銅金屬24〇及金屬擴散障 ^ ，得一平坦之銅金屬内連線結構24 2。 川移除 上述CMP進行時，以一晶圓载體將晶圓抓 面與CMP研磨台上的研磨墊接鎚 时 ^ 彳史八表 旋轉或線性移動，<吏晶圓=二f由研磨台及晶圓的 進行研磨的動作。一段時間後;：1及研磨劑磨擦’以 寺所、夕目^ ^ t / 後停止研磨劑的分佈，加入前 ΐ = ΐ ί 抑制劑並繼續研磨，此處的具有抗 =果之：制劑以ΒΤΑ為例，其可經由分佈研磨劑的同 一分佈糸統或經由另外一個八德 ^ ^ pe A 個刀佈糸統加到研磨墊與晶圓表 L 添加量為〇』2%至0.2%。一段時間後 將研磨劑及抑制劑：交磨劑並繼續研磨。如此 製程中的平坦化步驟= 整。在銅金屬内連線 使用BTA作為抑制劑為例，左可由有本^明之方法進行⑽:以 侵蚀破壞的現象，即使在少1 數有效減少晶圓表面結構受到 深度經測量小於200 A 文到侵餘的部份’其再侵姓 為使本發月之製私更加明白，請參見第3圖，係利用 0503-7189TWF ； TSMC2001-1024 ； Isabelle.ptd 531469 五、發明說明（5) 本發明之CMP方法製作銅金屬内連線之流程圖。首先提供 一半導體基底，如一矽基底，其上具有任何所需之半導體 元件；在此半導體基底上形成一内金屬介電層，產於其中 形成鑲嵌式開口 /雙鑲嵌式開口；在鑲嵌式開口 /雙鑲嵌式 開口底部及側壁，及内金屬的表面，形成一金屬擴散障礙 層；接著填入銅金屬，以填滿鑲嵌式/雙鐵嵌式開口並且 延伸至内金屬介電層的表面。接下來進行晶圓表面之平坦 化，藉由一晶圓載具（wafer carrier)將半導體基底固定 於一 CMP研磨裝置中，該CMP研磨裝置除了具有上述晶圓載 具外，還包含一研磨台（p〇lishing table)、置於研磨台 上的研磨墊（pad)、及研磨劑分佈系統，亦可視需要增加 一抑制劑分佈系統。CMP進行時，晶圓由晶圓載具自背面 m其正面朝向研磨墊’適當的去除銅金屬的研磨劑 η系統加到研磨墊與晶圓表面之間，藉著晶 ，載具和研磨t台朝的方向旋轉或移_力量及研磨劑 與曰曰圓表面的作用對銅金屬進行研磨。一 研磨劑的分佈，並加入抑制劑繼/一 _夺間後’分止 由研磨劑分佈系統加入，或經ώ s 抑制剤』、、工 心六方你田m…立 a、&由另一分佈系統加入。如此 以父互使用研磨劑及抑制劑的方 伸於介電層表面及不需要；金細，將延 的金屬擴散障礙層研磨劑，配合抑㈣Ϊ;使Ξ者;= 進行CMP，將不需要的金屬擴散 ;:二移除後，即传-平坦且未受侵餘破壞之銅金屬内連531469 V. Description of the invention (4) A copper metal layer 240 fills the opening 220 with the metal diffusion barrier layer 23o and extends on the surface of the dielectric layer 21o. Please refer to Figure 2D for the quasi-melon-type opening. Next, carry out the flattening of the wafer surface, and then use the Λ abrasive and inhibitor to carry out CMP. The diffusion barrier ^ gives a flat copper metal interconnect structure 24 2. When Chuan removes the above CMP, when a wafer carrier is used to connect the wafer gripping surface with the polishing pad on the CMP polishing table, ^ Shi Ba table rotates or linearly moves, < wafer = two f by polishing Table and wafer polishing operation. After a period of time :: 1 and the abrasive rubbing 'Yi Temple, Xi Mu ^ ^ t / stop the distribution of the abrasive, add the former ΐ = ΐ ί inhibitor and continue grinding, where the resistance = fruit: preparation Take BTA as an example, it can be added to the polishing pad and the wafer table L through the same distribution system of the distributed abrasive or through another Bade ^ pe A knife cloth system. The addition amount is 0% to 0.2%. . After some time, the abrasive and inhibitor: cross abrasive and continue grinding. In this way, the flattening step in the process = trimming. The use of BTA as an inhibitor in copper metal interconnects is taken as an example. The method can be performed according to the following method: Take the phenomenon of erosion and destruction, even if it is less than one, it can effectively reduce the depth of the wafer surface structure. The depth is measured to less than 200 A. The part of the surplus is to re-invade the family name to make it clearer. Please refer to Figure 3, which uses 0503-7189TWF; TSMC2001-1024; Isabelle.ptd 531469 5. Description of the invention (5) The invention The CMP method is a flow chart for making copper metal interconnects. First, a semiconductor substrate, such as a silicon substrate, is provided with any desired semiconductor components thereon; an internal metal dielectric layer is formed on the semiconductor substrate, and a damascene opening / dual damascene opening is formed therein; in the damascene opening The bottom and side walls of the / dual mosaic opening and the surface of the inner metal form a metal diffusion barrier layer; then copper metal is filled to fill the mosaic / dual iron recessed opening and extend to the surface of the inner metal dielectric layer. Next, the wafer surface is planarized. The semiconductor substrate is fixed in a CMP polishing device by a wafer carrier. The CMP polishing device includes a polishing table (p) in addition to the wafer carrier. 〇lishing table), a polishing pad (pad) placed on the polishing table, and an abrasive distribution system, and an inhibitor distribution system may be added as needed. During the CMP, the wafer is loaded from the wafer carrier from the back side to the polishing pad 'by a suitable system for removing copper metal. The system is added between the polishing pad and the surface of the wafer. Rotate or move in the direction of the force and the role of the abrasive and round surface to polish copper metal. The distribution of an abrasive, and the addition of an inhibitor, followed by a _ _ after the break, is added by the abrasive distribution system, or through the free s to inhibit the "," the work of mind six parties you field m ... Lia, & from another A distribution system was added. In this way, the side that uses the abrasive and the inhibitor mutually extends on the surface of the dielectric layer and is not needed; the gold is fine, and the extended metal diffusion barrier layer abrasive is combined with the inhibitor; the agent is; = CMP is not needed Metal diffusion ;: after removal, it will pass-flat and unbroken copper metal interconnect
第8頁 531469 五、發明說明（6) 依據本發明上述方 其半導體結構受到侵蝕 少數受到侵蝕的部份， 相較於傳統方法中常常 改善許多，足見本發明 構侵蝕的問題實為一簡 結構的製程中，對產品 雖然本發明已以實 本發明，任何熟習此技 内’當可作更動與潤飾 之申請專利範圍所界定 法進行銅金屬内連線CMP之晶圓， 破壞的情況有顯者的改善，即使在 其再侵蝕深度經測量小於2 〇 〇人， 有深達30 0 0至40 0 0 A侵蝕的現象已 對於改善在CMP製程中晶圓表面結 便且有效的方法，尤其在銅内連線 良率的提昇有極大的幫助。 施例揭露如上，然其並非用以限定 藝者’在不脫離本發明之精神範圍 ’因此本發明之保護範圍當視 者為準。 +茶Page 8 531469 V. Description of the invention (6) According to the present invention, the semiconductor structure is eroded and a few eroded parts are often improved compared with the traditional method, which shows that the problem of structural erosion of the present invention is a simple structure. In the manufacturing process, although the present invention has been implemented in the present invention, any person familiar with this technology should perform copper metal interconnect CMP wafers as defined in the scope of patents that can be modified and retouched. The damage is obvious. The improvement of this method is that even if the re-etching depth is less than 2000 people, the phenomenon of erosion with a depth of 300-400 A has already been an effective method for improving the surface formation of wafers in the CMP process, especially Improving the yield of copper interconnects can greatly help. The embodiment is disclosed as above, but it is not used to limit the artist's without departing from the spirit scope of the present invention. Therefore, the protection scope of the present invention shall prevail. + Tea
531469 圖式簡單說明 第1圖係旋轉式CMP裝置示意圖。 第2 A〜2D圖係依據本發明之一實施例之銅金屬内連線 製程剖面流程圖。 第3圖係依據本發明之一實施例之銅金屬内連線製程 之方塊流程圖。 符號說明： 1 0〜研磨台； 1 2〜研磨墊； 1 4〜研磨劑分佈系統； 1 6〜晶圓載體； 1 8〜晶圓； 1 9〜研磨劑； 2 0 0〜半導體基底； 21 0〜介電層； 220〜鑲嵌式開口； 220a〜内連線溝槽； 220b〜接觸孔； 2 3 0〜金屬擴散障礙層； 240、242〜銅金屬。531469 Brief description of drawings Figure 1 is a schematic diagram of a rotary CMP device. Figures 2A to 2D are cross-sectional flowcharts of a copper metal interconnect process according to an embodiment of the present invention. FIG. 3 is a block flow diagram of a copper metal interconnection process according to an embodiment of the present invention. Explanation of symbols: 1 0 to polishing table; 1 2 to polishing pad; 1 4 to abrasive distribution system; 16 to wafer carrier; 18 to wafer; 19 to abrasive; 2 0 to semiconductor substrate; 21 0 ~ dielectric layer; 220 ~ mosaic opening; 220a ~ interconnecting trench; 220b ~ contact hole; 230 ~ metal diffusion barrier layer; 240, 242 ~ copper metal.
0503-7189TWF ； TSMC2001-1024 ； Isabelle.ptd 第10頁0503-7189TWF; TSMC2001-1024; Isabelle.ptd page 10