TW530387B - DRAM formation method - Google Patents

Abstract

A DRAM formation method is provided, which comprises the following steps: (1) forming the first through hole in the semiconductor substrate; (2) depositing through hole; removing a part of the arsenic silica glass or phosphorous silica glass above the substrate; (4) conducting thermal treatment to drive the arsine or phosphorus ions of the arsenic silica glass or phosphorous silica glass into the substrate to form a conductive doped region; (5) removing the arsenic silica glass or phosphorous silica glass; (6) forming a dielectric layer along the surfaces of the substrate and conductive doped region, wherein the dielectric layer can be used as the dielectric film of a transistor gate or a capacitor; (7) forming a conduction layer on the dielectric layer and fill up the through hole; (8) removing a part of the conduction layer and defining the gate structure of a transistor and the second electrode of a capacitor simultaneously; (9) forming the lightly doped drain; (10) forming spacers on the sidewalls of the transistor and capacitor; and (11) forming the source and drain of the transistor.

Description

530387 V. Description of the invention α) Field of the invention: The present invention relates to a method for forming a dynamic random access memory, in particular to a method for forming a dynamic random access memory of a single polycrystalline silicon. BACKGROUND OF THE INVENTION Semiconductor semiconductor substrates generally include a logic element region and a dynamic random access memory (DRAM) region. The logic element region has a plurality of transistors, and the DRAM region also has a transistor. Dynamic random access memory is a kind of main volatile (v ο 1 a t i 1 e) memory, which is composed of a transistor and a capacitor. One end of the capacitor is connected to the doped region of the transistor, and the other end of the capacitor is connected to the reference potential. Through the electrical contact between the capacitor and the source region, digital information is stored in the capacitor, and the metal-oxygen half field effect An array of transistors (MOSFET), word lines (words ine) and bit lines (bit Π ne) are used to obtain the digital data in the capacitor. With the progress of the semiconductor industry, the accumulation of dynamic random access memory has also increased rapidly, making the size of the capacitors that make up DRAM also

Page 5 5. Description of the invention (2) The followers are greatly reduced. From ~ s' ~ ------- The surface area of the board is determined by the capacitor storage capacity of the capacitor storage capacity will be the size of the capacitor ;: soil and capacitor electrode capacity method has been greatly reduced. Therefore, the first is to reduce the capacitance, which means that the dielectric between the electrode plates is (丨) with a high dielectric constant; ′ generally increases the thickness of the capacitor storage layer. (3): Force ° (2) Reduction of electricity: J 枓 acts as two types of capacitors, increasing capacitor error V2, electrode in container :::;, board: dielectric and structure have been developed :; based on the principle of capability Electricity: Device: Fang 1 In order to increase the capacitor's process structure including m, Λ, some under-line capacitors have been developed (C woodworking Tuner, stacked capacitors, $ 1 with hemispherical grains) Q]: jnder bi t 1 lne (CUB), /, thunder line on the bit line of the sun and the eve of the sun, S: 突 ύ 突 4 * 生 [C〇B] CeU '^' th h, SPheriCal-㈣ n ⑽) ;; ^ ”nods) > ^ i con storage., '' (Crown shape) or hollow cylindrical structure (cylindrical structure) capacitors, etc., In order to reduce the buried buried capacitor structure in order to reduce the buried The manufacturing cost of in-line DRAM is usually to integrate the logic circuits on the semiconductor semiconductor substrate with the DRAM process to simplify the manufacturing steps and reduce the design rules (deSlgn rule). As for the process of dynamic random access memory for bit-line capacitors For the technology, please refer to "Method for" disclosed in U.S. Patent No. 5 8 9 3 7 3 4 fabricating capac 11 or-under-b 11 lme 530387 V. Description of the invention (3) (CUB) dynamic random access memory (DRAM) using tungesten landing plug contacts 1. Due to the manufacture of general DRAM, three or four polycrystalline silicon layers are usually formed. This is very unfriendly to a logic foundry, and it is very difficult to merge with a high-performance logic process for a so-called system integration chip (SOC). Therefore, the present invention proposes A method for fabricating dynamic random access memory to solve the above problems. Purpose and summary of the invention: The purpose of the present invention is to provide a method for forming a dynamic random access memory of a single polycrystalline silicon to reduce the dynamic random access memory. Manufacturing cost. Another object of the present invention is to provide a method for forming a single polysilicon dynamic random access memory to integrate a logic circuit on a semiconductor semiconductor substrate with a DRA M process, thereby simplifying process steps and reducing design rules. ). According to an embodiment of the present invention, the proposed dynamic random Methods of making memory comprising the steps of:

Page 7 530387 V. Description of the invention (4) 1 quality C mixed with a mixed base substrate semi-conductor-for perforation-section forming \) / 2 The fully filled substrate sub-substrate for semi-conductive glass layer Sedimentation through 3 〇 / IV layer 〇 glass porosity removal \) y 4 silicon caused by the quality of the 'hybrid' mixed with the heat part to apply the part of the glass on the bottom of the glass substrate broken base of the body's physical impurities are partially mixed Positioning the shape of the shape of the substrate can be used as the substrate can be semi-doped in the body-domain conduction region to the dopant-doped conductive dopants, among the layer-domain glass region doped with silicon doped with Av AMV white white matter doped with an impurity The quality of the layered glass is doped with a 5-conductor C doped to remove the doped surface area. A semi-conductor integrated with the electrode base is formed along the edges, and the capacitors of the layered dielectric and the gate-gate crystal of the film dielectric are allowed. . Middle-membrane perforation-the fully filled layer on top of the layer is formed by the layer conductivity, and the capacitors 8 and C are charged with the layer electrode, and the light-weight body is doped with the heteropole and the gate electrode. The electric crystal of the crystal is defined as a shaped pole. The device on the upper wall side holds electricity and body. The crystal power source is formed in the form of a gap between the wall electrode and the wall electrode. After forming the above-mentioned drain and source electrodes, it further includes the following steps: (1) forming an insulating layer on the semiconductor substrate. (2) Form a second through hole in the insulating layer. (3) forming a conductive material in the second perforation. In addition, the impurity-doped silica glass layer includes an arsenic silica glass layer or a phosphosilicate glass layer, and a deposition method thereof includes a chemical vapor deposition method (Chemica 1 Vapor Deposition; CVD). A method of forming an impurity-doped silica glass layer includes an etch-back method.

TI— IX

Page 8 530387 V. Description of the invention (5) In addition, the temperature of the above heat treatment is about 900 to 1100 degrees Celsius, and the method of removing the glass layer doped with impurities includes a wet worming method. In addition, the dielectric layer is one selected from the group consisting of a composite thin film including Ta 20 5, Ti02, PZT, BST, N / 0, 0 / N / 0, and the conductive layer includes polycrystalline silicon, and the insulating layer includes an oxide layer. . Detailed description of the invention: The object of the present invention is to provide a method for forming a dynamic random access memory of a single polycrystalline silicon, so as to reduce the manufacturing cost of the dynamic random access memory. Another object of the present invention is to provide a method for forming a single polysilicon dynamic random access memory to integrate a logic circuit and a dram process on a semiconductor semiconductor substrate, thereby simplifying process steps and reducing design rules. ). The invention provides a method for forming a dynamic random access memory of a single polycrystalline silicon. The present invention is described in detail in a preferred embodiment as follows: Please refer to FIG. 1. First, a first perforation is formed in a shallow trench isolation (STI) 12. A P-well (PW, PW) is formed. ) And N-well (N well) semiconductor substrate 10. its

Page 9 530387

V. Description of the invention (6) The semiconductor substrate 10 may be a <. ί 0 0 > or, < 1 11:〉 σσ early crystal silicon in the crystal orientation or a silicon substrate (si 1 on an insulating layer) 1 (: 0 I Ί (DI1 i) 1 S 1 j 1 at (3 r:, SOI), etc. 0 and shallow trench isolation domain 1: used to generate insulation 1 to form an isolation area in the middle. As the above process is It is produced by the technology known in the past, but not the focus of the present invention, so it will not be described in detail. Next, a silicon glass layer doped with impurities 16 is deposited on the semiconductor substrate 1 () and the shallow trench isolation region 12 and filled with the first perforation (hole) 0 where the impurity-doped silica glass layer 1 (bubble-containing silica glass layer or stone ion silica glass layer (that is, silica glass doped with Kun or stone type (As〇r P doped SL 1 icat ( g 1 as, S) layer) 〇 Please refer to the figure __ remove the semiconductor substrate 10 and the shallow trench isolation region Silica glass layer doped with impurities on top of 1 2 () ° / ,, n After using the 孰 / ,,, diffusion principle, the silicon glass layer with impurities 1 (3 埶 /, ', A conductive doped region is formed so that impurities (for example, Shishen or Shiyi ions) in the silica glass layer 16 doped with impurities are introduced into the semi-conductor substrate 10 ° 1 8 is used as the first electrode (also called the lower electrode) of the capacitor. 〇 Please refer to the figure to remove the impurity-doped silica glass layer 1 f) ° y, ,, and along the semiconductor substrate 1 (), A dielectric layer 2C is formed on the surface of the shallow trench isolation region 12 and the conductive doped region 18) The dielectric layer 20 is used not only as a dielectric layer of a capacitor but also as a gate of a transistor A dielectric layer 0, and then a conductive layer 22 is formed on the dielectric layer 20 and Full first perforation 0 Where the deposition of subsequent film layers is to be made smoother j The conductive layer 2 formed here can be paged 页 ο page 530387 V. Description of the invention (7) Use a method such as chemical mechanical polishing to perform a comprehensive flat Into. Please refer to FIG. 4, using lithography and etching techniques to remove a part of the conductive layer 22 to define the gate structure of the transistor and the second electrode (also called the upper electrode) of the capacitor at the same time. Please refer to FIG. 5, and then sequentially fabricate the N-type lightly doped drain (LDD), P-type lightly doped drain (LDD), and the spacer 24 of the transistor. The capacitor also has a spacer 2 around it. 4 as insulation protection. Next, an ion implantation method is used to form a drain and a source. Referring to FIG. 6, an insulating layer 26 is formed on the above structure. Then using lithography and etching technology, a second perforation is formed in the insulating layer 26, and then a conductive material 28 is formed to backfill the second perforation. The conductive material 2 8. In this way, the capacitors and transistors can be connected to each other or in electrical contact with other components and structures. The deposition method of the impurity-doped silica glass layer 16 includes a chemical vapor deposition method (Chemical Vapor Deposition; CVD). As for the removal of the impurity-doped silica glass layer 1 above the semiconductor substrate 10 The 6 method includes the back # 刻 法. In addition, the temperature at which the above-mentioned impurity-doped silica glass layer 16 is heat-treated is about 90 ° C to 100 ° C, and the temperature of the impurity-doped silica glass layer 16 is removed.

Page 11 530387 V. Description of the invention (8) / The method includes wet money engraving. The dielectric layer 20 is selected from the group consisting of Ta 20 5, Ti〇2, PZT, BST, nitride / oxide (N / 0), oxide / nitride / oxide (0 / N / 0) One of the clusters of the composite film, the conductive layer 22 includes doped polysilicon, and the insulating layer 26 includes an oxide layer. In the manufacturing method of the dynamic random access memory proposed by the present invention, the capacitor manufacturing process only requires a polycrystalline silicon layer, and the gate dielectric layer of the transistor and the capacitor dielectric layer are manufactured simultaneously, and the capacitor and the transistor Processes can be integrated. Therefore, compared with the traditional manufacturing method of dynamic random access memory, the manufacturing cost is relatively cheap, and the cell size is greatly reduced. The present invention has been described above with reference to the preferred embodiments, and is not intended to limit the scope of patent application for the present invention. Those skilled in the art can make some modifications and modifications without departing from the spirit of the present invention. Equivalent changes or modifications made under the spirit disclosed by the invention should be regarded as the protection scope of the invention. The scope of patent protection of the present invention depends on the scope of patent application and its equivalent fields.

Page 530 387 Brief Description of Drawings Using the following descriptions in conjunction with the following drawings will give a clearer understanding of the content and advantages of the present invention, of which: Figure 1 is a cross-sectional view of a semiconductor wafer, showing one of the aspects of the present invention. In the embodiment, a step of forming a first perforation on a semiconductor substrate, and then depositing a doped silica glass layer on the semiconductor substrate and filling the first perforation are provided. FIG. 2 is a cross-sectional view of a semiconductor wafer, showing one of the methods according to the present invention. In the embodiment, a step of performing a heat treatment on the impurity-doped silica glass layer to drive the impurities in the impurity-doped silica glass layer into the semiconductor substrate; FIG. 3 is a cross-sectional view of a semiconductor wafer, showing an implementation according to one of the present invention; For example, the steps of removing the silica glass layer doped with impurities, and then sequentially forming a dielectric layer and a conductive layer; FIG. 4 is a cross-sectional view of a semiconductor wafer, showing the removal of a part of the conductive layer according to an embodiment of the present invention to simultaneously define The gate structure of the transistor and the step of the second electrode of the capacitor; Figure 5 is a cross-sectional view of a semiconductor wafer, showing An embodiment is a step of fabricating a lightly doped drain (LDD) and a spacer of a transistor on a semiconductor substrate; and FIG. 6 is a cross-sectional view of a semiconductor wafer, showing that an insulation is first formed according to an embodiment of the present invention. Layer, and then forming a second perforation in the insulating layer, and filling the second perforation with a conductive material. Drawing number part:

Page 13 530387

Page 14

Claims (1)

530387 6. Scope of patent application 1. A method for manufacturing a dynamic random access memory, the method includes at least the following steps: forming a first perforation in a semiconductor substrate; depositing an arsenic-silica glass layer or a phosphosilicate glass layer on the semiconductor Over the substrate and filling the first perforation; removing a part of the arsenic-silica glass layer or the phosphosilicate glass layer located on the semiconductor substrate; subjecting the arsenic-silica glass layer or the phosphosilicate glass layer to heat treatment, In order to drive arsenic or phosphorus ions in the arsenic silica glass layer or the phosphosilicate glass layer into the semiconductor substrate, a conductive doped region is formed, wherein the conductive doped region can be used as a first electrode of a capacitor. Removing the arsenic-silica glass layer or the phosphosilicate glass layer; forming a dielectric layer along the surface of the semiconductor substrate and the conductive dopant region, wherein the dielectric layer can be used as a dielectric film of a transistor gate And the dielectric film of the capacitor; forming a conductive layer on the dielectric layer and filling the first perforation; removing part of the conductive layer to define the gate structure of the transistor at the same time . Brother and two electrodes of the capacitor, the transistor is formed of a lightly doped drain; forming a spacer on sidewalls of the transistor and the capacitor; and forming the transistor drain and the source. 2. The method of claim 1 in the scope of patent application, which includes the following steps after forming the above-mentioned drain and source: Page 15 530387 6. Scope of patent application Forming an insulating layer on the semiconductor substrate; forming a second perforation in the insulating layer; and forming a conductive material in the second perforation. 3. The method according to item 1 of the scope of patent application, wherein the method for depositing the above-mentioned vermiculite glass layer or the vermiculite glass layer includes a chemical vapor deposition method (C hem 1 ca 1 Vapor Deposition; CVD) ° 4. The method of claim 1, wherein the method for removing a part of the arsenic-silica glass layer or the phosphosilicate glass layer located on the semiconductor substrate includes an I-etching method. 5. The method according to item 1 of the scope of patent application, wherein the temperature of the above heat treatment is about 900 to 110 degrees Celsius. 6. The method according to item 1 of the scope of patent application, wherein the method for removing the arsenic-silica glass layer or the phenol-filled glass layer includes a wet money engraving method. 7. The method according to item 1 of the patent application range, wherein the above-mentioned dielectric layer is one selected from the group consisting of a composite film including Ta 20 5, Ti02, PZT, BST, N / 0, 0 / N / 0 . 8. The method according to item 1 of the patent application range, wherein the above-mentioned conductive layer comprises polycrystalline stone. Page 16 530387 6. Scope of patent application 9. The method according to item 2 of the patent scope, wherein the above-mentioned insulating layer includes an oxide layer. 10. A method for manufacturing a dynamic random access memory, the method includes at least the following steps: forming a first perforation in a semiconductor substrate; depositing an arsenic-silica glass layer or a phosphosilicate glass layer on the semiconductor substrate, And filling the first perforation; using an etch-back technique to remove a part of the arsenic-silica glass layer or the phosphosilicate glass layer on the semiconductor substrate; applying heat treatment to the arsenic-silica glass layer or the phosphosilicate glass layer So that arsenic or phosphorus ions in the arsenic-silica glass layer or the phosphosilicate glass layer are driven into the semiconductor substrate to form a conductive doping region, wherein the conductive doping region can be used as the first capacitor. An electrode; removing the arsenic-silica glass layer or the phosphosilicate glass layer by a wet etching method; forming a dielectric layer along the surface of the semiconductor substrate and the conductive doped region, wherein the dielectric layer can be used as a transistor A dielectric film of the gate and a dielectric film of the capacitor; forming a polycrystalline silicon layer on the dielectric layer and filling the first perforation; removing a part of the polycrystalline silicon layer to define the transistor at the same time Di gate structure and the second electrode of the capacitor, the transistor is formed of a lightly doped drain; forming a spacer on sidewalls of the transistor and the capacitor; Page 17 530387 6. The scope of the patent application forms the drain and source of the transistor; forming an insulating layer on the semiconductor substrate; forming a second perforation in the insulating layer; and forming a conductive material in the second perforation . 1 1. The method according to item 10 of the scope of patent application, wherein the method for depositing the arsenic-silica glass layer or phosphosilicate glass layer includes a chemical vapor deposition method (C hem 1 ca 1 Vapor Deposition; CVD) ° 1 2. The method of applying for item 10 of the patent scope, wherein the temperature of the above heat treatment is about 900 to 110 degrees Celsius. 1 3. A method for manufacturing a capacitor in a dynamic random access memory, the method includes at least the following steps: forming a first perforation in a semiconductor substrate; depositing an arsenic-silica glass layer or a phosphosilicate glass layer on the semiconductor substrate And filling the first perforation; removing a part of the arsenic-silica glass layer or the phosphosilicate glass layer over the semiconductor substrate; applying heat treatment to the arsenic-silica glass layer or the phosphosilicate glass layer to Arsenic or phosphorus ions in the arsenic-silica glass layer or the phosphosilicate glass layer are driven into the semiconductor substrate to form a conductive doped region, wherein the conductive doped region can be used as the first electrode of the capacitor. Removing the arsenic-silica glass layer or the silica-filled glass layer; Page 18, 530387 6. The scope of the patent application is to form a dielectric layer on the surface of the semiconductor substrate and the conductive doping region, wherein the dielectric layer can be used as a transistor gate in the dynamic random access memory. A dielectric film of the capacitor and a dielectric film of the capacitor; forming a conductive layer on the dielectric layer and filling the first perforation; and removing a portion of the conductive layer to simultaneously define the dynamic random access memory The gate structure of the transistor and the second electrode of the capacitor. 14. The method according to item 13 of the scope of patent application, wherein the method for depositing the arsenic-silica glass layer or shattered glass layer includes chemical vapor deposition (C hemica 1 Vapor Deposition; CVD) ° 1 5. The method according to item 13 of the scope, wherein the method for removing a part of the arsenic-silica glass layer or the phosphosilicate glass layer located on the semiconductor substrate includes a cash back method. 16. The method according to item 13 of the scope of patent application, wherein the temperature of the above heat treatment is about 900 to 110 degrees Celsius. 17. The method according to item 13 of the scope of patent application, wherein the method for removing the arsenic-silica glass layer or the silica-filled glass layer includes a wet etching method. 18. The method according to item 13 of the scope of patent application, wherein said conductive layer comprises polycrystalline silicon. Page 19, 530387 VI. Scope of patent application 1 9. A method for manufacturing a dynamic random access memory, the method includes at least the following steps: forming a first perforation in a semiconductor substrate; depositing a layer of silica glass doped with impurities on The semiconductor substrate is filled with the first perforation; the impurity-doped silica glass layer located on the semiconductor substrate is removed; and the impurity-doped silica glass layer is heat-treated to make the doped Impurities in the impurity-impregnated silica glass layer are driven into the semiconductor substrate to form a conductive doped region, wherein the conductive doped region can be used as the first electrode of the capacitor; removing the impurity-doped silica glass layer ; Forming a dielectric layer along the surface of the semiconductor substrate and the conductive doping region, wherein the dielectric layer can be used as a dielectric film of a transistor gate and a capacitor dielectric film; forming a conductive layer on the Over the dielectric layer and filling the first perforation; removing part of the conductive layer to define the gate structure of the transistor and the second electrode of the capacitor at the same time; The transistor has a lightly doped drain; forming a spacer on sidewalls of the transistor and the capacitor; and forming the transistor drain and the source. 20. The method according to item 19 of the scope of patent application, wherein after forming the above-mentioned drain and source, the method further includes the following steps: Page 20 530387 VI. Scope of patent application Forming an insulating layer on the semiconductor substrate; forming a second perforation in the insulating layer; and forming a conductive material in the second perforation. 2 1. The method according to item 19 of the scope of patent application, wherein the impurity-doped silica glass layer comprises an arsenic silica glass layer or a silica-filled glass layer. 2 2. The method according to item 19 of the scope of patent application, wherein the method for depositing the above-mentioned impurity-doped glass layer includes chemical vapor deposition (C hemica 1 Vapor Deposition; CVD) ° 2 3. The method according to item 19, wherein the temperature of the heat treatment is about 900 ° C to 110 ° C. 24. The method according to item 19 of the patent application range, wherein the method for removing the impurity-doped silica glass layer includes a wet etching method. 25. The method according to item 19 of the scope of patent application, wherein said conductive layer comprises polycrystalline silicon. 2 6. A method for manufacturing a capacitor in a dynamic random access memory, the method includes at least the following steps: forming a first perforation in a semiconductor substrate; depositing a doped silica glass layer on the semiconductor substrate And fill Page 21 530387 6. The scope of the patent application is full of the first perforation; removing the part of the silicon glass layer doped with impurities on the semiconductor substrate; applying heat treatment to the silicon glass layer doped with impurities to make the Impurities in the impurity-doped silica glass layer are driven into the semiconductor substrate to form a conductive doped region, wherein the conductive doped region can be used as the first electrode of the capacitor; removing the impurity-doped silica glass A dielectric layer is formed along the surface of the semiconductor substrate and the conductive doped region, wherein the dielectric layer can be used as a dielectric film of a transistor gate and a capacitor dielectric film; and a conductive layer is formed on Over the dielectric layer and filling the first perforation; and removing part of the conductive layer to simultaneously define the gate structure of the transistor in the dynamic random access memory and the second electrode of the capacitor . 27. The method according to item 26 of the scope of patent application, wherein the impurity-doped silica glass layer comprises an arsenic silica glass layer or a phosphosilicate glass layer. 28. The method according to item 26 of the scope of patent application, wherein the method for depositing the above-mentioned impurity-doped glass layer includes chemical vapor deposition (C hemica 1 Vapor Deposition; CVD) ° 2 9. The method according to item 26, wherein the temperature of the heat treatment is about 900 to 110 degrees Celsius. Page 22 530387 VI. Application scope of patent 30. The method according to item 26 of the scope of patent application, wherein the aforementioned conductive layer contains polycrystalline silicon. Page 23