TW530382B - Method of forming a metal interconnect - Google Patents

Abstract

A semiconductor substrate has a first dielectric layer positioned on the semiconductor substrate. At least one recess is formed in the first dielectric layer. Then a glue layer, a metal layer and a material layer, sealing an opening of the recess, are sequentially formed on the surface of the recess. Thereafter, a photo-etching-process is performed to form at least one metal interconnect in the glue layer, the metal layer and the material layer. The material layer that seals the opening of the recess is used to prevent portions of a photoresist layer from remaining in the recess during the photo-etching-process.

Description

530382 V. Description of the Invention (1) Field of the Invention The present invention provides a method for manufacturing a metal interconnect, especially a metal interconnect that can prevent photoresist from remaining in the metal interconnect. 3, line production method. Background: In the advanced very large seaie integrated circufts (VLSI) industry, the manufacturing process has progressed to a number of hundreds of thousands, or even a few, can be squeezed into the silicon surface with a volume of 1 to 2 cm%. More than a million metal oxide semiconductor (MOS semiconductor) transistors and other components. And metallization (metallization) and metal interconnects (metal interconnects) I want to contact these components 'for example, the three poles on the MOS device' and the metal layer and metal layer, contact (contact) In addition, the wires that have been in contact with the respective MOS components must be electrically connected with the wires according to the circuit design of the circuit to form a complete circuit, thereby forming a complete electronic device. In the current VLSI process technology, two types of conductor materials, such as tungsten (tungsten) and aluminum-silicon-copper alloy (Ab-Si-Cu alloy), are used as conductor materials for contact and interconnection. The former is made using low pressure chemical vapor deposition (LPCVD)

Page 5 530382 V. Description of the invention (2) Manufacturing process has the advantages of being less sensitive to the high temperature process and good step coverage ability. It is very suitable for metal interconnects that must withstand high temperatures, but The disadvantage is higher cost; the latter is manufactured by DC sputter ing, which has the advantage of good conductivity, but relatively speaking, the melting temper ature is lower (the melting point of aluminum is about For 5 7 7. C). In addition, other common conductor materials include titanium (Ti), titanium silicide (Tisi2), tungsten silicide (WSix), titanium nitride (TiN), and tungsten-titanium alloy (TiW al loy). Among them, titanium, titanium silicide, and tungsten silicide are mostly used to reduce the contact resistance (contact resistance) of the metal in contact with the MOS poles or the resistance of the wire, while titanium nitride and tungsten-titanium alloys are used. It is used as a barrier layer to prevent the metal and silicon from forming an interface stone metal, or as a drilling layer to improve the adhesion between metal and other materials (adhesion ab i1i ty). layer). Please refer to FIGS. 1 to 5, which are schematic diagrams of a conventional method for fabricating a metal interconnect 24 or via plug. As shown in FIG. 1, the semiconductor wafer 10 includes a substrate 12 and a first dielectric layer 14 covering the surface of the substrate 12. First, a photoresist layer 15 is coated on the surface of the first dielectric layer 14 and a phfotolithography process is performed to define the position and size of a recess in the photoresist layer 15. Then, a dry etch process is performed, and the first dielectric layer 14 is removed vertically down to the surface of the substrate 12 along the defined pattern to form a via hole having two vertical sidewalls (via ho 1 e). ) 1 6. It is worth noting that in the general case

530382

Below, the surface of the substrate 12 below the via 16 includes a metal layer (not shown). The same manufacturing process can also be applied to contact holes. In the case of a contact hole, the surface of the substrate 12 below the contact hole includes a source (not shown) and a drain (not shown) of an MOS transistor. Display, or gate (not shown). ≫ As shown in Figure 2, then formed in and above the via 16-the first: titanium nitride layer 18, and the first-titanium nitride layer 18 and Between the bottom and the bottom, there is usually a layer of titanium silicide (τ 丨 si 2). The first titanium nitride layer 18 is used as an adhesive layer (g 1 ue 1 ayer). It is formed by using the etiquette reaction (11 丨 丨 1 ^ (131: 丨 〇11) process, or by reactive sputtering. The former is formed by a certain thickness of titanium, ^ by magnetic control DC In the sputtering method, it is deposited on the surface of the wafer, and then the wafer is placed in an environment containing NH and NH, and this layer of titanium is nitrided to nitrogen by high temperature = titanium. The latter uses a metal target composed of titanium. The reaction gas, which is a mixture of argon () and nitrogen, is used to ionize titanium to produce titanium, and it reacts with the dissociation reaction in the electric cargo. eaction) formed nitrogen atoms 7 to form titanium nitride and deposited on the wafer surface. Then a chemical vapor phase, chemical vapor deposi ti on (CVD) process is performed on the first nitride layer 18 Tungsten layer (W 1 ayer) with good step cover age ability is deposited 22 ° as shown in Figure 3, followed by a first photolithography process on top of the tungsten layer 22 Form a picture

530382 V. Description of the invention (4) The photoresist layer 23 is used to define the pattern of the metal interconnects 24. Then, a dry rest (d r y e t c h) process is performed to remove the tungsten layer 22 and the titanium nitride layer 18 which are not covered by the photoresist layer 23 and form a metal interconnect 24. Because the step coverage ability of the tungsten layer 22 is quite good, when the tungsten layer 22 is formed, if the thickness of the tungsten layer 22 is insufficient, the opening of the via 16 1 will not be sealed, so that it will be formed. When the photoresist layer 23 is formed, some photoresist may enter the via hole 16. As shown in FIG. 4, after the photoresist layer 23 is removed, some photoresist will remain in the via 16 and cannot be removed cleanly. As shown in FIG. 5, a second dielectric layer 26 is deposited. Since some photoresist composed of polymer materials remains in the via hole 16, during the deposition process of the second dielectric layer 26, these remaining polymer materials are liable to produce physical and Chemical changes, so that some abnormal phenomena such as particles, defects, and bubbles are generated. In order to solve the above-mentioned problem of photoresist residue, improved technology has been proposed. Please refer to FIG. 6 to FIG. 11. FIGS. 6 to 11 are schematic diagrams of an improved method for making a metal interconnect 4 6. As shown in FIG. 6, the semiconductor wafer 30 includes a substrate; | 32, and the first dielectric layer 34 covers the surface of the substrate 32. First, a photoresist layer 35 is coated on the surface of the 'dielectric layer 34', and a photolithography process is performed to define the position and size of a groove (r c c s s) in the photoresist layer 35. Next, a dry #etch process is performed to remove the first dielectric layer vertically downward along the defined pattern.

530382 V. Description of the invention (6) As shown in FIG. 8, following the use of the first titanium nitride layer 38 as a stop layer, an etch back process or a chemical mechanical polishing process is performed. mechanical polish (CMP) process so that the tungsten layer 42 in the via 36 is approximately aligned with the first titanium nitride layer 38. Next, as shown in FIG. 9, a chemical vapor deposition (CVD) process is performed to deposit another tungsten layer 4 4 on the first titanium nitride layer 38 and the tungsten layer 4 2 for use as For metal interconnects. As shown in Fig. 10, the government is conducting a photolithography process to form a photoresist layer 45 on the tungsten layer 44 to define the metal ... . Then, a dry etch process is performed to remove the transfer layer 44 and the first nitride layer 38 covered by the μ-resistance layer 45, and the connection 46 is good. Because the coverage of the step 42 of the Yan layer 42 is quite good (V0_in, there will still be a void in the mesial hole 36. The surname e / in = grinding, and then deposit a layer of tungsten 42 with LLi: 5: r without photoresistive metal interconnects 46, including household catties without "I except ^ ί will not occur any more ★ The state of the resistance remaining in the dielectric hole 36 bis dielectric reed 48 Xi Yin. As shown in Figure 11, the last step is to proceed to the second two = integration process. Because there is no residual photoresist in the dielectric hole 36 &Quot; During the deposition process of the electrical layer 36, some such as

530382

Defects (bubMe), etc. V. Description of the invention (7) Particles, normal phenomena. However, this will lead to some new problems. For example, the tungsten material is more expensive than amber, and the cost will be significantly increased. When using the etch back or chemical mechanical polishing process to make surplus, it is easy to produce residues and residues. Defects make it difficult to control the yield (yie 1 d). Therefore, another improved technology has been proposed. Please refer to FIG. 12 and FIG. 15, and FIGS. 12 to 15 are schematic diagrams of another improved method for conventionally making a metal interconnect 78. As shown in FIG. 12, the semiconductor wafer 60 includes a substrate 62, and a first dielectric layer 64 covers the surface of the substrate 62. First, a photoresist layer 65 is coated on the surface of the first dielectric layer 64, and a photolithography process is performed to define the position and size of a recess in the photoresist layer 65. Next, a dry etch process is performed, and the first dielectric layer 64 is removed vertically down to the surface of the substrate 62 along the defined pattern to form a via hole 66 having two vertical sidewalls. . It is worth noting that, in other cases, the surface of the substrate 62 under the via hole 66 may also include a metal layer (not shown). The same manufacturing process can also be applied to a contact hole (contact ho 1 e). In the case of a contact hole, the surface of the substrate 6 2 below the contact hole includes a source (not shown), Pole (not shown) or gate (not shown).

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530382 V. Description of the invention (8) As shown in FIG. 12, 'The first titanium nitride is formed in the interlayer hole 66 and on the first dielectric layer 64 to be used as a glue layer. Layer 68, and then a chemical vapor deposition (CVD) process is performed to directly deposit a tungsten layer (tungsten layer) with good step coverage on the first titanium nitride layer 68 , W layer) 72. The thickness of the tungsten layer 72 in this improved technology is thicker than that of other described technologies, so that it can be used for both the interposer plug and the metal interconnection, without the need for any tungsten. Return to name or chemical mechanical polishing process, and then deposit another tungsten layer.

As shown in FIG. 14, a first photolithography process is performed to form a pattern on the tungsten layer 72.

A patterned photoresist layer 73 is used to define the pattern of the metal interconnects 7 4. Then, a dry process (d r y e t c ^) is performed to remove the tungsten layer 72 and the titanium nitride layer 68 that are not covered by the photoresist layer 73 and form a metal interconnect 74. Since the tungsten layer 72 has a fairly good step coverage capability, after the formation of the Yan layer 72, 'the via hole 66 will have a void (V0id) in it, but because the thickness of the tungsten layer 72 is very thick, the via hole is The tungsten ^ 72 at the top of 66 will seal the opening of the via hole 66 and serve as a barrier for the photoresist layer 73 to enter the void in the second via hole 66. Therefore, after the photoresist: layer 73 is removed, no photoresist will remain in the via hole 66, and it cannot be removed completely. As shown in FIG. 15, a second dielectric layer 76 is then deposited.

Page 12 530382 V. Description of the invention (9) Cheng Jie (Like electrical layer system = workers and students "... in the second (particle), defect (defect); some like particles, while reducing the number of process steps, avoid: Tolerance] =) :: Anomalies (1) and defective ... process, improve yield 2 However, this also still results in a thicker crane material, more cost waves f = 7 questions. For example, the required deposition (... p w㈣ is too high to open; ^ and the step height of the first crane layer 72 tends to have a flatter sinker, and affects the subsequent two-pass V: .76, so how can we develop A metal that solves the problem of photoresist residues and does not require the Shanghai-Yunnan line process. Not only can it effectively increase the cost and it is difficult to be planarized. ^, Too thick tungsten layer, with high yield, has become a very important issue. Question 'At the same time, simplify the process and provide an overview of the invention. Therefore, the main purpose of the present invention is to provide a (metal interconnect) and its producer, photoresist residue, and photoresist residue. In the preferred embodiment, the present invention first contains a first A semiconductor substrate of a dielectric layer, and a surface package is formed in the first dielectric layer.

530382 V. Description of the Invention (ίο)

There is at least one recess, and then the groove surface is sealed with a titanium nitride layer, a tungsten metal layer, and a second titanium nitride layer and a second nitride layer on the surface of the groove. η). Then, an etching process (PEP) is performed to form at least one metal interconnect interconnect in the first titanium nitride layer and the first and second gasification layers. Among them, the J layer that seals the groove opening is used to prevent the photoresist residue in the yellow light and etching process. Because the present invention has a poor covering ability to form a first titanium nitride layer and repeatedly to form a step. The second titanium nitride layer is a hole in the layer. Therefore, in the subsequent yellowing of the metal interconnect, there will be no abnormality in which the photoresist remains in the via hole. The invention does not need to deposit a too thick tungsten layer, so it will not cause the problem of cost increase and flattening. The invention also does not need to add a tungsten process, which can avoid the generation of residues and defects, so that the yield rate is additionally covered by the second titanium nitride layer on the transfer layer, which is not only an anti-reflective layer, but also enables the production of metal interconnects. The yellow light process can also be used as an adhesion layer to improve the tungsten metal and second dielectric capabilities. '' Detailed description of the invention is to form a first order, and use this to carry out a yellow light I metal layer to wire (metal ξ titanium dinitride in the groove tungsten layer, and then used to seal the dielectric process, like. Because of this It is easy to control and difficult to etch back. It can be used for easy process and adhesion of electrical layer

In the present invention

530382 V. Description of the invention (12) and deposited on the wafer surface. A chemical vapor deposition (CVD) process is then performed to deposit a tungsten layer (W layer) with good step coverage on the first titanium nitride layer i08. 112) As shown in FIG. 18 ', a reactive titanium sputter process is then used to form a second titanium nitride layer 114 on the tungsten layer 112. As the reactive sputtering process is a physical vapor deposition (PVD) process, it is characterized by the inability to provide a good deposition film with step coverage (Cs tep coverage), so that most of the sputtered metal cannot be completely filled. (Fi 1 1) to the interstitial hole 丨 〇6, so the opening will be closed due to the overhang (〇verhang) 1 1 6, leaving only a closed hole (void) in the interstitial hole 1 〇6 中. Among them, the second titanium nitride layer 1 1 4 can also be replaced by a titanium layer (titanium layer) or a tungsten tungsten layer (TiW layer) formed by a physical vapor deposition process, because it also has a step coverage capability. Good and high temperature resistance. As shown in FIG. 19, a first photolithography process is performed to form a patterned photoresist layer (117) on the second titanium nitride layer 1 1 4. To define the pattern of the metal interconnects 1 18. Then a dry etch process is performed to remove the second titanium nitride layer 1 1 4 and the tungsten layer 1 1 which are not covered by the photoresist layer 1 17 & and The first titanium nitride layer 1 0 8 forms a metal interconnect 1 1 8. Because the opening of the via 106 has been covered by the step with poor step coverage

Page 16 530382 V. Description of the invention (13) " --- Sealed by the titanium layer 114 ', so that when the photoresist layer ιΐ7 is formed, no photoresist will enter the via 106. Finally, the photoresist layer 117 is removed. = As shown in FIG. 20, a deposition king of a second dielectric layer 122 is then performed. Because the photoresist does not remain in the interlayer hole, there will be no abnormalities such as particles, defects, and bubbles during the deposition process of the second dielectric layer 122. phenomenon. Because the present invention first forms a first titanium nitride layer and a tungsten layer, and then forms a second titanium nitride layer with poor step coverage, which is used to seal the opening of the interlayer hole. Therefore, in the subsequent yellow light manufacturing process of metal interconnections, the abnormal phenomenon of photoresist remaining in the via hole will not occur. Because the present invention does not need to deposit a tungsten layer that is too thick, it does not cause the problem of increased cost and difficulty in being planarized, and the present invention does not need to add a tungsten etchback process, which can avoid the generation of residues and defects, and thus make Yield is easy to control. In addition, the second titanium nitride layer overlying the tungsten layer can not only be used as an anti-reflection layer (ARC layer), making the yellow light process for making metal interconnects easier, and can be used As a glue layer, the adhesion between tungsten metal and the second dielectric layer is improved. Compared with the conventional method for making metal interconnects, the metal interconnects of the present invention first form a first nitride. A titanium layer and a tungsten layer, and then forming a first order

Page 17 530382 V. Description of the invention (14) The second titanium nitride layer with poor ladder coverage is used to seal the opening of the via hole. Therefore, during the yellow light process of metal interconnections, there will be no photoresist layer remaining in the interlayer holes to effectively avoid the occurrence of abnormal phenomena such as particles, defects and bubbles. Therefore, the present invention can not only solve the problem of photoresist residue, but also does not need to deposit a too thick tungsten layer, in order to effectively simplify the process, solve the problem of increased cost and difficult to be planarized, and thereby achieve the goal of improving yield.

The above description is only a preferred embodiment of the present invention, and all equivalent changes and modifications made in accordance with the scope of the patent application for the present invention shall fall within the scope of the invention patent.

Page 18 530382 Simple illustration of the diagrams Simple illustration of the diagrams Figures 1 to 5 are schematic diagrams of the conventional method for making a metal interconnect or interposer plug. Figures 6 to 11 are schematic diagrams of conventional methods for improving a metal interconnect. Figures 12 to 15 are schematic diagrams of another improved method for conventionally making a metal interconnect.

16 to 20 are schematic diagrams of a method for manufacturing a metal interconnect in the present invention. ., Symbol description

10 semiconductor wafer 12 substrate 14 first dielectric layer 15 photoresist layer 16 dielectric hole 18 first titanium nitride layer 22 tungsten layer 23 first photoresist layer 24 metal interconnect 26 second dielectric layer 30 semiconductor wafer 32 Substrate 34 First dielectric layer 3 5 ~ Photoresist layer 36 Dielectric hole 42 Tungsten layer 44 Tungsten layer 45 First photoresist layer 46 Metal interconnect 48 Second dielectric layer 60 Semiconductor wafer 6 2 Substrate

Page 19 530382 Simple illustration of the diagram 64 First dielectric layer 66 Dielectric hole 72 Tungsten layer 7 4 Metal interconnect 1 0 0 Semiconductor wafer 104 First dielectric layer 1 0 6 Dielectric hole 1 1 2 Tungsten layer I 1 6 Suspension II 8 Metal interconnects 65 Photoresist layer 68 First titanium nitride layer 73 First photoresist layer 76 Second dielectric layer 102 Substrate 1 0 5 Photoresist layer layer Titanium Ti layering resistance Electric Nitrogen and Nitrogen Photoelectricity

Page 20

Claims (1)

530382 VI. The scope of patent application is regarded as an anti-reflection layer (ARC Layer) ° 9 · As in the method of the scope of patent application No. 1, wherein the titanium nitride layer is used as a glue layer layer). 10. A method for manufacturing a metal interconnect, the method includes the following steps: providing a semiconductor substrate, and the semiconductor substrate includes a conductive region, and a first dielectric layer ( dielectr ic layer) covers the semiconductor substrate and the conductive area; and performs a photo-etching-process (PEP) on the first dielectric layer to form the first dielectric layer. At least one recess (recess) up to the surface of the conductive region; a first titanium nitride (TiN) layer and a tungsten (tungsten, W) layer are sequentially formed on the first dielectric layer and the surface of the recess; ) A metal layer, and the tungsten metal layer and the first titanium nitride layer do not completely fill the groove; a second titanium nitride (TiN) layer is formed on the surface of the hafnium metal layer, and − The second titanium nitride layer seals (sea 1) the opening of the groove; forming a patterned photoresist layer on the surface of the second titanium nitride layer to define at least one metal interconnect Line pattern; etchin g process) 530382 6. Scope of patent application Further preventing the photoresist from remaining in the groove. 16 · The method according to item 10 of the scope of patent application, wherein the second titanium nitride layer is used as an anti-reflection layer (ARC layer). The method of item 0, wherein the second titanium nitride layer is used as a glue layer. 1 8 · —A method of manufacturing a metal interconnect that prevents photoresist from remaining in the metal 1 interconnect, the manufacturing method includes the following steps: providing a semiconductor substrate and the semiconductor substrate It includes a conductive region, and a first dielectric layer covering the semiconductor substrate and the conductive region. A yellow light and etching process (PEP) is performed on the first dielectric layer. Forming at least one recess in a dielectric layer up to the surface of the conductive region; A glue layer and an iron (W) metal layer are sequentially formed on the first dielectric layer and the groove surface, and the tungsten metal layer and the glue layer do not completely fill the groove; A titanium nitride (T i N) layer is formed on the surface of the crane metal layer, and the & titanium nitride layer seals (sea 1) the opening of the groove; Page 25 530382 6. The scope of the application for a patent forms a patterned photoresist layer on the surface of the titanium nitride layer, which is used to define the pattern of at least one metal interconnect; an etching process is performed to remove The titanium nitride layer, the tungsten metal layer, and the adhesive layer covered by the photoresist layer to form the metal interconnect; removing the photoresist layer; and connecting the metal interconnect and the first dielectric layer A second dielectric layer is formed on the surface; wherein the vaporized titanium layer is formed by a stepped coating (stepc 〇verage) which is used to seal (sea 1) the opening of the groove. (Open), thereby preventing the photoresist from remaining in the groove. 19 · The manufacturing method according to item 18 of the scope of patent application, wherein the first dielectric layer and the second dielectric layer are both made of si 1 ic on dioxide (Si 0 2). Make up. 20 · The manufacturing method according to item 18 of the scope of patent application, wherein the adhesive layer is a titanium silicon compound (T i S i D layer and a titanium nitride formed by a reactive sputter process) It is formed by stacking layers under and above. '2 1 · The method according to item 18 of the scope of patent application, wherein the tungsten layer is formed by a chemical vapor deposition (CVD) process. Page 26 530382 VI. Application for Patent Scope 2 2. The method of claim 18 for patent application, wherein the titanium nitride layer is used as an anti-reflection layer (ARC layer) 〇 2 3 The method of claim 18, wherein the titanium nitride layer is used as a glue layer. Page 27