JPH07283219A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To simply manufacture a semiconductor device, provided with a low resistance and highly reliable wiring, at low cost. CONSTITUTION:A wiring layer 2 is formed on a single crystal silicon substrate 1, and an interlayer insulating film 3 is formed thereon. A contact hole 4 is opened on the interlayer insulating film 3. A wiring layer 5 is formed on the interlayer insulating film 3. The wiring layer 5 is formed by successively laminating a titanium film 6, a titanium nitride film 7, a tantalum film 8 and a copper film 9, and the wiring layer 5 is brought into contact with the substrate 1 and the wiring layer 2 through the contact hole 4. The titanium film 6 and the tantalum film 8 are formed by a magnetron sputtering method, and titanium nitride film 7 is formed by a magnetron sputtering method in which a reactive sputtering method is combindly used. The copper thin film 9 is formed by a copper sulfate plating method in which a Ta film B is used as a cathode.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, a method for manufacturing the semiconductor device, and a device for manufacturing the semiconductor device, and more particularly to a low resistance and highly reliable wiring using copper, gold and silver as wiring materials. The present invention relates to a semiconductor device, a method for manufacturing the semiconductor device, and a device for manufacturing the semiconductor device.

[0002]

2. Description of the Related Art With the high integration of semiconductor integrated circuits, increase in wiring resistance due to increase in wiring length and increase in inter-wiring capacitance due to reduction in space between wirings have become remarkable. As a result, in the conventional wiring using aluminum alloy as the wiring material, the signal delay becomes large, and it is difficult to improve the operation speed of the semiconductor integrated circuit. Further, when an aluminum alloy is used as the wiring material, it is difficult to improve the reliability of the semiconductor integrated circuit because the electromigration (EM) resistance and the stress migration (SM) resistance are insufficient. Therefore, it has been considered to use copper, gold, silver, etc., as a wiring material, which has a resistivity lower than that of an aluminum alloy and a melting point higher than that of the aluminum alloy, and thus has significantly better EM resistance and SM resistance than the aluminum alloy. Among them, copper has a resistivity of 1.7 μΩ · cm.
In addition to its low resistivity (aluminum has a resistivity of 2.8 μΩ · cm) and is cheaper than gold or silver, it is being actively researched as a next-generation wiring material to replace aluminum alloys.

A conventional wiring manufacturing method using such copper as a wiring material will be described with reference to FIGS. First, as shown in FIG. 15, a wiring layer 102 such as a gate electrode of a MOS transistor is formed on a single crystal silicon substrate (wafer) 101, and an interlayer insulating film 103 made of a silicon oxide film is formed thereon. Then, a contact hole 104 for making contact with the substrate 101 and the wiring layer 102 is opened in the interlayer insulating film 103.

Then, as shown in FIG. 16, titanium (Ti) is formed on the entire surface of the wafer including the inside of the contact hole 104.
A film 105 and a titanium nitride (TiN) film 106 are sequentially formed.

Then, as shown in FIG. 17, a copper thin film 107 is formed on the TiN film 106 on the entire surface of the wafer including the inside of the contact hole 104. As a method of forming the copper thin film 107, (1993 Symposium on VLSI Technology; pp. 12
3-124) 、 (1993 Symposiumon VLSI Technology; pp.125
-126) 、 (1991 Symposium on VLSI Technology; pp.37-
38) and other detailed MOCVD (Metal-Organic)
CVD method, (J. Electrochem. Soc. 139,9
22 (1992)), (Extended Abstracts of the 1993 Inter
national Conference on Solid State Devices and Mat
erials; pp.549-551) and other methods using the sputtering method, (PLPai: IEEE VLSI Multilevel Int.
erconnection Conference., 1989, pp.258-264) and the like, and a method using an autocatalytic plating (electroless plating) method.

By the way, TiN film 106 and Ti film 1
05 functions as a barrier layer. The TiN film 106 is formed to suppress the reaction between the copper thin film 107 and the substrate 101 and prevent an increase in junction leak current due to mutual diffusion. Further, the reason why the Ti film 105 is formed is that the contact resistance becomes high when only the TiN film 106 is formed.

Then, as shown in FIG. 18, a copper thin film 10 is formed.
After applying a resist on the substrate 7, a resist pattern 108 is formed through an exposure process and a development process. Then, as shown in FIG. 19, the copper thin film 10 is formed by a dry etching method using the resist pattern 108 as an etching mask.
7, the TiN film 106 and the Ti film 105 are removed and the wiring layer 1
09 is formed. Here, in order to etch the copper thin film 107, (Extended Abstracts of the 1990 Internatio
nal Conference on Solid State Devices and Material
s; pp.215-218), a dry etching method is used in which a wafer is heated to 250 to 300 ° C. using a mixed gas of silicon chloride (SiCl ₄ ), nitrogen, chlorine and ammonia. .

[0008] In this case, to heat the wafer to 250 to 300 ° C. is to separate the CuCl ₂ gas and chlorine and copper in the etching gas is generated rapidly react from the wafer surface. When etching aluminum with chlorine-based etching gas may include, but AlCl ₃ gas react chlorine and the aluminum can is produced, since high vapor pressure of the AlCl ₃ gas, the wafer is 50 to 80 ° C. Al just by heating
Cl ₃ gas is quickly separated from the wafer surface. Using the chlorine-based etching gas, the TiN film 106 and the T
Also when the i film 105 is etched, the wafer may be heated at 50 to 80 ° C. as in the case of aluminum. On the other hand, CuCl ₂
Since the vapor pressure of the gas is low, the CuCl ₂ gas cannot be separated from the wafer surface unless the wafer is heated to 250 to 300 ° C.

After that, as shown in FIG. 20, the resist pattern 108 is removed and the wiring layers 102 and 109 are used to remove the resist pattern.
The layer wiring structure is completed.

[0010]

The above-described conventional wiring manufacturing method has the following problems. (1) Method of forming copper thin film 107 When the MOCVD method is used, it takes time to manufacture the copper thin film 107 because the deposition rate is as slow as about 100 nm / min. The resistivity of the copper thin film 107 formed by the MOCVD method is 2.
1.7 μΩ, which is the original resistivity of copper, when it exceeds 0 μΩ ・ cm
・ It becomes higher than cm. This is because the constituent elements in the organic gas source used in the MOCVD method are impurities as impurities in the copper thin film 107.
It is considered that this is because of being mixed in. Furthermore, MOC
Since the organic gas source used in the VD method is expensive, the manufacturing cost is high.

Although the resistivity of the copper thin film 107 formed by the sputtering method is 1.9 Ω · cm, which is lower than that of the MOCVD method, it is higher than the original resistivity of copper. This is because the inert gas (argon or the like) used in the sputtering method is the copper thin film 107.
It is considered that this is because of being mixed in. Furthermore, the step coverage is limited in the sputtering method, and the contact hole 1
When 04 is miniaturized, voids are generated in the copper thin film 107 in the contact hole 104 and the contact resistance increases.

In the autocatalytic plating method, 1 μm copper thin film 1
It takes about 40 minutes to deposit 07, and MOCVD
It takes even longer than the law. Further, in the self-catalytic plating method, since cyanide, sodium and the like are contained in the bath, it adversely affects the substrate 101 and MO formed on the substrate 101.
Elements such as S-transistors may not operate normally.

(2) Etching of copper thin film 107 To etch the copper thin film 107, a wafer is set to 250 to 300.
Since it needs to be heated to ° C, a dry etching apparatus equipped with a high temperature heating mechanism must be used. But,
Since such a dry etching apparatus is not used in the conventional semiconductor device manufacturing process, it must be newly introduced, which requires capital investment and increases the scale of manufacturing equipment. Further, although a material having heat resistance must be used for the resist pattern 108, a resist having heat resistance of about 300 ° C. is not general and is expensive, so that the manufacturing cost is high.

By the way, when gold or silver is used as a wiring material, the same manufacturing method as that of copper causes the same problem. The present invention has been made to solve the above problems, and an object of the present invention is to provide a semiconductor device having a wiring with low resistance and high reliability.
Another object of the present invention is to provide a simple and low-cost manufacturing method of such a semiconductor device. Another object of the present invention is to provide an apparatus for manufacturing such a semiconductor device.

[0015]

SUMMARY OF THE INVENTION The invention according to claim 1 has a wiring having a structure in which a metal thin film is interposed between a barrier layer and a copper or noble metal thin film as a main wiring material. And

According to a second aspect of the present invention, a step of forming a metal thin film on a wafer and an electroplating method using the metal thin film as a cathode are used to form copper or a noble metal as a main wiring material on the surface of the metal thin film. The gist of the present invention is to have a step of forming a wiring made of a thin film.

According to a third aspect of the present invention, the wiring is formed by a step of forming a metal thin film on a wafer, a step of forming a wiring pattern on the metal thin film, and an electroplating method using the metal thin film as a cathode. Using the pattern as a mask, a step of forming a copper or noble metal thin film to be a main wiring material on the surface of the metal thin film, a step of removing the wiring pattern, and the metal thin film using the copper or noble metal thin film as an etching mask. The gist of the present invention is to have a step of etching.

According to a fourth aspect of the present invention, a step of forming a barrier layer on the wafer by a sputtering method, a step of forming a metal thin film on the barrier layer by a sputtering method or a MOCVD method, and the metal thin film And a step of forming a wiring made of a thin film of copper or a noble metal, which is a main wiring material, on the surface of the metal thin film by an electroplating method using as a cathode.

According to a fifth aspect of the invention, a step of forming a barrier layer on the wafer by a sputtering method, a step of forming a metal thin film on the barrier layer by a sputtering method or a MOCVD method, and the metal thin film A step of forming a wiring pattern thereon, and a step of forming a thin film of copper or a noble metal to be a main wiring material on the surface of the metal thin film by an electroplating method using the metal thin film as a cathode, using the wiring pattern as a mask, The gist of the present invention is to include a step of removing the wiring pattern and a step of etching the metal thin film and the barrier layer using the copper or noble metal thin film as an etching mask.

According to a sixth aspect of the present invention, a step of forming a barrier layer on the wafer by a sputtering method, a step of forming a metal thin film on the barrier layer by a sputtering method or a MOCVD method, and the metal thin film A step of forming a copper or noble metal thin film, which is a main wiring material, on the surface of the metal thin film by an electroplating method using a cathode as a cathode; a step of forming a wiring pattern on the copper or noble metal thin film; The gist of the present invention is to include a step of etching the copper or noble metal thin film, the metal thin film, and the barrier layer using the as a mask.

According to a seventh aspect of the present invention, there is provided a step of forming a contact hole in the interlayer insulating film and a sputtering method.
The step of forming a barrier layer on the inner surface of the contact hole, the step of forming a metal thin film on the barrier layer by a sputtering method or the MOCVD method, and the surface of the metal thin film by an electroplating method using the metal thin film as a cathode. A step of forming a thin film of copper or a noble metal as a main wiring material in the contact hole and filling the inside of the contact hole, and exposing the interlayer insulating film by a full-scale etchback method using a chemical mechanical polishing method or a dry etching method. The gist of the present invention is to have a step of forming a plug in the hole.

The invention according to claim 8 is the method for manufacturing a semiconductor device according to any one of claims 4 to 7,
The gist of the present invention is to omit the metal thin film and make the barrier layer conductive, and use the conductive barrier layer as the cathode of the electroplating method.

According to a ninth aspect of the present invention, in the method of manufacturing a semiconductor device according to any one of the second to eighth aspects,
The gist of the electroplating method is copper sulfate plating.

A tenth aspect of the present invention relates to a manufacturing apparatus used in the method for manufacturing a semiconductor device according to the ninth aspect, wherein a quartz tank filled with a copper sulfate bath and a temperature for controlling the temperature of the copper sulfate bath are used. The gist of the invention is to include a control device, a stirrer for stirring a copper sulfate bath, a filter for filtering the copper sulfate bath, a copper plate as an anode, and a constant current device for supplying a constant current between the anode and the cathode. .

[0025]

According to the first aspect of the present invention, by using a copper or noble metal thin film as the main wiring material, it is possible to realize a highly reliable wiring with low resistance. Further, by providing the metal thin film, the adhesion between the copper or noble metal thin film and the barrier layer can be improved. By providing the barrier layer, it is possible to prevent the copper or noble metal thin film and the lower layer (wafer, wiring layer, etc.) of the barrier layer from affecting each other.

According to the second aspect of the invention, it is possible to form the wiring made of a thin film of copper or noble metal on the wafer. The wiring formed by the electroplating method has excellent step coverage and has a low resistivity because impurities are less mixed therein. Further, the wiring can be formed quickly by optimizing the various conditions of the electroplating method.

According to the third aspect of the present invention, the wiring pattern is used as a mask for selectively depositing the copper or noble metal thin film to form the wiring layer without etching the copper or noble metal thin film. You can

According to the invention of claim 4, claim 1
The semiconductor described in 1. can be formed. According to the invention described in claim 5, similarly to the invention described in claim 3, the wiring layer can be formed without etching the thin film of copper or noble metal. In addition, a barrier layer can be formed.

According to the sixth aspect of the invention, it is possible to form the wiring made of a copper or noble metal thin film on the wafer. In addition, a barrier layer can be formed. According to the invention described in claim 7, the plug made of copper or noble metal can be formed by the electroplating method.

According to the invention described in claim 8, the semiconductor device according to any one of claims 4 to 7 can be manufactured without providing a metal thin film. According to the invention described in claim 9, the wiring can be formed by the copper thin film by the copper sulfate plating method. Since the copper sulfate plating method does not have the problem of the autocatalytic plating method, the copper thin film can be formed without affecting the wafer.

According to the tenth aspect of the invention, it is possible to provide an apparatus capable of forming a wiring by a copper thin film by the copper sulfate plating method.

[0032]

【Example】

(First Embodiment) A first embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a sectional view of the semiconductor device of this embodiment. A lower wiring layer 2 is formed on a single crystal silicon substrate (wafer) 1, and an interlayer insulating film 3 is formed thereon. A contact hole 4 for making contact with the substrate 1 and the wiring layer 2 is opened in the interlayer insulating film 3. An upper wiring layer 5 is formed on the interlayer insulating film 3. The wiring layer 5 is formed by sequentially laminating a Ti film 6, a TiN film 7, a tantalum (Ta) film 8 and a copper thin film 9 from the bottom, and contacts the substrate 1 and the wiring layer 2 through the contact holes 4. ing.

Next, the manufacturing method of this embodiment will be sequentially described with reference to the drawings. Step 1 (see FIG. 2): The wiring layer 2 is formed on the substrate 1, and the interlayer insulating film 3 is formed thereon. And the interlayer insulating film 3
A contact hole 4 is opened in the. The wiring layer 2 may be formed of any material such as a gate electrode of a MOS transistor made of polysilicon, a metal wiring layer, or the like, and may be formed by any method. Also, regarding the interlayer insulating film 3, a silicon oxide film, a silicon nitride film, a silicate glass (PSG,
Any material and forming method such as BPSG, ASG, etc. may be used.

Step 2 (see FIG. 3): A Ti film 6 (film thickness: 50 nm) is formed on the entire surface of the wafer including the inside of the contact hole 4 by the magnetron sputtering method. Next, by a magnetron sputtering method which also uses a reactive sputtering method, T
A TiN film 7 (film thickness: 100 nm) is formed on the i film 6. Then, a Ta film 8 (film thickness: 100 nm) is formed on the TiN film 7 by the magnetron sputtering method.

Step 3 (see FIG. 4): After applying a resist on the Ta film 8, a resist pattern 10 is formed through an exposure step and a development step. Step 4 (see FIG. 5): A copper thin film 9 is selectively deposited only on the Ta film 8 in the opening A (the portion where the resist pattern 10 is not formed) A of the resist pattern 10 by the copper sulfate plating method. That is, the resist pattern 10 is used as a mask for selectively depositing the copper thin film 9.

FIG. 7 shows a schematic structure of an apparatus for forming the copper thin film 9. This apparatus comprises a quartz tank 22 filled with a copper sulfate bath 21, a temperature control device 23, a stirrer 24, a pump 25, a filter 26, a pipe 27, a copper plate 28, a constant current device 29 and the like. The temperature control device 23, the pump 25, and the filter 26 are provided in the middle of the pipe 27. The copper sulfate bath 21 has a pipe 27 when the pump 25 operates.
It flows through the inside in the direction of arrow B, and circulates in the route of quartz tank 22 → filter 26 → pump 25 → temperature control device 23 → quartz tank 22. The temperature control device 23 is provided to control the temperature of the copper sulfate bath 21. The filter 26 is provided to remove particles contained in the copper sulfate bath 21 (that is, to filter the copper sulfate bath 21).
When the line width of the wiring layer 5 is 0.3 μm, particles of 0.1 μm or more can be removed. Stirrer 2
4 is provided for stirring the copper sulfate bath 21 in the quartz tank 22. The negative side terminal 29a of the constant current device 29 is connected to the Ta film 8 and the positive side terminal 2 of the constant current device 29 is connected.
9b is connected to the copper plate 28. The wafer (substrate 1) and the copper plate 28 are the copper sulfate bath 21 in the quartz tank 22.
It is soaked in. That is, the Ta film 8 serves as a cathode (cathode) and the copper plate 28 serves as an anode (anode).

In the copper sulfate bath 21, copper sulfate and sulfuric acid are the main components of the bath, copper sulfate is a source of divalent copper ions, and sulfuric acid has the action of increasing the conductivity and improving the dissolution of the anode. .
When the copper concentration in the copper sulfate bath 21 increases, the current density also increases and the deposition rate of the copper thin film 9 increases, but the uniform electrodeposition property deteriorates. Therefore, when the line width of the wiring layer 5 is narrow (resist pattern 10). When the width of the opening A is small), the copper thin film 9 cannot be reliably formed. On the contrary, when the concentration of sulfuric acid in the copper sulfate bath 21 is increased, the solubility of copper sulfate is lowered and the deposition rate of the copper thin film 9 is slowed down, but the uniform electrodeposition property is improved and the line width of the wiring layer 5 is narrow. Even in this case, the copper thin film 9 can be reliably formed. Therefore, copper sulfate bath 21
The ratio of sulfuric acid to copper is 4 or more and 10 or less (4 <sulfuric acid / copper <1
0) is desirable. For example, in the copper sulfate bath 21, the copper content is adjusted to 40 to 55 g / l and the sulfuric acid content is adjusted to 150 to 250 g / l.

When the temperature of the copper sulfate bath 21 (bath temperature) becomes higher, the current efficiency becomes higher and the deposition rate of the copper thin film 9 becomes faster, but the plating becomes rough and the uniform electrodeposition property deteriorates. Therefore, the bath temperature is preferably 20 to 80 ° C., and particularly 20 to 30 ° C. when the wiring layer 5 has a narrow line width.

If the stirring of the copper sulfate bath 21 by the stirrer 24 is improved, the cathode current efficiency can be made 100%, but if the cathode current density is too high, the plating will be rough and the uniform electrodeposition will be deteriorated. On the other hand, the anode current efficiency is 100% unless the anode current density is too low, but if the anode current density is too high, the dissolution of the cathode may deteriorate and passivation may occur. In addition, when both current densities increase, the voltage applied to the substrate 1 also increases, which causes lattice defects in the substrate 1 and dielectric breakdown of the interlayer insulating film 3.
Therefore, it is desirable that the cathode current density be 0.005 to 0.05 A / cm ² and the anode current density be 0.001 to 0.01 A / cm ² .

For example, copper in the copper sulfate bath 21 is 50 g / l, sulfuric acid is 200 g / l, bath temperature is 30 ° C., and cathode current density is 0.02 A / cm.
^2, when the anode current density was copper sulfate plating under conditions of 0.005 A / cm ^2, the voltage applied to the substrate 1 0.5 2V
Is low, and a lattice defect occurs in the substrate 1 or the interlayer insulating film 3
There is no fear of causing insulation breakdown. The deposition rate of the copper thin film 9 at this time is about 300 nm / min, and
This is much faster than the deposition rate (about 100 nm / min) when using the CVD method. Further, since the copper thin film 9 formed under the above conditions contains almost no impurities, the resistivity thereof is about 1.7 μΩ · cm, which is extremely close to the original value of copper.

FIG. 8 is a photomicrograph of the surface condition of the copper thin film 9 and the resist pattern 10 formed under the above conditions, observed with a scanning electron microscope (SEM). It can be seen that the copper thin film 9 is selectively deposited only in the opening A of the resist pattern 10.

If various conditions of the copper sulfate plating method are set in consideration of the uniform electrodeposition property as described above, no void is generated in the copper thin film 9 in the contact hole 4, and the contact resistance is Does not increase. For example, when the copper thin film 9 was formed under the above conditions, it was confirmed that voids did not occur even in the fine contact hole 4 having a hole size of 0.5 μm φ or less and an aspect ratio of 3 or more.

Step 5 (see FIG. 6): Resist pattern 1
Remove 0. As a removing method, any method such as a wet method using an organic solvent or a dry ashing method using a mixed gas of oxygen and nitrogen may be used.

Step 6 (see FIG. 1): Using the copper thin film 9 as an etching mask, a Ta film 8 and a Ti film 8 are formed by a dry etching method using a mixed gas of chlorine and boron chloride (BCl ₃ ).
The N film 7 and the Ti film 6 are removed. At this time, since heating of the wafer is sufficient at 50 to 80 ° C., a general dry etching apparatus can be used. In this way, the wiring layer 5 is completed, and the two-layer wiring structure including the wiring layers 2 and 5 is completed.

By the way, the TiN film 7 and the Ti film 6 function as a barrier layer. The TiN film 7 is formed in order to suppress the reaction between the copper thin film 9 and the substrate 1 and prevent an increase in junction leak current due to mutual diffusion. If the thickness of the TiN film 7 is increased, the aspect ratio of the wiring layer 5 is increased, which tends to make it difficult to flatten the surface.
The effect of suppressing the reaction between the substrate 1 and the substrate 1 tends to decrease. Therefore, the thickness of the TiN film 7 may be 30 to 150 nm, preferably 50 to 100 nm.

Further, the Ti film 6 is formed because the contact resistance becomes high when only the TiN film 6 is formed.
If the thickness of the Ti film 6 is increased, the aspect ratio of the wiring layer 5 is increased, which tends to make it difficult to flatten, and if the thickness is decreased, the contact resistance is increased and stable contact cannot be obtained. Therefore, the thickness of the Ti film 6 is 10
The thickness may be -100 nm, preferably 20-50 nm.

On the other hand, the reason for forming the Ta film 8 is to improve the adhesion between the TiN film 7 and the copper thin film 9 and to use it as a cathode in the copper sulfate plating method. T
If the film thickness of the a film 8 becomes thick, the aspect ratio of the wiring layer 5 becomes large, and it tends to be difficult to flatten it. If it becomes thin, the effect of improving the adhesion between the TiN film 7 and the copper thin film 9 tends to decrease. is there. Therefore, the Ta film 8 may have a thickness of 30 to 150 nm, preferably 50 to 100 nm.

As described above, according to this embodiment, by using the copper sulfate plating method, the copper thin film 9 having a low resistivity and excellent step coverage can be deposited quickly. Since the copper sulfate plating method does not have the problem of the above-mentioned autocatalytic plating method, the copper thin film 9 can be formed without affecting the substrate 1. Further, the materials (copper sulfate bath 21, copper plate 28) and equipment used in the copper sulfate plating method are inexpensive and easily available, and their operation is simple and highly controllable. Then, by using the resist pattern 10 as a mask for selectively depositing the copper thin film 9, the wiring layer 5 can be formed without etching the copper thin film 9. Therefore, it is not necessary to use a dry etching apparatus having a high temperature heating mechanism for etching the copper thin film. Therefore, according to this embodiment, the wiring layer 5 having low resistance and high reliability is provided.
Can be manufactured easily and at low cost.

In addition to the copper sulfate plating method, copper electroplating methods include copper cyanide plating method and copper pyrophosphate plating method. However, in the copper cyanide plating method, since the bath contains cyanide, sodium, potassium, etc., the substrate 1
Adversely affect. Also, in the copper pyrophosphate plating method,
Since the bath contains pyrophosphoric acid, potassium, etc., it also adversely affects the substrate 1. Therefore, these electroplating methods cannot be replaced by the copper sulfate plating method. On the other hand, the sulfuric acid used in the copper sulfate plating method has been frequently used for a long time in the manufacturing process of semiconductor devices, and it has been confirmed that it does not adversely affect the substrate 1.

(Second Embodiment) A second embodiment of the present invention will be described below with reference to the drawings. The sectional structure of the semiconductor device of this embodiment is the same as that of the first embodiment shown in FIG.

Next, the manufacturing method of this embodiment will be described in sequence with reference to the drawings. Step I (see FIG. 2) and step II (see FIG. 3); the same as step 1 and step 2 of the first embodiment.

Step III (see FIG. 9): A copper thin film 9 is deposited on the Ta film 8 by a copper sulfate plating method. That is,
In the first embodiment, Ta of the opening A of the resist pattern 10 is
Although the copper thin film 9 was selectively deposited only on the film 8, in the present embodiment, Ta on the entire surface of the wafer including the inside of the contact hole 4 was Ta.
A copper thin film 9 is deposited on the film 8.

The method of forming the copper thin film 9 is the same as in step 4 of the first embodiment. Therefore, similar to the first embodiment, if the conditions of the copper sulfate plating method are set in consideration of the uniform electrodeposition property, no void is generated in the copper thin film 9 in the contact hole 4 and the contact resistance is reduced. Does not increase.

Step IV (see FIG. 10): After applying a resist on the copper thin film 9, a resist pattern 10 is formed through an exposure step and a development step. Step V (see FIG. 11); Copper thin film 9 and Ta film are formed by a dry etching method in which the resist pattern 10 is used as an etching mask and a mixed gas of silicon chloride, nitrogen, chlorine, and ammonia is used to heat the wafer at 250 to 300 ° C. 8, Ti
The wiring layer 5 is formed by removing the N film 7 and the Ti film 6.

Step VI (see FIG. 12): The resist pattern 10 is removed by the same method as in Step 5 of the first embodiment. As a result, a two-layer wiring structure including the wiring layers 2 and 5 is completed. As described above, according to the manufacturing method of the present embodiment, by using the copper sulfate plating method as in the first embodiment, copper having a low resistivity and excellent step coverage can be obtained without adversely affecting the substrate 1. The thin film 9 can be deposited quickly. However, in this embodiment, the resist pattern 10 and the interlayer insulating film 3 are 25
Since the resist pattern 10 and the interlayer insulating film 3 are heated at 0 to 300 ° C., it is necessary to use a material having heat resistance higher than that.

(Third Embodiment) A third embodiment of the present invention will be described below with reference to the drawings. In the present embodiment, the same components as those in the first embodiment are designated by the same reference numerals and the description thereof will be omitted.

FIG. 12 shows a sectional view of the semiconductor device of this embodiment. In the contact hole 4, Ti film 6 and TiN
A copper plug 11 is embedded via the film 7 and the Ta film 8. A titanium / tungsten (TiW) film 12 as a barrier layer is formed on the copper plug 11, and an aluminum thin film 13 is formed thereon.
Are formed. This aluminum thin film 13 and TiW film 12
And form the upper wiring layer 14. That is, the wiring layer 14 is in contact with the underlying wiring layer 2 via the copper plug 11.

Next, the manufacturing method of this embodiment will be described in order with reference to the drawings. Step [1] (see FIG. 2), step [2] (see FIG. 3), step [3] (see FIG. 9); the same as step I, step II, and step III of the second embodiment.

Step [4] (see FIG. 13); In order to form the copper plug 11 leaving only the copper thin film 9 in the contact hole 4, chemical mechanical polishing (CMP; Chemical Mechanical Po
By the lishing) method, the entire surface of the laminated film including the copper thin film 9, the Ta film 8, the TiN film 7, and the Ti film 6 is etched back. That is, when the surface of the wafer is pressed against a polishing pad filled with a slurry-like polishing liquid to increase the relative movement speed of the polishing pad with respect to the surface of the wafer, the convex portions having large steps are preferentially polished. The entire surface etch back is completed when the interlayer insulating film 3 is exposed. For the chemical mechanical polishing method for copper thin films, see (VLSI Multilevel Intercon
nection Conference: pp.15-21 (1993)).

Step [5] (see FIG. 14); The TiW film 12 (film thickness; 50) is formed on the entire surface of the wafer by magnetron sputtering.
nm) and the aluminum thin film 13 are sequentially formed. Step [6] (see FIG. 12): After applying a resist on the aluminum thin film 13, a resist pattern (not shown) is formed through an exposure step and a development step. Then, the aluminum thin film 13 and the TiW film 12 are removed by a dry etching method using the resist pattern as an etching mask to form a wiring layer 14. As a result, the wiring layers 2 and 14
The layer wiring structure is completed.

As described above, according to this embodiment, the copper thin film 9 is buried in the contact hole 4 and the entire surface is etched back to form the copper plug 11 from the copper thin film 9. Therefore, the resistivity of the copper plug 11 is low and voids do not occur.

The above embodiments may be modified as follows, and in that case, the same operation and effect can be obtained. 1) Rather than forming the TiN film 7 by the magnetron sputtering method, after the Ti film 6 is formed, it is heated rapidly in a nitrogen or ammonia atmosphere to nitride the surface of the Ti film 6 to form the TiN film 7. To do.

2) Ti film 6 and TiN film 7 formed by magnetron sputtering, TiW film, Ti film alone, W
Replace with a barrier metal such as a single film. In this case, the Ta film 8 can be omitted by using the barrier metal as a cathode.

3) The Ta film 8 is replaced with a metal film of copper, tungsten, titanium, molybdenum, cobalt, nickel, palladium or the like. As a method of forming the metal film,
There are MOCVD method, sputtering method and the like. For example, in the MOCVD method of tungsten, tungsten fluoride (WF
₆ ) and hydrogen mixed gas is used. Since the metal film is thin, even if a copper film is used,
The heating of the wafer during etching in step 6 of the embodiment is
50-80 ° C is sufficient, and a general dry etching apparatus can be used.

4) The magnetron sputtering method used for forming each metal film is replaced with a normal sputtering method or an ion beam sputtering method. In the ordinary sputtering method, the structure of the sputtering apparatus is simple and the operation is easy. On the other hand, the ion beam sputtering method enables high-purity film formation.

5) The entire surface etch-back method in the step [4] of the third embodiment is not the chemical mechanical polishing method but the second method.
The same dry etching method as used in step V of the embodiment is used instead. 6) Use the TiW film 12 as an appropriate barrier layer (TiN film alone, T
The i-film 6 and the TiN film 7 have the same laminated structure film, etc.).

7) In mass production of semiconductor devices, the copper thin film 9 is not formed for each wafer (substrate 1), but a plurality of wafers are placed on a rack and the copper sulfate bath 21 in the quartz tank 22 is placed. Then, the copper thin film 9 is simultaneously formed on a plurality of wafers.

8) The copper thin film 9 is replaced with a thin film of noble metal (gold, silver, platinum, rhodium, palladium) formed by electroplating. 9) The resist pattern 10 in the second embodiment is replaced with a pattern made of a silicon oxide film.

Although the respective embodiments of the present invention have been described above, technical ideas other than the claims which can be understood from the respective embodiments will be described below together with their effects. (A) A semiconductor device in which the barrier layer is any one of a laminated structure of a titanium film and a titanium nitride film, a titanium nitride film alone, a titanium tungsten film, a tungsten film alone, and a titanium film alone. In this way, the effect of the invention can be enhanced by optimizing the structure and material of the barrier layer with respect to the layers formed above and below (that is, the metal thin film and the wafer or wiring layer).

(B) A semiconductor device in which the metal thin film is made of one material selected from the group consisting of copper, tungsten, titanium, tantalum, molybdenum, cobalt, nickel, and palladium. In this way, the effect of the invention can be enhanced by optimizing the material of the metal thin film with respect to the layers formed above and below (that is, the copper or noble metal thin film and the barrier layer).

(C) The semiconductor device in which the noble metal thin film is made of one material selected from the group consisting of gold, silver, platinum, rhodium, and palladium. By doing so, the noble metal thin film can be selected according to the resistance and reliability required for the wiring.

(D) In the method of manufacturing a semiconductor device according to claim 8, the conductive barrier layer is a semiconductor device in which one of a titanium tungsten film, a tungsten film alone, and a titanium film alone is used. Production method. In this way, the effect of the invention can be enhanced by optimizing the structure and material of the barrier layer with respect to the layers formed above and below it (that is, the thin film of copper or noble metal and the wafer or wiring layer). it can.

In the present specification, members relating to the constitution of the invention are defined as follows. (A) Wafer includes not only a silicon substrate but also a semiconductor substrate other than silicon such as gallium arsenide, an insulating substrate such as quartz or glass having a semiconductor thin film formed on its surface, and the like.

(B) The wiring pattern includes not only a resist pattern but also a pattern made of any material which can be easily removed and can be formed into a fine pattern such as a silicon oxide film or a silicon nitride film.

[0076]

As described above in detail, according to the present invention, it is possible to provide a semiconductor device having a wiring with low resistance and high reliability. Further, it is possible to provide a simple and low-cost manufacturing method and manufacturing apparatus for such a semiconductor device.

[Brief description of drawings]

FIG. 1 is a sectional view showing a structure of a first embodiment embodying the present invention.

FIG. 2 is a cross-sectional view for explaining a manufacturing method of first to third embodiments embodying the present invention.

FIG. 3 is a sectional view for explaining the manufacturing method according to the first to third embodiments.

FIG. 4 is a cross-sectional view for explaining the manufacturing method of the first embodiment.

FIG. 5 is a cross-sectional view for explaining the manufacturing method of the first embodiment.

FIG. 6 is a cross-sectional view for explaining the manufacturing method of the first embodiment.

FIG. 7 is a schematic configuration diagram of an apparatus for forming a copper thin film 9.

FIG. 8 is a micrograph showing a surface state of a device in the process of manufacturing in the first example.

FIG. 9 is a sectional view for explaining the manufacturing method for the first and second embodiments.

FIG. 10 is a sectional view for explaining the manufacturing method for the second embodiment.

FIG. 11 is a cross-sectional view for explaining the manufacturing method of the second embodiment.

FIG. 12 is a cross-sectional view showing the structure of the third embodiment.

FIG. 13 is a cross-sectional view for explaining the manufacturing method of the third embodiment.

FIG. 14 is a sectional view for explaining the manufacturing method for the third embodiment.

FIG. 15 is a cross-sectional view for explaining the manufacturing method of the conventional example.

FIG. 16 is a cross-sectional view for explaining the manufacturing method of the conventional example.

FIG. 17 is a cross-sectional view for explaining the manufacturing method of the conventional example.

FIG. 18 is a cross-sectional view for explaining the manufacturing method of the conventional example.

FIG. 19 is a cross-sectional view for explaining the manufacturing method of the conventional example.

FIG. 20 is a cross-sectional view for explaining the manufacturing method of the conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Substrate (wafer) 3 Interlayer insulating film 4 Contact hole 6 Titanium film as a barrier layer 7 Titanium nitride film as a barrier layer 8 Tantalum film as a metal film 9 Copper thin film 10 Resist pattern as a wiring pattern 11 Plug 21 Copper sulfate bath 22 quartz tank 23 temperature control device 24 stirrer 26 filter 28 copper plate 29 constant current device

Claims (10)

[Claims] 1. A semiconductor device comprising a wiring having a structure in which a metal thin film (8) is interposed between a barrier layer (6, 7) and a copper or noble metal thin film (9) as a main wiring material. 2. A thin film of copper or a noble metal used as a main wiring material on the surface of the metal thin film by a step of forming a metal thin film (8) on a wafer (1) and an electroplating method using the metal thin film as a cathode. (9) A method of manufacturing a semiconductor device, comprising the step of forming wiring. 3. A step of forming a metal thin film (8) on the wafer (1), a step of forming a wiring pattern (10) on the metal thin film, and an electroplating method using the metal thin film as a cathode. Using the wiring pattern as a mask, a step of forming a copper or noble metal thin film (9) as a main wiring material on the surface of the metal thin film, a step of removing the wiring pattern, an etching mask for the copper or noble metal thin film And a step of etching the metal thin film as a method of manufacturing a semiconductor device. 4. A step of forming a barrier layer (6, 7) on the wafer (1) by a sputtering method, and a step of forming a metal thin film (8) on the barrier layer by a sputtering method or a MOCVD method. And a step of forming a wiring made of a copper or noble metal thin film (9) which is a main wiring material on the surface of the metal thin film by an electroplating method using the metal thin film as a cathode. 5. A step of forming a barrier layer (6, 7) on the wafer (1) by a sputtering method, and a step of forming a metal thin film (8) on the barrier layer by a sputtering method or a MOCVD method. A step of forming a wiring pattern (10) on the metal thin film, and an electroplating method using the metal thin film as a cathode, using the wiring pattern as a mask, copper or a noble metal serving as a main wiring material on the surface of the metal thin film. Forming a thin film (9), removing the wiring pattern, and etching the metal thin film and the barrier layer using the copper or noble metal thin film as an etching mask. . 6. A step of forming a barrier layer (6, 7) on the wafer (1) by a sputtering method, and a step of forming a metal thin film (8) on the barrier layer by a sputtering method or a MOCVD method. , A step of forming a copper or noble metal thin film (9) as a main wiring material on the surface of the metal thin film by an electroplating method using the metal thin film as a cathode, and a wiring pattern (10) on the copper or noble metal thin film. ), And a step of etching the copper or noble metal thin film, the metal thin film, and the barrier layer using the wiring pattern as an etching mask. 7. A step of forming a contact hole (4) in an interlayer insulating film (3), a step of forming a barrier layer (6, 7) on the inner surface of the contact hole by a sputtering method, and a sputtering method or a MOCVD method. By the step of forming a metal thin film (8) on the barrier layer and an electroplating method using the metal thin film as a cathode, a copper or noble metal thin film (9) as a main wiring material is formed on the surface of the metal thin film. A step of forming and filling the contact hole, and a step of exposing the interlayer insulating film to form a plug (11) in the contact hole by a chemical mechanical polishing method or a dry etch method. A method for manufacturing a semiconductor device comprising: 8. The method of manufacturing a semiconductor device according to claim 4, wherein the metal thin film is omitted and the barrier layer is made conductive, and the conductive barrier layer is formed by a cathode of an electroplating method. A method of manufacturing a semiconductor device, comprising: 9. The method of manufacturing a semiconductor device according to claim 2, wherein the electroplating method is a copper sulfate plating method. 10. A quartz tank (22) filled with a copper sulfate bath (21), a temperature control device (23) for controlling the temperature of the copper sulfate bath, and a stirrer (24) for stirring the copper sulfate bath. The semiconductor according to claim 9, comprising a filter (26) for filtering a copper sulfate bath, a copper plate (28) as an anode, and a constant current device (29) for supplying a constant current between the anode and the cathode (8). A manufacturing device used in a method of manufacturing a device.