TW529177B - MOS low-voltage vertical transistor - Google Patents

MOS low-voltage vertical transistor Download PDF

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TW529177B
TW529177B TW090128190A TW90128190A TW529177B TW 529177 B TW529177 B TW 529177B TW 090128190 A TW090128190 A TW 090128190A TW 90128190 A TW90128190 A TW 90128190A TW 529177 B TW529177 B TW 529177B
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vertical transistor
low
mos
voltage vertical
region
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TW090128190A
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Peter Sommer
Jenoe Tihanyi
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Infineon Technologies Ag
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7812—Vertical DMOS transistors, i.e. VDMOS transistors with a substrate comprising an insulating layer, e.g. SOI-VDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H01L29/7824—Lateral DMOS transistors, i.e. LDMOS transistors with a substrate comprising an insulating layer, e.g. SOI-LDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78642—Vertical transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor
    • H10B12/053—Making the transistor the transistor being at least partially in a trench in the substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/485—Bit line contacts
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41741—Source or drain electrodes for field effect devices for vertical or pseudo-vertical devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H01L29/456—Ohmic electrodes on silicon

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  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

The invention relates to a MOS low-voltage vertical transistor (VMT), in which the rear-side drain electrode (12) is connected to a vertically extending drain zone (7) via a plug (11) in an insulating layer (9).

Description

529177 A7 __B7 五、發明説明（1 ) 本發明係關於一種金屬氧化物半導體（卜丨〇5)低電壓（LV)垂 直電晶體。 IEEE SPECTRUM 1999年8月號中第79頁揭示一 MOS垂直 電晶體’其沒極形成一儲存節點’以及同時在一 DRAM單 元中形成一傳統場效電晶體的閘極。其他低阻抗電力的 M〇S場效電晶體之實例，還有HEXFET和SIPMOS結構。 本發明的目的是為提供一種MOS低電壓垂直電晶體，其 可以簡單地連接到任何一個其他的基板。 根據本發明由一MOS低電壓垂直電晶體的方式達到該目 的。該M〇S低電壓垂直電晶體具有第一導電型態的一半導 體主體，其具有一第一和一第二主要表面，並在進入連接 該第一主要表面的區域有相反於該第一導電型態之一第二 導電型態的一源極區帶，該第二主要表面上所提供的一絕 緣層具有一窗口，該窗口是在與該緣極區帶不相對區域的 該第二主要表面之一區域内，由多晶系矽組成的一汲極電 極，經由該窗口延伸出去，該第二導電型態的一區域從該 第二主要表面延伸至該窗口下方，以沒有接觸該源極區帶 的方式到達該第一主要表面處一樣的深度，以及一閘電極 是位於該源極區帶與該第二導電型態區域之間，且在該第 一主要表面上方。 該汲極電極的多晶系矽最好以一η‘摻雜多晶系矽層組成， 因為後者可以相當簡單地連接至其他任何的基板，像是一 另外的半導體主體，至少包括一儲存電容器。此另外的半 導體主體，如果適當的話，也可以有另外一個電晶體，例 -4 - 本紙張尺度適用中國國家A4規格~—--- 529177 A7 ____一一 B7 i、發明説明（2 ) ' ^ ~ 如：一 μ〇s侧面電晶體或一 M〇s垂直電晶體。 具有該窗口的絕緣層位於形成汲極電極的該n‘導電多晶系 矽層上，該絕緣層最好是以二氧化矽組成。此二氧化矽層 是以形成該窗口的一個或其他複數個洞提供，連接該第二 導電型態區域至該^導電多晶系矽層的一插塞是經由該窗 口或經由該洞從上向外擴散或植入，具有相同導電型態的 該插塞當作是該第二導電型態的區域。 該MOS低電壓垂直電晶體中，形成該半導體的一矽層應 用於該絕緣層上，該源極區域是安排在該矽層内。 如果根據本發明的MOS低電壓垂直電晶體，經由其汲極 電極組成的一多晶系矽層連接至一另外的矽基板，如上所 述，該基板獲得一儲存電容器和一另外的電晶體，如果適 當的話。因此其可以優異的方式適用於一 DRAM記憶體單 元’有別於一極小的空間要求。 參考下面的圖示可以更加詳細地解釋本發明，該圖示包 括： 圖1顯示根據本發明MOS低電壓垂直電晶體之一具體實施 例的一縱向戴面圖， 圖2顯示使用根據本發明M〇s低電壓垂直電晶體的一 DRAM記憶體單元之一縱向截面圖， 圖3是相關於圖2的DRAM記憶體單元之等效電路圖，以及 圖4顯示包括根據本發明兩個^4〇5低電壓垂直電晶體的一 DRAM記憶體單元另一實例之縱向戴面圖。 圖1顯示穿過根據本發明MOS低電壓垂直電晶體具體實施 本紙張尺度適用中國國家標準(CNS) A4規格(210 χ 297公釐) 529177 A7 五、發明説明（3 例之另一實例的縱向戴面圖。 第Λ辱Π半導體的主體1，特別是㈣所組成的，在其 構而且开I内具有…電區帶3’為具有-環狀的架 4_極。此隸區帶3連接至由金屬製成的 極接响層4，例如·庐β如+ 3 , ·. 士、 1 Μ •像疋鋁或是由^導電多晶系矽組成，同 二接至-源極電極s。還有，像以二氧化矽製成的一絕緣 層）是提供於該半導體主體1上方區域内的主要表面2上，一 閘極私極6或由η+導電多晶系矽製成的G組合於該絕緣層内 。该半導體主體1内，一n導電區域7是位於該閘極電極6的 下方，並與該源極區帶3有一段距離之該區域，從該第一主 要表面2延伸至該半導體主體1的一主要表面8—樣遠處， (與後者相對之）。例如：另外由二氧化矽製成的一絕緣層9 可以提供於該主要表面8上，至少一個位於該絕緣層内的洞 形成一窗口 10,其窗口是填入多晶系矽製成的一n+導電插 塞丨丨。此插塞1 1連接該n導電區域丨至一 n-導電之多晶系矽 層1 “其位於5亥絕緣層9上並且為一〉及極電極D。該插塞η 藉由從該多晶系矽層12的η導電雜質向外擴散摻雜，或是在 半導體主體1加於該絕緣層9之前以像是”精敏切割”植入摻 雜。 根據本發明的MOS低電壓垂直電晶體可以簡單的方式連 接至其他任何基板，此歸屬於該η —導電多晶系矽層丨2位於 •'底部"之類。接下來參考圖2和圖4的一 DRAM記憶體單元， 將有更詳細的解釋。 圖2顯示一 D RAM記憶體單元，其中圖1具體實施例的該 6 - 本紙張尺度適用中國國家標準(CNS) A4規格（210 X 297公釐） 529177529177 A7 __B7 V. Description of the invention (1) The present invention relates to a metal oxide semiconductor (Bu 05) low voltage (LV) vertical transistor. IEEE SPECTRUM, August 1999, page 79 discloses a MOS vertical transistor 'its terminal forms a storage node' and simultaneously forms the gate of a conventional field effect transistor in a DRAM cell. Examples of other low impedance power MOS field effect transistors include HEXFET and SIPMOS structures. The object of the present invention is to provide a MOS low-voltage vertical transistor which can be simply connected to any other substrate. This is achieved according to the invention by means of a MOS low voltage vertical transistor. The MOS low-voltage vertical transistor has a semiconductor body of a first conductivity type, which has a first and a second major surface, and is opposite to the first conductivity in a region entering the first major surface. A source region of a second conductivity type, an insulating layer provided on the second main surface has a window, and the window is the second main region in a region that is not opposite to the marginal region In one area of the surface, a drain electrode composed of polycrystalline silicon extends through the window, and an area of the second conductivity type extends from the second main surface to below the window so as not to contact the source. The polar zone approached the same depth at the first major surface, and a gate electrode was located between the source zone and the second conductivity type region, and above the first major surface. The polycrystalline silicon of the drain electrode is preferably composed of an η′-doped polycrystalline silicon layer, because the latter can be connected to any other substrate fairly easily, such as an additional semiconductor body, including at least a storage capacitor. . This other semiconductor body, if appropriate, can also have another transistor, Example-4-This paper size applies to China's national A4 specifications ~ --- --- 529177 A7 ____ one one B7 i. Description of the invention (2) ^ ~ For example: a μs side transistor or a Ms vertical transistor. The insulating layer having the window is located on the n 'conductive polycrystalline silicon layer forming the drain electrode, and the insulating layer is preferably composed of silicon dioxide. The silicon dioxide layer is provided by one or other holes forming the window, and a plug connecting the second conductive type region to the ^ conductive polycrystalline silicon layer is through the window or through the hole from above. Diffusion or implantation, the plug with the same conductivity type is regarded as the area of the second conductivity type. In the MOS low-voltage vertical transistor, a silicon layer forming the semiconductor is applied to the insulating layer, and the source region is arranged in the silicon layer. If the MOS low-voltage vertical transistor according to the present invention is connected to an additional silicon substrate via a polycrystalline silicon layer composed of its drain electrode, as described above, the substrate obtains a storage capacitor and an additional transistor, If appropriate. Therefore, it can be applied in an excellent manner to a DRAM memory unit 'differently from a very small space requirement. The present invention can be explained in more detail with reference to the following diagram, which includes: FIG. 1 shows a longitudinal wearing view of a specific embodiment of a MOS low voltage vertical transistor according to the present invention, and FIG. 2 shows the use of M according to the present invention. 〇s a low-voltage vertical transistor of a DRAM memory cell in a longitudinal sectional view, FIG. 3 is an equivalent circuit diagram of the DRAM memory cell related to FIG. 2, and FIG. Vertical wear view of another example of a DRAM memory cell with a low voltage vertical transistor. Figure 1 shows the implementation of the MOS low-voltage vertical transistor according to the present invention. The paper size applies the Chinese National Standard (CNS) A4 specification (210 x 297 mm) 529177 A7. 5. Description of the invention (3 examples of another example) The surface of the first semiconductor semiconductor, especially the ㈣, is composed of 电 and I in its structure and the electric zone 3 'is a frame with a ring-shaped 4 pole. This slave zone 3 Connected to a pole-response layer 4 made of metal, such as · β β such as + 3, ···, 1 Μ • Like 疋 aluminum or composed of ^ conductive polycrystalline silicon, connected to the-source electrode s. Also, like an insulating layer made of silicon dioxide) is provided on the main surface 2 in the area above the semiconductor body 1, a gate electrode 6 or made of η + conductive polycrystalline silicon G is combined in the insulating layer. In the semiconductor body 1, an n-conducting region 7 is located below the gate electrode 6 and is a distance from the source zone 3, and extends from the first main surface 2 to the semiconductor body 1. A major surface 8-like distance, (as opposed to the latter). For example, an insulating layer 9 made of silicon dioxide may be provided on the main surface 8, and at least one hole in the insulating layer forms a window 10, and the window is made of polycrystalline silicon. n + conductive plug 丨 丨. The plug 11 is connected to the n-conducting region 丨 to an n-conductive polycrystalline silicon layer 1 "it is located on the insulating layer 9 and is one" and the electrode D. The plug η is connected from the poly The n conductive impurities of the crystalline silicon layer 12 are diffused and doped out, or the semiconductor body 1 is implanted with a doping like "fine cutting" before the semiconductor body 1 is added to the insulating layer 9. The MOS low-voltage vertical electrical The crystal can be connected to any other substrate in a simple manner, which belongs to the η-conductive polycrystalline silicon layer 2 is located at the “bottom” or the like. Next, referring to a DRAM memory cell of FIGS. 2 and 4, There is a more detailed explanation. Figure 2 shows a D RAM memory unit, in which the 6-this paper size of the specific embodiment of Figure 1 applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 529177

-電c垂直電晶體是安排在一側面場效電晶體上，守 2政f晶體有一 P—導電半導體主體14與η導電源極和汲極區 :’分別為15和16，以及由二氧化矽製成的一絕緣層17。 這種凊况的该多晶系矽層12是位於該絕緣層1 7上，使其形 成側面场效電晶體的一閘極電極，同時從η-導電多晶系 矽層12和η導電區帶15以及η導電區帶16之每一個情況下， 刀別產生儲存電容器c丨和C2，其電容器内該電介質從該絕 緣層17所形成。該源極區帶15是接地的，而在一端的該汲 極區帶1 6有一 +3伏特（V)的供給電位，例如：經由一電阻R 外加於上，另一端則是連接至一感應放大器SA。 所以，圖2的安排形成一具有一 M〇s低電壓垂直電晶體 VMT的記憶體單元，該M〇s低電壓垂直電晶體連接到一位 兀線BL，一字元線冒1，以及經由一儲存節點匕連接至一儲 存電容器C1和C2，還有該垂直M0S場效電晶體LMt，正是 呈現在圖3中圖2所安排的等效電路圖。 圖4顯示根據本發明一具有該M〇s低電壓垂直電晶體之一 記憶體單元的另一實例，然而對照於圖2的例子，此實例所 提供的是另一 MOS低電壓垂直電晶體VMT，，以取代該垂直 場效電晶體LMT。而此另一個MOS低電壓垂直電晶體VM丁， 疋與该垂直電晶體VM丁相似的方式架構，並且具有當作汲 極的接觸區帶以取代多晶糸石夕層12，而一 π"1"導電區域18 一 方面是連接到該感應放大器SA，另一方面則是經由電阻R 連接到一約為+3 V的供給電壓。該rT導電源極區帶3，和該p ^電半導體主體1 一起接地’而且該源極是以η導電區域7， 本紙張尺度適用中國國家標準(CNS) Α4規格(210 X 297公釐) 529177 五、發明説明（5 形成的。 广-和圖4的具體實施例中，極接觸層4最好由〇導卞 多晶系石夕組成。然而也可以提供—金屬，特別像是^電 代該導電多晶系矽。 ’取 ▲特定的導電型態也可以互換。此情況下以實例 »亥半午體主體1或lln導電，同時區域7或7，就是ρ導：' 同，情形也可以適用於該半導體主體的其他區域。。相 取後也可以使用_種不同的 是例如··石炭化石夕以取代石夕。還有，本發明^虹主耻，像 一 7w - 百本發明也不限於應用在 可1 =二：是根據本發明的_低電壓垂直電晶體 使用於”夕曰曰糸石夕層12堆疊於一另外半導體主體上之 任何特別有利的情況。 參考符號表 1 P導電半導體主體 2 較高的主要表面 n+導電源極區帶 4 源極接觸層 5 絕緣層 6 閘極電極 7 η導電區域 8 較低的主要表面 9 絕緣層 10 窗口 11 ^導電插塞 i紙張尺度^家標準(CNS) Α4規格(210-Electric c vertical transistor is arranged on a side field effect transistor. The crystal f has a P-conducting semiconductor body 14 and n conductive power source and drain regions: '15 and 16 respectively, and by the dioxide An insulating layer 17 made of silicon. In this case, the polycrystalline silicon layer 12 is located on the insulating layer 17 so that it forms a gate electrode of a side field effect transistor, and simultaneously from the η-conductive polycrystalline silicon layer 12 and the η conductive region In each case of the band 15 and the n conductive zone band 16, the storage capacitors c 丨 and C2 are generated by the knife, and the dielectric within the capacitor is formed from the insulating layer 17. The source zone 15 is grounded, and the drain zone 16 at one end has a supply potential of +3 volts (V), for example: it is applied to it via a resistor R, and the other end is connected to an inductor Amplifier SA. Therefore, the arrangement of FIG. 2 forms a memory cell having a MOS low voltage vertical transistor VMT, which is connected to a bit line BL, a word line 1 and A storage node D is connected to a storage capacitor C1 and C2, and the vertical MOS field effect transistor LMt is the equivalent circuit diagram shown in FIG. 3 and FIG. 2. FIG. 4 shows another example of a memory cell having the Mos low voltage vertical transistor according to the present invention. However, compared to the example of FIG. 2, this example provides another MOS low voltage vertical transistor VMT. To replace the vertical field effect transistor LMT. This other MOS low-voltage vertical transistor VM is structured in a similar manner to the vertical transistor VM and has a contact zone as a drain to replace the polycrystalline vermiculite layer 12, and a π " 1 " The conductive region 18 is connected to the sense amplifier SA on the one hand, and to a supply voltage of approximately +3 V via a resistor R on the other hand. The rT conducting power source electrode band 3 is grounded together with the p ^ semiconductor body 1 'and the source electrode is η conductive region 7. This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 529177 V. Description of the invention (formed by 5) In the specific embodiment of FIG. 4 and FIG. 4, the electrode contact layer 4 is preferably composed of a polycrystalline stone. However, it can also be provided—metal, especially like electricity. Substitute the conductive polycrystalline silicon. 'Take ▲ specific conductivity types can also be interchanged. In this case, an example »Hemi-Benton body 1 or lln is conductive, while region 7 or 7, which is ρ conductance:' Same, situation It can also be applied to other areas of the semiconductor body. It can also be used after the phase is taken. The difference is, for example ,: • charcoal fossil evening to replace stone evening. Also, the present invention ^ Hong Zhuan, like a 7w-Baiben The invention is not limited to any particularly advantageous situation where 1 = two: low voltage vertical transistors according to the present invention are used in "Xi Yue Xiu Shi Xi Xi layer 12 stacked on another semiconductor body. Reference symbol table 1 P conductive semiconductor body 2 Higher main surface n + conductive power source zone 4 source contact layer 5 insulating layer 6 gate electrode 7 η conductive area 8 lower major surface 9 insulating layer 10 window 11 ^ conductive plug i paper size ^ home standard (CNS) Α4 specifications ( 210

X 297公釐） 529177 A7 B7 五、發明説明（6 ) 12 多晶系石夕層 13 絕緣層 14 另外的半導體主體 15 另外的源極區帶 16 另外的汲極區帶 17 絕緣層 18 n+導電接觸區域 R 電阻 SA 感應放大器 G 閘極電極 S 源極電極 D >及極電極 BL 位元線 WL 字元線 VMT，VMT’ MOS垂直電晶體 LMT M〇S側面電晶體 -9 - 本紙張尺度適用中國國家標準(CNS) A4規格（210 x 297公釐）X 297 mm) 529177 A7 B7 V. Description of the invention (6) 12 Polycrystalline stone layer 13 Insulating layer 14 Other semiconductor body 15 Other source zone 16 Other drain zone 17 Insulating layer 18 n + conductive Contact area R Resistance SA Induction amplifier G Gate electrode S Source electrode D > and electrode BL bit line WL word line VMT, VMT 'MOS vertical transistor LMT M0S side transistor-9-paper size Applicable to China National Standard (CNS) A4 (210 x 297 mm)

Claims (1)

529177 A8 B8 C8 申請專利範圍 l* 一種金屬氧化物半導體（M〇S)低電壓垂直電晶體（νΜτ， VMT’）’其具有第一導電型態的一半導體主體（1，㈠，該 主肢有第一（2)和一第二（8)主要表面，並在進入連接該 第主要表面（2)的區域有相反於該第—導電型雜之一第 二導電型態的一源極區帶（3, 3，）；在該第二主要表面（8) 上提ί、的一絕緣層（9)具有一窗口（1〇)，該窗口（ι〇)是在 與该源極區帶（3，3’）不相對區域的該第二主要表面（8)之 區域内，由多晶系矽組成的一没極電極（1 1，12)經由該 窗口（10)延伸出去，該第二導電型態的一區域（7, 7，）從該 第二主要表面（8)延伸至該窗口（10)上方，以沒有接觸該 源極區I (3，3’）的方式到達該第一主要表面（2)深遠處， 以及一閘電極（6，G)是位於該源極區帶（3, 3，）與該第二導 電型恶區域（7，7’）之間，且在該第一主要表面（2)上方。 2.如申請專利範圍第1項之MOS低電壓垂直電晶體，其特 徵在於該汲極電極（Η，12)是以高度摻雜的多晶系矽所組 成。 j.如申凊專利範圍第1項之MOS低電壓垂直電晶體，其特 徵在於所提供的該垂直電晶體，是用來形成一 DRAM記 憶體單元於一另外的半導體主體（14，1，）上，其至少包括 一個儲存電容器（C1，C2)。 4. 如申請專利範圍第1至3項其中一項之MOS低電壓垂直電 晶體’其特徵在於該另外的半導體主體（14)額外地包括 一 MOS側面電晶體（Lmt)。 5. 如申請專利範圍第1至3項其中一項之MOS低電壓垂直電 -10 - 本纸張尺度適用中國國家標準(CNS) A4規格(210X297公釐） A BCD 529177529177 A8 B8 C8 Patent application scope 1 * A metal oxide semiconductor (MOS) low voltage vertical transistor (νΜτ, VMT ')' which has a semiconductor body (1, ㈠, the main limb of the first conductivity type) There is a first (2) and a second (8) main surface, and a source region opposite to the second conductive type of the first conductive type is provided in an area connecting to the first main surface (2). A band (3, 3,); an insulating layer (9) provided on the second main surface (8) has a window (10), and the window (ι〇) is in a zone with the source region (3,3 ') In the region of the second major surface (8) that is not opposite, an electrode (11, 12) composed of polycrystalline silicon extends out through the window (10), and the first A region (7, 7,) of the two conductivity type extends from the second main surface (8) to above the window (10), and reaches the first region in a way that does not contact the source region I (3, 3 '). A major surface (2) is deep and far away, and a gate electrode (6, G) is located between the source region (3, 3,) and the second conductive type evil region (7, 7 '). And above the first major surface (2). 2. If the MOS low-voltage vertical transistor of item 1 of the patent application scope is characterized in that the drain electrode (Η, 12) is highly doped It is composed of crystalline silicon. J. The MOS low-voltage vertical transistor, as described in the first item of the patent application, is characterized in that the vertical transistor provided is used to form a DRAM memory unit in another semiconductor body. (14,1,), which includes at least one storage capacitor (C1, C2). 4. If the MOS low-voltage vertical transistor according to one of the claims 1 to 3 is characterized by the additional semiconductor body (14) In addition, it includes a MOS side transistor (Lmt). 5. If the MOS low-voltage vertical power of one of the items 1 to 3 of the scope of patent application is -10-This paper size applies to Chinese National Standard (CNS) A4 Specifications (210X297 mm) A BCD 529177 曰日，其特欲在於該另外的半導體主體（1，）額外地包括一 MOS垂直電晶體（VMr)。 6 T申請專利範圍第1至3項其中一項之M0S低電壓垂直電 晶體，其特徵在於該源極區帶（3)是連接至—位元線，以 及。亥問電極（6，G)是連接到—記憶體單元的—字元線 (WL)。 7. 3申μ專利範圍第1至3項其中一項之m〇S低電壓垂直電 晶體、，其特徵在於該第一導電型態是Ρ導電型態，而且該 第一導電型態是η導電型態。 8. ★申#專利範圍第1至3項其中一項之m〇S低電壓垂直電 曰曰曰體’其特徵在於該第二導電型態之區域(7，7，)是連接 到^窗σ (1 〇)内該多晶系梦層（12)的-插塞（11)。 9. 如申巧專利乾圍第8項之M〇s低電壓垂直電晶體，其特 Μ在於。亥插基⑴）是以向外擴散或植入的方式推雜。 10. 如申請專利範圍第！至3項其中一項之M〇s低電壓垂直電 曰曰，其知·被在於該多晶系矽層〇2)形成一另外電晶體 的閘極電極和/或儲存電容器（C1，的一電極。On the day, the special purpose is that the additional semiconductor body (1,) additionally includes a MOS vertical transistor (VMr). 6 T The patented M0S low voltage vertical transistor of one of the items 1 to 3 is characterized in that the source region (3) is connected to a bit line, and. The helium electrode (6, G) is connected to the-word line (WL) of the -memory cell. 7. The m0S low-voltage vertical transistor in one of the first to third aspects of the patent application, characterized in that the first conductivity type is a P conductivity type, and the first conductivity type is η Conductive type. 8. ★ The # 0 patent range of one of the items 1 to 3 of the m0S low-voltage vertical electric body is characterized in that the region (7, 7,) of the second conductivity type is connected to the window The plug (11) of the polycrystalline dream layer (12) within σ (10). 9. For example, the M0s low-voltage vertical transistor in item 8 of the Shenqiao patent is characterized by its characteristics.插 Insertion base ⑴) pushes impurities by way of outward diffusion or implantation. 10. Such as the scope of patent application! One of the three items of M0s low-voltage vertical electricity is known, it is known that the polycrystalline silicon layer (2) forms a gate electrode and / or a storage capacitor (C1, a electrode. -11--11-
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