DE10056296C1 - MOS vertical transistor for LV applications has polycrystalline drain electrode in window of insulation layer on one side of semiconductor body and gate electrode within insulation layer on its opposite side - Google Patents
MOS vertical transistor for LV applications has polycrystalline drain electrode in window of insulation layer on one side of semiconductor body and gate electrode within insulation layer on its opposite sideInfo
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- DE10056296C1 DE10056296C1 DE10056296A DE10056296A DE10056296C1 DE 10056296 C1 DE10056296 C1 DE 10056296C1 DE 10056296 A DE10056296 A DE 10056296A DE 10056296 A DE10056296 A DE 10056296A DE 10056296 C1 DE10056296 C1 DE 10056296C1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 23
- 238000009413 insulation Methods 0.000 title abstract 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 23
- 238000009792 diffusion process Methods 0.000 claims description 2
- 238000002513 implantation Methods 0.000 claims description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 10
- 230000005669 field effect Effects 0.000 description 6
- 235000012239 silicon dioxide Nutrition 0.000 description 5
- 239000000377 silicon dioxide Substances 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 238000001228 spectrum Methods 0.000 description 1
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- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7812—Vertical DMOS transistors, i.e. VDMOS transistors with a substrate comprising an insulating layer, e.g. SOI-VDMOS transistors
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
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- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7827—Vertical transistors
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- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
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- H10B—ELECTRONIC MEMORY DEVICES
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- H10B12/05—Making the transistor
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- H01L29/0642—Isolation within the component, i.e. internal isolation
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- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41741—Source or drain electrodes for field effect devices for vertical or pseudo-vertical devices
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Abstract
Description
Die vorliegende Erfindung betrifft einen MOS-Niedervolt- (NV-)Vertikaltransistor.The present invention relates to a MOS low-voltage (LV) vertical transistor.
Aus IEEE SPECTRUM August 1999, S. 79, ist ein MOS-Vertikal transistor bekannt, dessen Drain einen Speicherknoten und gleichzeitig Gate eines herkömmlichen Feldeffekttransistors in einer DRAM-Zelle bildet. Andere Beispiele für niederohmige Leistungs-MOS-Feldeffekttransistoren sind HEXFET- und SIPMOS- Strukturen.From IEEE SPECTRUM August 1999, p. 79, is a MOS vertical transistor known, the drain of a storage node and at the same time gate of a conventional field effect transistor forms in a DRAM cell. Other examples of low impedance Power MOS field effect transistors are HEXFET and SIPMOS Structures.
Es ist Aufgabe der vorliegenden Erfindung, einen MOS-Nieder volt-Vertikaltransistor zu schaffen, der sich leicht mit ei nem beliebigen weiteren Substrat verbinden lässt.It is an object of the present invention to provide a MOS low volt vertical transistor to create that easily with egg can connect any other substrate.
Diese Aufgabe wird erfindungsgemäß gelöst durch einen MOS- Niedervolt-Vertikaltransistor mit einem eine erste und eine zweite Hauptoberfläche aufweisenden Halbleiterkörper des ei nen Leitungstyps, in dessen an die erste Hauptoberfläche an grenzenden Bereich eine Sourcezone des anderen, zum einen Leitungstyp entgegengesetzten Leitungstyps eingebracht ist, einer auf der zweiten Hauptoberfläche vorgesehenen und ein Fenster aufweisenden Isolierschicht, wobei das Fenster in ei nem dem Bereich der Sourcezone nicht gegenüberliegenden Ge biet der zweiten Hauptoberfläche vorgesehen ist, einer sich durch das Fenster hindurch erstreckenden Drainelektrode aus polykristallinem Silizium, einem sich unterhalb des Fensters von der zweiten Hauptoberfläche bis zur ersten Hauptoberflä che und berührungsfrei mit der Sourcezone erstreckenden Ge biet des anderen Leitungstyps und einer im Bereich zwischen der Sourcezone und dem Gebiet des anderen Leitungstyps und oberhalb der ersten Hauptoberfläche vorgesehenen Gateelektro de. According to the invention, this object is achieved by a MOS Low-voltage vertical transistor with a first and one second main surface of the semiconductor body of the egg NEN type, in the first main surface bordering one source zone of the other, for one Line type of opposite line type is introduced, one provided on the second main surface and one Window insulating layer, the window in egg Ge not opposite the area of the source zone the second main surface is provided, one itself through the window extending drain electrode polycrystalline silicon, one located below the window from the second main surface to the first main surface surface that extends without contact with the source zone offers the other line type and one in the range between the source zone and the area of the other conduction type and provided gate electrode above the first main surface de.
Das polykristalline Silizium der Drainelektrode besteht in bevorzugter Weise aus einer n+-dotierten polykristallinen Si liziumschicht, da diese relativ einfach mit anderen, beliebi gen Substraten, wie beispielsweise einem weiteren, wenigstens eine Speicherkapazität enthaltenden Halbleiterkörper verbun den werden kann. Dieser weitere Halbleiterkörper kann gegebe nenfalls auch einen weiteren Transistor, wie beispielsweise einen MOS-Lateraltransistor oder einen MOS-Vertikaltransistor aufweisen.The polycrystalline silicon of the drain electrode preferably consists of an n + -doped polycrystalline silicon layer, since this can be connected relatively easily to other substrates, such as another semiconductor body containing at least one storage capacity. This further semiconductor body can optionally also have a further transistor, such as a lateral MOS transistor or a vertical MOS transistor.
Auf der die Drainelektrode bildenden n+-leitenden polykri stallinen Siliziumschicht befindet sich die das Fenster auf weisende Isolierschicht, die in bevorzugter Weise aus Silizi umdioxid besteht. Diese Siliziumdioxidschicht ist mit einem oder auch mehreren, das Fenster bildenden Löchern versehen. Durch dieses Fenster bzw. durch diese Löcher wird ein das Ge biet des anderen Leitungstyps mit der n+-leitenden polykri stallinen Siliziumschicht verbindender Stöpsel ausdiffundiert oder von oben implantiert, wobei dieser Stöpsel den gleichen Leitungstyp wie das Gebiet des anderen Leitungstyps hat.On the n + -conducting polycrystalline silicon layer forming the drain electrode there is the insulating layer facing the window, which preferably consists of silicon dioxide. This silicon dioxide layer is provided with one or more holes forming the window. Through this window or through these holes, a plug connecting the area of the other line type with the n + -type polycrystalline silicon layer is diffused or implanted from above, this plug having the same line type as the area of the other line type.
Oberhalb der Isolierschicht ist bei dem MOS-Niedervolt-Verti kaltransistor eine den Halbleiter bildende Siliziumschicht aufgetragen, in welcher die Sourcezone angeordnet ist.The MOS low-voltage verti is above the insulating layer Kaltransistor a silicon layer forming the semiconductor applied in which the source zone is arranged.
Wenn der erfindungsgemäße MOS-Niedervolt-Vertikaltransistor über seine aus einer polykristallinen Siliziumschicht beste hende Drainelektrode mit einem weiteren Siliziumsubstrat ver bunden wird, das, wie oben erwähnt wurde, eine Speicherkapa zität und gegebenenfalls einen weiteren Transistor erhält, kann er damit in hervorragender Weise für eine DRAM-Speicher zelle eingesetzt werden, welche sich durch einen minimalen Platzbedarf auszeichnet. If the MOS low-voltage vertical transistor about its best of a polycrystalline silicon layer ver drain electrode with another silicon substrate is bound, which, as mentioned above, a memory capa quity and possibly another transistor, it can do an excellent job for a DRAM memory cell, which is characterized by a minimal Characterizes space requirements.
Nachfolgend wird die Erfindung anhand der Zeichnungen näher erläutert. Es zeigen:The invention will be described in more detail below with reference to the drawings explained. Show it:
Fig. 1 eine Schnittdarstellung eines Ausführungsbei spiels des erfindungsgemäßen MOS-Niedervolt- Vertikaltransistors, Fig. 1 is a sectional view of an exemplary embodiment of the invention, game-MOS low-voltage vertical transistor,
Fig. 2 eine Schnittdarstellung durch eine DRAM-Speicher zelle, die den erfindungsgemäßen MOS-Niedervolt- Vertikaltransistor verwendet, Fig. 2 is a section through a cell DRAM memory, using the inventive low-voltage MOS vertical transistor,
Fig. 3 ein Ersatzschaltbild zu der DRAM-Speicherzelle von Fig. 2 und Fig. 3 is an equivalent circuit diagram for the DRAM memory cell of Fig. 2 and
Fig. 4 eine Schnittdarstellung durch ein weiteres Bei spiel einer DRAM-Speicherzelle aus zwei MOS-Nie dervolt-Vertikaltransistoren gemäß der vorliegen den Erfindung. Fig. 4 is a sectional view through another example of a DRAM memory cell made of two MOS Nie dervolt vertical transistors according to the present invention.
Fig. 1 zeigt einen Schnitt durch ein Ausführungsbeispiel des erfindungsgemäßen MOS-Niedervolt-Vertikaltransistors. Fig. 1 shows a section through an embodiment of the MOS low-voltage vertical transistor of the present invention.
Ein p-leitender Halbleiterkörper 1 aus insbesondere Silizium weist in seiner einen Hauptoberfläche 2 eine n+-leitende Zone 3 auf, die ringförmig gestaltet sein kann und Source bildet. Diese Source-Zone 3 ist mit einer Source-Kontaktschicht 4 aus Metall, wie beispielsweise Aluminium, oder aus n+-leitendem polykristallinem Silizium verbunden und an eine Sourceelek trode S angeschlossen. Weiterhin ist auf der Hauptoberfläche 2 im Bereich oberhalb des Halbleiterkörpers 1 eine Isolier schicht 5 aus beispielsweise Siliziumdioxid vorgesehen, in die eine Gateelektrode 6 bzw. G aus n+-leitendem polykristal linem Silizium eingelagert ist. Im Halbleiterkörper 1 befin det sich unterhalb der Gateelektrode 6 und im Abstand von der Sourcezone 3 ein n-leitendes Gebiet 7, das sich von der einen Hauptoberfläche 2 bis zu einer dieser gegenüberliegenden Hauptoberfläche 8 des Halbleiterkörpers 1 erstreckt. Auf der Hauptoberfläche 8 ist eine weitere Isolierschicht 9 aus bei spielsweise Siliziumdioxid vorgesehen, in welcher sich ein durch wenigstens ein Loch gebildetes Fenster 10 befindet, das mit einem n+-leitendem Stöpsel 11 aus polykristallinem Sili zium gefüllt ist. Dieser Stöpsel 11 verbindet das n-leitende Gebiet 1 mit einer auf der Isolierschicht 9 vorgesehenen n+- leitenden polykristallinen Siliziumschicht 12, welche eine Drainelektrode D darstellt. Die Dotierung des Stöpsels 11 er folgt durch Ausdiffusion von n-leitendem Fremdstoff aus der polykristallinen Siliziumschicht 12 oder durch Implantation, bevor auf der Isolierschicht 9 beispielsweise durch "Smart Cut" der Halbleiterkörper 1 aufgetragen wird.A p-type semiconductor body 1 made in particular of silicon has in its one main surface 2 an n + -conducting zone 3 which can be designed in a ring shape and forms a source. This source zone 3 is connected to a source contact layer 4 made of metal, such as aluminum, or of n + -conducting polycrystalline silicon and connected to a source electrode S. Furthermore, an insulating layer 5 made of, for example, silicon dioxide is provided on the main surface 2 in the area above the semiconductor body 1 , into which a gate electrode 6 or G made of n + -conducting polycrystalline silicon is embedded. In the semiconductor body 1 is underneath the gate electrode 6 and at a distance from the source zone 3, an n-type region 7 , which extends from one main surface 2 to a main surface 8 of the semiconductor body 1 opposite this. On the main surface 8 , a further insulating layer 9 is provided from, for example, silicon dioxide, in which there is a window 10 formed by at least one hole, which is filled with an n + -conducting plug 11 made of polycrystalline silicon. This plug 11 connects the n-type region 1 to an n + -type polycrystalline silicon layer 12 which is provided on the insulating layer 9 and which represents a drain electrode D. The plug 11 is doped by diffusion of n-conducting foreign matter from the polycrystalline silicon layer 12 or by implantation before the semiconductor body 1 is applied to the insulating layer 9, for example by "smart cut".
Der erfindungsgemäße MOS-Niedervolt-Vertikaltransistor lässt sich auf einfache Weise mit anderen, beliebigen Substraten verbinden, was auf die "unten" liegende, n+-leitende polykri stalline Siliziumschicht 12 zurückzuführen ist. Dies soll im folgenden anhand der Fig. 2 und 4 für eine DRAM-Speicherzelle noch näher erläutert werden.The MOS low-voltage vertical transistor according to the invention can be connected in a simple manner to any other desired substrates, which can be attributed to the "bottom", n + -conducting polycrystalline silicon layer 12 . This will be explained in more detail below with reference to FIGS. 2 and 4 for a DRAM memory cell.
Fig. 2 zeigt eine DRAM-Speicherzelle, bei der der MOS-Nieder volt-Vertikaltransistor des Ausführungsbeispiels von Fig. 1 auf einem Lateral-Feldeffekttransistor mit einem p--leitenden Halbleiterkörper 14 und n-leitenden Source- bzw. Drainzonen 15, 16 sowie einer Isolierschicht 17 aus Siliziumdioxid ange ordnet ist. Die polykristalline Siliziumschicht 12 befindet sich dabei auf der Isolierschicht 17, so dass sie eine Gate elektrode für diesen Lateral-Feldeffekttransistor bildet und gleichzeitig Speicherkapazitäten C1 und C2 aus jeweils der n+-leitenden polykristallinen Siliziumschicht 12 und der n- leitenden Zone 15 bzw. der n-leitenden Zone 16 entstehen, bei denen das Dielektrikum aus der Isolierschicht 17 gebildet wird. Die Sourcezone 15 liegt auf Ground, während die Drain zone 16 einerseits über einen Widerstand R mit einem Versorgungspotential von beispielsweise +3 V beaufschlagt und an dererseits mit einem Leseverstärker SA verbunden ist. Fig. 2 shows a DRAM memory cell in which the MOS low-voltage vertical transistor of the embodiment of Fig. 1 on a lateral field effect transistor with a p - -type semiconductor body 14 and n-type source or drain zones 15 , 16 and an insulating layer 17 made of silicon dioxide is arranged. The polycrystalline silicon layer 12 is located on the insulating layer 17 , so that it forms a gate electrode for this lateral field-effect transistor and at the same time storage capacities C1 and C2 each consisting of the n + -conducting polycrystalline silicon layer 12 and the n -conducting zone 15 and N-type zones 16 are formed, in which the dielectric is formed from the insulating layer 17 . The source zone 15 is at ground, while the drain zone 16, on the one hand, is supplied with a supply potential of, for example, +3 V via a resistor R and, on the other hand, is connected to a sense amplifier SA.
Damit bildet die Anordnung von Fig. 2 eine Speicherzelle mit einem MOS-Niedervolt-Vertikaltransistor VMT, der an eine Bit leitung BL, eine Wortleitung WL und über einen Speicherknoten K an die Speicherkapazitäten C1 und C2 sowie den Lateral-MOS- Feldeffekttransistor LMT angeschlossen ist wie dies in einem Ersatzschaltbild für die Anordnung von Fig. 2 in Fig. 3 dar gestellt ist.The arrangement of FIG. 2 thus forms a memory cell with a MOS low-voltage vertical transistor VMT, which is connected to a bit line BL, a word line WL and, via a storage node K, to the storage capacitances C1 and C2 and the lateral MOS field-effect transistor LMT as shown in an equivalent circuit diagram for the arrangement of FIG. 2 in FIG. 3.
Fig. 4 zeigt ein weiteres Beispiel einer Speicherzelle mit dem erfindungsgemäßen MOS-Niedervolt-Vertikaltransistor, der hier aber im Gegensatz zum Beispiel von Fig. 2 mit einem wei teren MOS-Niedervolt-Vertikaltransistor VMT' anstelle des La teral-Feldeffekttransistors LMT versehen ist. Dieser weitere MOS-Niedervolt-Vertikaltransistor VMT' ist in ähnlicher Weise aufgebaut wie der Vertikaltransistor VMT und weist anstelle der polykristallinen Siliziumschicht 12 als Kontaktzone für Drain einen n+-leitenden Bereich 18 auf, der einerseits an den Leseverstärker SA und andererseits über den Widerstand R an eine Versorgungsspannung von etwa +3 V angeschlossen ist. Die n+-leitende Sourcezone 3' ist zusammen mit dem p- leitenden Halbleiterkörper 1' geerdet, während Source durch das n-leitende Gebiet 7' gebildet ist. Fig. 4 shows a further example of a memory cell with the MOS low-voltage vertical transistor according to the invention, which, however, in contrast to the example of Fig. 2 is provided with a white direct MOS low-voltage vertical transistor VMT 'instead of the La teral field effect transistor LMT. This further MOS low-voltage vertical transistor VMT 'is constructed in a similar manner to the vertical transistor VMT and instead of the polycrystalline silicon layer 12 as a contact zone for drain has an n + -conducting region 18 which is connected to the sense amplifier SA on the one hand and via the resistor R on the other hand is connected to a supply voltage of approximately +3 V. The n + -type source zone 3 'is grounded together with the p-type semiconductor body 1 ', while the source is formed by the n-type region 7 '.
Bei den Ausführungsbeispielen der Fig. 2 und 4 besteht die Source-Kontaktschicht 4 in bevorzugter Weise aus n+-leitendem polykristallinem Silizium. Es ist aber auch möglich, anstelle von diesem n+-leitendem polykristallinem Silizium ein Metall, wie insbesondere Aluminium, vorzusehen.In the exemplary embodiments in FIGS . 2 and 4, the source contact layer 4 preferably consists of n + -conducting polycrystalline silicon. However, it is also possible to provide a metal, such as in particular aluminum, instead of this n + -conducting polycrystalline silicon.
Die angegebenen Leitungstypen können ohne weiteres auch umge kehrt werden. In diesem Fall ist beispielsweise der Halblei terkörper 1 bzw. 1' n-leitend, während dann das Gebiet 7 bzw. 7' p-leitend ist. Entsprechendes gilt auch für die übrigen Gebiete des Halbleiterkörpers.The specified line types can also be easily reversed. In this case, for example, the semiconductor body 1 or 1 'is n-conductive, while the region 7 or 7 ' is then p-conductive. The same applies to the other areas of the semiconductor body.
Schließlich kann für den Halbleiterkörper anstelle von Sili zium auch ein anderes Material, wie beispielsweise Silizium carbid, verwendet werden. Auch ist die Erfindung nicht auf die Anwendung auf eine Speicherzelle beschränkt. Vielmehr kann der erfindungsgemäße MOS-Niedervolt-Vertikaltransistor immer dann besonders vorteilhaft eingesetzt werden, wenn er mit seiner polykristallinen Siliziumschicht 12 auf einem wei teren Halbleiterkörper gestapelt werden soll. Finally, another material, such as silicon carbide, can be used for the semiconductor body instead of silicon. The invention is also not restricted to use on a memory cell. Rather, the MOS low-voltage vertical transistor according to the invention can always be used particularly advantageously when it is to be stacked with its polycrystalline silicon layer 12 on a white semiconductor body.
11
p-leitender Halbleiterkörper
p-type semiconductor body
22
obere Hauptoberfläche
upper main surface
33
n+ n +
-leitende Sourcezone
conductive source zone
44
Source-Kontaktschicht
Source contact layer
55
Isolierschicht
insulating
66
Gateelektrode
gate electrode
77
n-leitendes Gebiet
n-type area
88th
untere Hauptoberfläche
lower main surface
99
Isolierschicht
insulating
1010
Fenster
window
1111
n+ n +
-leitender Stöpsel
- conductive plug
1212
polykristalline Siliziumschicht
polycrystalline silicon layer
1313
Isolierschicht
insulating
1414
weiterer Halbleiterkörper
further semiconductor body
1515
weitere Sourcezone
further source zone
1616
weitere Drainzone
another drain zone
1717
Isolierschicht
insulating
1818
n+ n +
-leitendes Kontaktgebiet
R Widerstand
SA Leseverstärker
G Gateelektrode
S Sourceelektrode
D Drainelektrode
BL Bitleitung
WL Wortleitung
VMT, VMT' MOS-Vertikaltransistor
LMT MOS-Lateraltransistor
-leading contact area
R resistance
SA sense amplifier
G gate electrode
S source electrode
D drain electrode
BL bit line
WL word line
VMT, VMT 'MOS vertical transistor
LMT MOS lateral transistor
Claims (10)
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE10056296A DE10056296C1 (en) | 2000-11-14 | 2000-11-14 | MOS vertical transistor for LV applications has polycrystalline drain electrode in window of insulation layer on one side of semiconductor body and gate electrode within insulation layer on its opposite side |
PCT/DE2001/004005 WO2002041403A2 (en) | 2000-11-14 | 2001-10-19 | Mos low-voltage vertical transistor |
TW090128190A TW529177B (en) | 2000-11-14 | 2001-11-14 | MOS low-voltage vertical transistor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE10056296A DE10056296C1 (en) | 2000-11-14 | 2000-11-14 | MOS vertical transistor for LV applications has polycrystalline drain electrode in window of insulation layer on one side of semiconductor body and gate electrode within insulation layer on its opposite side |
Publications (1)
Publication Number | Publication Date |
---|---|
DE10056296C1 true DE10056296C1 (en) | 2002-02-07 |
Family
ID=7663189
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE10056296A Expired - Fee Related DE10056296C1 (en) | 2000-11-14 | 2000-11-14 | MOS vertical transistor for LV applications has polycrystalline drain electrode in window of insulation layer on one side of semiconductor body and gate electrode within insulation layer on its opposite side |
Country Status (3)
Country | Link |
---|---|
DE (1) | DE10056296C1 (en) |
TW (1) | TW529177B (en) |
WO (1) | WO2002041403A2 (en) |
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JP2021108331A (en) * | 2019-12-27 | 2021-07-29 | キオクシア株式会社 | Semiconductor memory |
Family Cites Families (3)
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DE3477102D1 (en) * | 1984-04-25 | 1989-04-13 | Siemens Ag | One-transistor memory cell for high-density integrated dynamic semiconductor memories, and method for manufacturing the same |
JPS6193669A (en) * | 1984-10-15 | 1986-05-12 | Nec Corp | Semiconductor element |
JPS6231176A (en) * | 1985-08-02 | 1987-02-10 | Sharp Corp | Laminated semiconductor device |
-
2000
- 2000-11-14 DE DE10056296A patent/DE10056296C1/en not_active Expired - Fee Related
-
2001
- 2001-10-19 WO PCT/DE2001/004005 patent/WO2002041403A2/en active Application Filing
- 2001-11-14 TW TW090128190A patent/TW529177B/en not_active IP Right Cessation
Non-Patent Citations (1)
Title |
---|
IEEE Spectrum, Aug. 1999, p. 79 * |
Also Published As
Publication number | Publication date |
---|---|
WO2002041403A3 (en) | 2002-12-05 |
TW529177B (en) | 2003-04-21 |
WO2002041403A2 (en) | 2002-05-23 |
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