TW529167B - Dual transistor SRAM cell and its operation method - Google Patents

Abstract

A dual transistor SRAM cell and its operation method are introduced. This SRAM cell has a first transistor, a second transistor, a first capacitor and a second capacitor. The first transistor has a first terminal, a second terminal and a gate terminal. The first terminal is coupled to the first bit line and the gate terminal is coupled to the word line. The first capacitor has a first terminal and a second terminal. The first terminal of the first capacitor is coupled to the second terminal of the first transistor and the second terminal of the first capacitor is coupled to the substrate bias. The second transistor has a first terminal, a second terminal and a gate terminal. The first terminal of the second capacitor is coupled to the second bit line and the gate terminal of the second capacitor is coupled to the word line. The second capacitor has a first terminal and a second terminal. The first terminal of the second capacitor is coupled to the second terminal of the second transistor and the second terminal of the second capacitor is coupled to the substrate bias.

Description

529167

529167 V. Description of the invention (2) The cell size of the electric crystal cells is about 10 to 16 times as large as that of the memory. Therefore, 'this method is not possible', and because: Sixth, the cost is more expensive. In addition, compared with i: i technology, it also progresses, the components of the early area increase, and the overall leakage of Tian Yicai's static random access memory when it is turned off (Stand by Current). "Living memory" phenomenon. Compared with T, when using two: J :: "off: cells, although the cell size of the memory cell is reduced, the σ H_ body has a higher recorded voltage (power supply voltage plus electricity: 2 :: You must use electrical voltage (threshold voltage)). The more electric charges stored in the starting body of the electric motor, the more it can prevent the storage of the capacitor. (1 eak), so that the data can be preserved. " In view of this, the omission of the charge in the valley is in accordance with the present invention. The present invention accesses the memory cell, using the traditional static ^ A, using two transistors to follow the static memory access dynamics :: access to the memory cell and static Compared with the random small cell size, which is 5 times lower than that of Prince Edward, it has dots. Therefore, the two i Φ ϊ charging voltage and the small standby current are superior to the current static random storage; the static random access memory cell of f should be desirable for the industrial use of the present invention. Static random access #Two types of static random access memory cells with two transistors. The capacitor and the second cell include the first transistor, the second transistor, and the first and second connection terminal valleys. Among them, the first transistor has a first connection terminal, a bit line, a first gate, a terminal, and a first connection terminal of the first transistor is coupled to the first remote terminal of a transistor. Character lines. The first capacitor is connected to the second capacitor. First connecting end handle of first capacitor

529167

529167 V. Description of the invention (4) The source supply voltage switches the cell substrate voltage to memorize the state before the cell reads. As mentioned above, the present invention uses two dynamics to store in two dynamic random access memory cells and sub-fetch memory cells. At the same time, as the basis for writing data values, and: After the voltage is de-energized, the charge voltage in the capacitor will charge and drop the Jingye Sutian Fan line in advance to determine the value of the read data: ^, ,, ^ Whether the voltage is pulled, small charging dust, low reserve , ☆ Wu Ming has small cell utilization benefits. Therefore, two batteries are used for this purpose: 髀 „The other industries of the book should be able to replace the current static random access memory, the random access memory cell label, and jg 圮 memory cell. 1 0 0: Cell 101, 105: NMOS transistor 103, 107: Capacitor BL: First bit line BLB: Second bit line WL: Word line SN1 ································· The first storage node SN2: the second storage node. The first picture of the static bear random access 4 is a simple circuit diagram of a memory cell 100 and a second cell according to a preferred embodiment of the present invention. The static random access m and m are both lightly connected & 03, 107. Among them, the NM0S transistor is not connected to the element line WL, the NMOS transistor 101, 105

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Page 8 529167 V. Description of the invention (5) The first connection terminals are respectively coupled to the first bit line.

The NMOS transistor 101, 105 is complicated _ brother one wire BLB ground) ~ = ,,, field cell substrate (CeU plate) voltage VCP (usually it is the first bit line BL for prostitutes) The other end of the second bit line BLB is coupled to a sense amplifier. In the comparative example, the method of writing and reading the cell 100 will be connected from L to the ± Rayleigh cell 100 in the writing mode. , The voltage on the word line WL

Sherlock Leimau vnifGN ^ is switched to this static random access memory supply II ,, ^, (if designed with a dynamic random access memory cell, the character line WL ^, is switched to supply power voltage VDD + dynamic random Access the initial voltage of the transistor in the memory cell (threshold v0ltage)). The voltages on the first and second bit lines BLB are respectively supplied with the power supply voltage vdd or the ground voltage 根据 according to the data to be written (shell material 0 or shell material 1). For example, please refer to both the magic map and the second diagram. Among them, the second diagram shows the best practice according to the present invention; taking notes, writing the timing diagram of the capital on the cell. When you want to write: ;; == the voltage on the sub-element line WL on the 1st day is boosted to the supply voltage VDD by the ground voltage ⑽ ^, and the voltage on the first bit line BL is determined by the ground voltage GND is pushed up to the supply voltage VDD, and the voltage on the second bit line is pulled down from the supply voltage VDD to the ground voltage GND. In this case, if you are familiar with this technique f, you can see that the NMOS transistor ΐ (π is on), the capacitor 103 starts to store charge, and according to the voltage change on the first bit line BL, the capacitor The charge voltage (the voltage of the first storage node SN1) is increased from the ground voltage to the supply voltage VDD minus the initial voltage V1 of the NM0S transistor. 〇1 ^

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V. Description of the invention (6) (VDD — VTN). As for the NMOS transistor 105, it is also turned on. The voltage on the second bit line BLB changes. The voltage stored in the capacitor (the voltage of the second storage node SN2) is drawn from 〇]) — VTN. Drop to voltage GND. The voltage on the word line WL is pushed up to the supply voltage vdd — after a period of time, the supply voltage VDD is then pulled down to the ground voltage GND to turn off the NMOS transistor 1 01, 1 05, and it is retained. The charge stored in the six devices 10 3, 107. This completes the work of writing data into cells. In the same way, you can understand the movement of the cell 丨 〇〇 writing data 〇. When the cell 100 is in the reading mode, the voltages on the first bit line BL and the second bit line BLB are precharged and balanced to the supply voltage dd. The voltage on the word line WL will still be switched from the ground voltage GND to the supply voltage VDD. Please refer to FIG. 1 and FIG. 3 at the same time. Among them, FIG. 3 is a timing diagram of reading the lean material 1 in the static random access memory cell according to the preferred embodiment of the present invention. When reading data i, the voltages on the first bit line and the second bit fBLB are controlled by the sense amplifier. When the sense amplifier is enabled by induction (when the induced voltage is the ground voltage GND), it is precharged. And balanced to the supply voltage VDD. Next, the voltage on the word line WL is switched from the ground voltage GND to the supply voltage Dp. At this time, both the NMOS transistor 101 and the NMOS transistor 105 are turned on. The voltage is VDD_VTN. Because of &, the voltage on the first bit line = voltage will still be the supply voltage VDD. On the contrary, since the voltage of the second storage f = point SN2 is the ground voltage GND, and the electricity on the second bit line blb needs to be evenly distributed, when the capacitor 107 starts to accept the second bit line BLB, When the charge is charged, the voltage on the second bit line will be pulled down to 529167 by the 529167 V. Invention description (7), and the last voltage stored by the second storage node SN2 will be The charge amount of the element line BLB is insufficient when it is pre-charged, and stays slightly below VDD ~ VTN. During the period when the voltage of the first storage node SN1 is VDD_VTN and the gas voltage of the second storage node SN2 is slightly lower than VDD-VTN, the sense amplifier is enabled to sense the voltages on the first bit line BL and the second bit line πβ. . Inductive amplification state, the difference between the voltage on the first bit line (supply power supply voltage) and the voltage on the second bit line BLB (slightly lower than the supply power voltage) at the time of induction. The data is data 丨. When the inductive amplification recognizes that the cell 1 00 is stored at this time as the data i, the sense amplifier is disabled, and its induced enable voltage is switched from the ground voltage GND to the power supply voltage VDD. This is the potential on the first bit line 虬 and the second bit line BLB, which are coupled to them, and are respectively maintained at the supply voltage VDD and pulled down to the ground voltage GND. The charge voltages stored in the capacitors 103 and 107 are therefore It is maintained at VDD-VTN and pulled down to the ground voltage GND, that is, the voltages of the first storage node SN1 and the second storage node SN2 are restored to the voltages when reading has not started. Finally, the voltage on the word line 叽 is supplied by the power The voltage VDD is switched to the ground voltage GND, the NMOS transistor 101, 105 is turned off, and the charge stored in the capacitors 103 and 107 is retained, and the point f between SN1 and the second storage node SN2 is retained. When unread The voltage above. ^ = 成 = cell 1 0 0 to read data 1. The same way, you can also understand the action of cell 1000 to read data 0. In addition, the sense amplifier follows the electrical line on the word line 覆. It is switched to the ground voltage ⑽!), And the induction is enabled, that is, the first bit line BL u and the second bit line BLB are precharged and balanced to the supply voltage.

I 9040 twf ptLi Page 11 529167 V. Description of the invention (8) VDD to read the next cycle cell j In summary, the present invention provides a static random access memory cell for the fe cell to access the storage stored in the capacitor in the memory cell. Basis for obtaining information. Therefore, the present invention uses a two-electron crystal as a method, in addition to having a small cell ruler because this cell has fewer components, is small, and the actual cost is low, and other random access memory cells are used in the industry. Jiashi limited the present invention. Anyone familiar with this technique = within the scope, can be used as a variety of changes 1 has been included in the attached patent application 00 is stored-a kind of, and its charge compared to the static inch, charge Has advantages. use. Exemplified by the artist, move and run the data in the boundary. With two dynamic use methods, the voltages are different, and the static leakage current is low. The overall leakage current is low, so it should be exposed as above, but it will not depart from the decoration, so this will prevail. Random access In addition to the advantages of dynamic random writing or memory access to the memory cell and its operational advantages, the smaller, ready to replace the current static, it is not the protection of the spirit of the invention.

Page 529167 Brief description of the drawings In order to make the above and other objects, features, and advantages of the present invention more comprehensible, the preferred embodiments are described below in detail with the accompanying drawings, as follows: Brief description: Figure 1 shows a simple circuit diagram of a static random access memory cell according to a preferred embodiment of the present invention; Figure 2 shows a static random access memory according to a preferred embodiment of the present invention The clock diagram of the memory cell at the time of writing data 1; and FIG. 3 shows the clock diagram of the data at the time of reading data 1 of the static random access memory cell according to the preferred embodiment of the present invention.

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Claims (1)

529167 ~, patent application scope 1 · A two-electricity-first transistor, and a gate terminal, the second line, the first transistor-first capacitor, a first end of the first capacitor, and a cell bottom of the first capacitor Material electric second transistor, the gate of the second electric body, the second transistor is a second capacitor, the first capacitor with the capacitor is connected to the first capacitor 2 such as access memory 3 A second memory cell line and a second bit of the second application cell, the application cell, the two motor access dynamics follow the cell's bottom line, and its solar cell's static random access memory cell , Having a first connection terminal, mi ^ includes:-an electric connection: ί $ The terminal is coupled to the first connection terminal of the Japanese body-the body, the gate terminal is coupled to a word line; there is a first connection terminal and the first Two connection terminals, one connection terminal is coupled to the first transistor—u ^ one connection voltage connection—the connection terminal transfers the static random access memory blister having a first connection terminal, a second connection terminal, and a first transistor. A connection end is coupled to a second bit line The word line; and a first connecting terminal and a second connection end, connected to the first terminal I connected to the second connecting end Ma of the second transistor is connected to the substrate terminal coupled to the cell voltage. In the static randomness of the two transistors described in the first item of the invention, the first transistor is an NMOS transistor. The static randomness of the two transistors described in item 1 of the scope of interest is that the 5 xuanzhuang one transistor is a nmos transistor. A method for operating a static random access memory cell of a crystal. The memory cell has a first dynamic random access memory cell for mechanical access to the memory cell, wherein the first dynamic random access memory and the second dynamic random access memory cell have common characteristics. A word material voltage and its own / first bit line and an operation method include: 9 () 4 () t \\ i pul Page 14 529167 Sixth, the scope of the patent application When the static random access memory cell writes a piece of data, the voltage is switched from the cell substrate voltage to a power supply electric mule, which is used to supply the cell; the material "and the source to supply electricity The first bit line and the second closing line are empty; the Shifan line, and the voltage of the subfan line is switched by the power supply voltage to the cell substrate voltage. The method for operating a two-transistor machine to access a memory cell according to item 4, wherein the cell substrate voltage is 1 to ground voltage. 6 · The static random access of the two transistors as described in item 4 of the scope of patent application The operation method of the memory cell, wherein the operation method further includes: ~ When the value to be written is i, the voltage of the first bit line is pushed up to the power source by the thin cell voltage Supply voltage, the voltage of the second bit line is pulled down to the cell substrate voltage from the power supply voltage. 7. Operation method of the static random access memory cell of the two transistors as described in item 4 of the patent application scope , Among which the operation method further includes: When the value of the data to be written is 0, the voltage of the / bit line is pulled down from the power supply voltage to the cell substrate voltage, and the voltage of the second bit line is pushed up by the cell substrate voltage To the power supply voltage. 8. The method for operating a static random access memory cell of two transistors as described in item 6 of the scope of patent application, wherein a first capacitor in the first dynamic random access memory cell is stored in the first capacitor. The voltage is the power supply voltage minus the starting voltage of one of the first crystals in the first dynamic random access memory cell. 9 · The static randomness of the two transistors as described in item 6 of the patent application scope 9040twf ptd Page 15 529167 VI. Operation method of applying patent for accessing memory cell, farming ^ ~~ in the middle-the second capacitor is stored in the memory by dynamic random access memory cell 1 〇 · If the scope of patent application It is the voltage of the substrate of the child. To access the memory cell, 1 = static random voltage of the two transistors described above. /. The voltage of the substrate of the Hai cell is a grounded electric 1 1 · A two-transistor private A method, the static random access memory is treacherous and the memory cell is operated by the operating cell and a second dynamic random storage ^ ς = —The first dynamic random access memory machine accesses the memory cell and the two cells, where the first motion follows a word line and a cell substrate, and the t machine accesses the Ji memory cell in common. -The second bit line, its operation: the method package J has one of each of the -bit lines of the static random access record, including the second line and the second bit line The bit-bit precharges the electricity of the word line to a power supply voltage; the voltage should be switched from the cell substrate voltage to the power supply drop: ί ί 1:70 line and the second bit Whether the voltage of the element line is pulled by the F L slave machine to access the value of the data stored in the memory cell; and after that, the value of the data stored in the static random access memory cell will be pulled down by '1J The voltage of the bit line is reduced to the voltage of the cell substrate; the voltage of the TL line is used to supply power from the power source The cells were switched to base pressure. 12. Static randomness of the two transistors as described in item u of the patent application. The operation method of thinking cell, wherein the cell substrate voltage is a ground () () 4 () Uv! 'Pul 1 3 • The static energy of a two transistor follows her +:, the static random access record, two = the operator accessing the memory cell and the machine accessing the storage: " Cell, where the AND !; line and-cell substrate voltage = ϊίΠΓί have a common bit line, and its operation method includes its own -bit-bit line 5 Hai static random access _ _ &# — ° When I have written a piece of information, I have included: The source supply voltage is changed to the voltage of the 9th line from the cell substrate voltage to-the power supply voltage i :: value position: provide the cell substrate voltage and will The bit line and the second bit line; the cell substrate voltage reads the voltage (power supply voltage) to the detailed static state, and the access memory cell reads the data, including: the first bit line and The second bit of electricity is balanced to the power supply voltage;-the line of electricity is pre-charged to supply electricity; the voltage of the word line is switched from the cell substrate voltage to the electricity according to the first bit line and the first The two bits are pulled down, aged,] the data stored in the static random access memory cell = value;, less After determining the value of the data stored in the static random access memory cell, the voltage of the bit line being pulled down is reduced to the cell substrate voltage; 529167 ^) 040twf ptd Page 18