經濟部智慧財產局員工消費合作社印製 527602 A7 五、發明說明（） 發明領域： 本發明係有關於一種用以感測動態隨機存取記懷體 (Dynamic Random Access Memory ; DRAM)内之電壓的系 統及其應用’特別是有關於在低電壓邏輯製裎（L〇gic Process)的内嵌式（Embedded)動態隨機存取記憶體中，記 憶胞所儲存之電壓的感測系統，用以在低電壓運作時準確 區分記憶胞中所儲存之電壓。 發明背景： 隨機存取記憶體（Random Access Memory; Ram)為一 種揮發性的（Volatile)記憶體，其中動態隨機存取記憶體是 以記憶胞内，電容的帶電荷（Charging)狀態來決定所存放的 數位訊號。請參考第1圖，其所繪示為習知動態隨機存取 記憶體之記憶胞的示意圖。所謂的DRAM的記憶胞1 〇 , 一 般是由金氧半導（MOS)電晶體15和一個電容器20所構 成，位元線（Bit Line)25和字元線（Word Line)30則是藉控 制金氧半導電晶體1 5的啟動與否，以對電容器20進行充 電或放電的動作，達到調整電容器20中所儲存電荷的容 量，進而決定所存放的數位訊號為“ Γ或“ 〇 ” 。 2 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公t ) 1 ¥ w V ------I---1--裝--------訂--------I 1^ (請先閱讀背面之注意事項再填寫本頁) 527602 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（） 當需要從DRAM的記憶胞10内讀取所記錄的資料 時，連接金氧半導電晶體丨5的閘極之字元線3 〇被施以電 壓以啟動金氧半導電晶體15，此時位元線25則切換至感 測放大器（Sense Amplifier)(未繪示），因此DRAM的記憶胞 10中的電容器20將與感測放大器電性連接。感測放大器 將來自電容器20的電壓，和參考電壓值（Reference v〇hage) 作一比較，如此即可決定DRAM的記憶胞1 0中所儲存的 數據為“Γ或“0” 。 由於上述的讀取動作會將原來儲存於Dram的記憶胞 1 0中的資料破獲，因此在讀取後，必須對DRAM的記憶胞 1 0進行充電回復原來儲存的資料。此外，DRAM的記憶胞 1 0中的電容器2 0所儲存的電荷，也會隨著時間而流失， 故也需對DRAM的記憶胞1 〇進行不斷的充電、放電以維 持DRAM中所儲存的數位資料。 雖然DRAM記憶胞1 〇的讀和寫的操作頻繁，而且週 邊迴路（如充放電電路、感測放大器的電路等）的設計也因 而複雜，但是因為每個DRAM記憶胞只需要一個電晶體和 一個電容器，其構造簡單，而且利用高積集度的設計和製 造，可使得DRAM的製造成本降低，而又獲得良好的讀寫 功能’使得 DRAM的應用越來越廣泛，其中内嵌式 (Embedded)DRAM的發展更是迅速。 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -------------^---I----^--------- (請先閱讀背面之注意事項再填寫本頁) 527602 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明（） 内嵌式DRAM主要係設計於多功能的晶片内，如系統 單晶片（System-on-a-Chip ; SoC)，以對晶片中系統提供快 速的服務。由於製程技術的快速進步’一顆晶片中所能容 納的電晶體數目也就隨著迅速增加。為了滿足系統效能的 不斷提高之需求與降低晶片生產的成本，愈來愈多的設計 將數個原本分散在各個晶片的功能整合在一顆晶片中，成 為所謂的系統單晶片。由於系統單晶片的功能越來越多， 也越來越越先進，因此系統單晶片所需要的邏輯製程之内 嵌式DRAM也隨著增加。 為了降低消耗的功率及運作時產生的熱量，大多數的 晶片都在低電壓下運作，所以内嵌式DRAM的運作也在低 電壓下進行，例如在丨5伏特- 〇 5你4主+ 0曰 你U仇将至υ.5伙特之間進行（視電路 設計而定）’而不同於習知DRAM的運作電壓（如3 3伏特 至-1 · 0伏特之間）。 ’ 請同時參考第1圖和第2圖，其中第2圖所緣示為習 =喪式DRAM於運作時記憶胞中電壓對時間的關係圖。 當讀取DRAM的記憶胞丨〇内所記錄 貝布叶日子，位疋線25 被預充電路施以電壓，一妒在，ν，窗从+ ^ 般係以運作電壓範圍75之一丰， 即如第2圖所示之電壓7〇，作Λ讀跑 ^ _ 作為讀取DRAM的記憶胞1〇 内所§己錄的 > 料時的參考電壓。 本纸張尺度適用中國國家標準（CNS)A4^T^_x 297公^ ------ - - - - - - . I I ! I I--^ ---------丨 *· (請先閱讀背面之注意事項再填寫本頁) 527602 Α7 --- Β7 五、發明說明（） -------------裝--- (請先閱讀背面之注意事項再填寫本頁) 如第2圖中所示之記憶胞於讀取時電壓對時間的關 係’係包括讀取記憶胞中儲存的數位訊號為“丨”.，和讀取 記憶胞中儲存的數位訊號為“ 0，，時的兩種情況。首先以讀 取&己憶胞中儲存的數位訊號為“ 1 ”的情況來作說明。在第 一階段60時，位元線25被感測放大器施加參考電壓，如 位元線電壓曲線50所示。同時，記憶胞1 〇中所儲存的電 壓則如記憶胞電壓曲線6 5所示，係位於接近運作電壓範圍 75的最高準位，即電壓55，表示記憶胞中儲存的數位訊號 在第二階段8 0中’由於字元線3 0被施壓，與字元線 3 0電性連接的金氧半導電晶體1 5便啟動，此時位元線2 5 與感測放大益電性連接’因此電容器2 〇便透過已啟動的金 氧半導電晶體1 5和位元線2 5，跟感測放大器電性連接。 由於位元線25和電容器20有一電壓差，所以當兩者電性 連接後，為了達到電壓平衡的目的，電容器2〇的電壓便下 降，即記憶胞1 0的電壓下降，如記憶胞電壓曲線6 5所示， 同時位元線25的電壓上升，如位元線電壓曲線5〇所示。 經濟部智慧財產局員工消費合作社印製 另外，當記憶胞10中儲存的數位訊號為“ 〇，，的情況 時，在第一階段60 ’位元線25被感測放大器施加電壓7〇 作為參考電壓，如位元線電壓曲線8 5所示。而在第一階段 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公t ) 527602 Α7 —-------------g7 __^_ - ----------- 五、發明說明（） 60時’圮憶胞1 〇中所儲存的電壓則如記憶胞電壓曲線9〇 所示，係位於接近運作電壓範圍75的最低準位，即電壓 9 5 ’表示記憶胞中餘存的數位訊號為“ 〇 ’，。 在第二階段80中，由於字元線3〇被施壓.，與字元線 3 0電性連接的金氧半導電晶體丨5便啟動，此時位元線μ 與感測放大器電性連接，因此電容器2〇便透過已啟動的金 氧半導電晶體1 5和位元線25，跟感測放大器電性連接。 由於位元線25和電容器2〇有一電壓差，所以當兩者電性 連接後’為了達到電壓平衡的目的，電容器2〇的電壓便上 升，即記憶胞1 〇的電壓上升，如記憶胞電壓曲線9 〇所示， 同時位元線2 5的電壓下降，如位元線電壓曲線8 5所示。 内嵌式DRAM就是透過感測放大器對參考電壓和記憶胞的 電壓作一比較’得出兩者之間相差的量，來加以區別每個 記憶胞中儲存的數位訊號為“ 1 ”或“ 〇，，。 經濟部智慧財產局員工消費合作社印製 ------------"丨-裝--------訂- 24先閱讀背面之注急事項再填寫本頁) 線 然而因製程參數飄移和元件材料的影響等問題，使得 内欲式dram的記憶胞結構中常因次啟始洩漏 (Subthreshold Leakage)、閘極洩漏（Gate Leakage)和接面洩 漏（Junction Leakge)等而產生洩漏電流，導致内嵌式dram 的記憶胞電壓上升’特別是當記憶胞中健存的數位訊號為 的情況時，對區分記憶胞中儲存的數位訊號為“ r， 或“〇”的過程產生嚴重的影響。尤其在低電壓下運作（如 本紙張尺度適用申國國家標準（CNS)A4規格（210 X 297公t ) 527602 A7 B7 五、發明說明（ 在1 .5伏特至-〇 5 # 4士 ^伏特之間）的内嵌式DRAM，對雷『 化非常敏感，因此淹， 丄 j电壓的變 1:1 /¾漏電流對記憶胞中電容写的 非常嚴重。 σ ^電位影響 "歴1和弟J圖’其中第3圖所繪 知内嵌式DRAMw作時記憶胞中f壓對㈣的關^ 由於當記憶胞10中儲存的數位訊號為“ 1 ” _，電：^ 儲存有大量電荷’所以記憶胞電壓曲線6 5位於接近Γ 壓範…最高準位(即電壓55),並…漏：：：: 很大的影響。伸去4政二 又 1一田兄憶胞1 0中儲存的數位訊號為“ 〇 *r Ζ隐胞電壓曲線^ 〇〇應如冑2圖所示之記憶胞電壓 線9〇’位於接近運作電壓範圍75的最低準位（即電壓95) 但由於受到洩漏電流的影響，使得記憶胞1〇的電壓於第 階段60中往上提升，因此記憶胞電壓曲線1 00往上提升 電壓1 0 5的準位。 --------------裝--------訂. f請先閱讀背面之注音？事項再填寫本頁} 比對第2圖和第3圖，可看出當感測 經濟部智慧財產局員工消費合作社印製 壓範圍75之一半的電壓值7〇作參考電壓，在檢查每個記 憶胞1 0中儲存的數位訊號為“ 〇，，的時候，因位元線電壓 曲線8 5 (即參考電壓曲線）與記憶胞電壓曲線1 〇 〇之間的相 差量’隻小’因此容易出現誤判的結I，將記憶胞i 〇中原來 儲存的數位訊號Π，誤判4 “「…匕可發現，利 用運作電壓範圍75之-半作為參考電壓，以區別每個記憶 線 本紙張尺度適用中國國家標準（CNSM4規格（21G X 297公f ) 527602 A7 B7 五、發明說明（） 胞1 0中儲存的數位訊號為“丨，，或“ 〇，，的習知檢杳方 法，當應用在低電壓運作邏輯製程的嵌入式dram時:未 能提供準確的判斷’使得讀取嵌入式DRAM中儲存的資料 時出現錯亂，影響系統的運作。 發明目的及概述： 蓉於上述之發明背景中，隨著半導體製程的快速發 展’特別是系統單晶片的效能和功用越來越多，所需要的 邏輯製程之内嵌式DRAM也隨著增加。但由於製程參數飄 移和元件材料的影響等問題，使得内嵌式1)11八1^的記憶胞 結構中常會產生泡漏電流，導致内丧式dram的記憶胞電 壓上升，於讀取記憶胞中的數位訊號時容易發生嚴錢錯 亂’讀取的準確度因而下降。而當 曰 、 田円甘欠式DRAM在低電壓 下運作時，洩漏電流產生的影響尤其嚴重。 本發明的主要目的為提供了— ^ ^ ^ 種用以感測動態隨機存 取f憶體内之電壓的系統及其應 ^ ,(J 特別係應用在低電壓 邊輯製程的内嵌式DRAM中，用，、，h 用以k高讀取儲存Dram中 資料時的準確度。利用本發明之 4 ’則動態隨機存取惰· If 内之電壓的系統，可使讀取儲存 子取.己隱體 兔 —. 存於内嵌式DRAM中的資料 時’不谷易受到洩漏電流的影響 的内嵌式DRAM於讀取資料時/解決了低電壓邏輯製程 出現錯亂的問題，進而提 本纸張尺度適用中國國家標準（CNS)A4規格（21〇T^7^^ ------------I-裝—— (請先閱讀背面之沒意事項再填寫本頁) 訂. 〆線丨*丨 經濟部智慧財產局員工消費合作社印製 527602 A7Printed by the Consumers' Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs 527602 A7 V. Description of the invention () Field of the invention: The present invention relates to a method for sensing voltage in a dynamic random access memory (DRAM). System and its application'especially relates to a voltage sensing system stored in a memory cell in an embedded dynamic random access memory of a Low Voltage Logic Process (L0gic Process). Accurately distinguish voltages stored in memory cells during low voltage operation. Background of the invention: Random access memory (Random Access Memory; Ram) is a kind of volatile (Volatile) memory, in which the dynamic random access memory is determined by the charged state of the capacitor in the memory cell. Digital signal stored. Please refer to FIG. 1, which shows a schematic diagram of a memory cell of a conventional dynamic random access memory. The so-called DRAM memory cell 10 is generally composed of metal-oxide-semiconductor (MOS) transistor 15 and a capacitor 20, and the bit line 25 and word line 30 are controlled by The activation of the metal-oxide semi-conductive crystal 15 is to charge or discharge the capacitor 20 to adjust the capacity of the charge stored in the capacitor 20, and then determine whether the digital signal stored is "Γ" or "0". 2 This paper size is applicable to China National Standard (CNS) A4 specification (210 X 297 g t) 1 ¥ w V ------ I --- 1--installation -------- order ---- ---- I 1 ^ (Please read the notes on the back before filling out this page) 527602 A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention () When reading from the DRAM memory cell 10 In the recorded data, the gate zigzag line 3 connected to the metal-oxide semi-conductive crystal 5 is applied with a voltage to start the metal-oxide semi-conductive crystal 15 and the bit line 25 is switched to the sense amplifier (Sense Amplifier) (not shown), so the capacitor 20 in the memory cell 10 of the DRAM will be electrically connected to the sense amplifier. The sense amplifier will The voltage from the capacitor 20 is compared with the reference voltage (Reference v0hage), so that it can be determined whether the data stored in the memory cell 10 of the DRAM is "Γ" or "0". Since the above reading operation will crack the data originally stored in the memory cell 10 of the Dram, after reading, the memory cell 10 of the DRAM must be charged to restore the original stored data. In addition, the charge stored in the capacitor 20 in the DRAM memory cell 10 will also be lost with time. Therefore, the DRAM memory cell 10 needs to be continuously charged and discharged to maintain the digits stored in the DRAM. data. Although the DRAM memory cell 10 has frequent read and write operations, and the design of peripheral circuits (such as the charge and discharge circuit, the circuit of the sense amplifier, etc.) is therefore complicated, each DRAM memory cell requires only one transistor and one Capacitors have a simple structure, and the use of high integration design and manufacturing can reduce the manufacturing cost of DRAM and obtain good read and write functions. 'Make the application of DRAM more and more widespread, of which embedded (Embedded) The development of DRAM is even faster. This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) ------------- ^ --- I ---- ^ -------- -(Please read the notes on the back before filling this page) 527602 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. Description of the invention () Embedded DRAM is mainly designed in multi-function chips, such as system sheets Chip (System-on-a-Chip; SoC) to provide fast service for systems in a chip. Due to the rapid progress of process technology, the number of transistors that can be accommodated in a wafer has also increased rapidly. In order to meet the increasing demand for system performance and reduce the cost of chip production, more and more designs are integrating several functions that were originally distributed in each chip into a single chip to become the so-called system-on-a-chip. As SoCs have more and more functions, and they are more and more advanced, the number of embedded DRAMs in the logic process required for SoCs has also increased. In order to reduce the power consumption and the heat generated during operation, most chips operate at low voltage, so the operation of the embedded DRAM is also performed at low voltage, such as 丨 5 Volts-〇5 you 4 main + 0 Say you will be between U. 5 and 5 (depending on the circuit design) 'and is different from the operating voltage of the conventional DRAM (such as between 3 3 volts--1 · 0 volts). ’Please refer to Figure 1 and Figure 2 at the same time. The relationship between Figure 2 and Figure 2 shows the relationship between voltage and time in memory cells during operation of DRAM. When reading the Bebe leaf days recorded in the memory cell of the DRAM, the bit line 25 is applied with a voltage by the pre-charging circuit. Once jealous, ν, the window from + ^ is generally one of the operating voltage range 75. That is, as shown in FIG. 2, the voltage 70 is used as Λ read run ^ _ as the reference voltage when reading the § recorded in the memory cell 10 of the DRAM. This paper size applies Chinese National Standard (CNS) A4 ^ T ^ _x 297 male ^ -------------. II! I I-^ --------- 丨 * · (Please read the precautions on the back before filling this page) 527602 Α7 --- Β7 V. Description of the invention () ------------- Installation --- (Please read the notes on the back first Please fill in this page again) The voltage-time relationship of the memory cell during reading as shown in Figure 2 includes the reading of the digital signal “丨” stored in the memory cell and the storage of the digital signal stored in the memory cell. There are two cases when the digital signal is "0,". Firstly, the case where the digital signal stored in the & memory cell is "1" will be described. In the first stage at 60, the bit line 25 is The reference voltage is applied by the sense amplifier, as shown by the bit line voltage curve 50. At the same time, the voltage stored in the memory cell 10 is shown as the memory cell voltage curve 65, which is near the highest level of the operating voltage range 75 , That is, voltage 55, indicates that the digital signal stored in the memory cell in the second stage 8 0 'because the word line 30 is pressed, the metal-oxide semi-conductive crystal 15 electrically connected to the word line 30 is turned on. At this time, the bit line 2 5 is electrically connected to the sense amplifier, so the capacitor 2 0 is electrically connected to the sense amplifier through the activated metal-oxide semi-conductive crystal 15 and the bit line 25. There is a voltage difference between the element line 25 and the capacitor 20, so when the two are electrically connected, in order to achieve the purpose of voltage balance, the voltage of the capacitor 20 drops, that is, the voltage of the memory cell 10 drops, such as the voltage curve of the memory cell 6 5 As shown, the voltage of bit line 25 rises at the same time, as shown by the bit line voltage curve 50. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs In addition, when the digital signal stored in the memory cell 10 is "0 ,, In this case, in the first stage, the bit line 25 is applied with a voltage 70 by the sense amplifier as a reference voltage, as shown in the bit line voltage curve 85. And in the first stage, this paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 male t) 527602 Α7 —------------- g7 __ ^ _------ ------ V. Description of the invention () At 60 o'clock, the voltage stored in the memory cell 10 is as shown in the memory cell voltage curve 90, which is at the lowest level near the operating voltage range 75, that is, the voltage 9 5 'indicates that the remaining digital signal in the memory cell is "0". In the second stage 80, since the word line 30 is pressed, the metal-oxygen semiconducting electrically connected to the word line 30 The crystal 5 is activated. At this time, the bit line μ is electrically connected to the sense amplifier, so the capacitor 20 is electrically connected to the sense amplifier through the activated metal-oxide semi-conductive crystal 15 and the bit line 25. Because there is a voltage difference between the bit line 25 and the capacitor 20, when the two are electrically connected, in order to achieve the purpose of voltage balance, the voltage of the capacitor 2 rises, that is, the voltage of the memory cell 10 rises, such as the voltage of the memory cell Curve 90 is shown, and at the same time, the voltage of bit line 25 is decreased, as shown by bit line voltage curve 85. Embedded DRAM is through Sense amplifier reference voltage and the voltage of the memory cell for a more 'an amount of a phase difference between the two stars, each of the memory cells to be distinguished stored digital signal is "1" or "square ,,. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs ------------ " 丨 -Pack -------- Order- 24 Read the urgent matters on the back before filling in this page) However, due to problems such as process parameter drift and the influence of component materials, the memory cell structure of the internal desire type often has subthreshold leaks, gate leaks, and junction leaks. Leakage current is generated, which causes the voltage of the memory cell of the embedded dram to rise, especially when the digital signal stored in the memory cell is "," to distinguish the digital signal stored in the memory cell as "r," or "〇". The process has a serious impact. Especially when operating at low voltage (such as the application of the national standard (CNS) A4 specification (210 X 297 g t) of this paper size) 527602 A7 B7 V. Description of the invention (in 1.5 volts to -〇 5 # 4 (between ^ ^ volts) of embedded DRAM, very sensitive to lightning, so flooding, 丄 j voltage change 1: 1 / ¾ leakage current is very serious to write capacitance in the memory cell. Σ ^ potential Impact " 歴 1 and younger J picture 'of which the embedded DRAM operation shown in the third picture The relationship between f pressure and ㈣ in the memory cell ^ Because the digital signal stored in the memory cell 10 is "1" _, electricity: ^ has a large amount of charge stored, so the voltage curve of the memory cell 6 5 is located near the Γ pressure range ... the highest accuracy Bit (that is, voltage 55), and ... leakage :::: Great influence. The digital signal stored in the 4th, second, and 1th brother Tian Yiyi 10 is "〇 * r ZZ hidden voltage curve ^ 〇 〇 The memory cell voltage line 90 ′ should be near the lowest level of the operating voltage range 75 (ie, voltage 95) as shown in Figure 2. However, due to the influence of the leakage current, the voltage of the memory cell 10 is at stage 60. It rises from the middle, so the memory cell voltage curve 1 00 rises up the voltage 1 0 5 level. -------------- Installation -------- Order. F Please Read the phonetic on the back? Matters and then fill out this page} Comparing Figure 2 and Figure 3, you can see that when sensing the voltage value of one-half and one-half of the voltage range 75 printed by the Intellectual Property Bureau's Consumer Cooperatives of the Ministry of Economic Affairs for reference Voltage, when checking that the digital signal stored in each memory cell 10 is "0,", the bit line voltage curve 8 5 (that is, the reference voltage curve) and The phase difference between the memory cell voltage curve '100' is only small, so it is prone to misjudged junction I. The digital signal originally stored in memory cell i 0 is misjudged 4 "" ... can be found by using the operating voltage range 75-half is used as a reference voltage to distinguish each memory line. The paper size applies Chinese national standards (CNSM4 specification (21G X 297 male f)) 527602 A7 B7 V. Description of the invention () The digital signal stored in cell 10 is “丨 ,, or "〇 ,," a conventional inspection method, when applied to embedded dram of low-voltage operation logic process: failed to provide accurate judgment 'makes the reading of data stored in embedded DRAM confused, Affect the operation of the system. Object and Summary of the Invention: In the above background of the invention, with the rapid development of semiconductor processes, especially the efficiency and functions of system-on-a-chips, the number of embedded DRAMs required for logic processes has also increased. However, due to problems such as process parameter drift and the influence of component materials, the embedded cell structure often causes bubble leakage current, which causes the voltage of the memory cell of the internal dram to rise, which can be used to read the memory cell. When digital signals in the medium are prone to severe money confusion, the accuracy of reading is reduced. And when the Tian Tian Gan owing DRAM operates at low voltage, the impact of leakage current is particularly serious. The main purpose of the present invention is to provide a system for sensing the voltage in the dynamic random access f memory and its application. (J is especially an embedded DRAM applied to the low-voltage side-programming process. In, use ,,, h for k-high accuracy in reading and storing data in the Dram. Using the 4 'system of the present invention to dynamically access the voltage in the lazy · If, the read storage can be taken. Hidden Hidden Rabbit—When storing data in embedded DRAM, 'embedded DRAM that is not susceptible to leakage current when reading data / solves the problem of disorder in the low-voltage logic process, and further reduces the cost The paper size applies the Chinese National Standard (CNS) A4 specification (21〇T ^ 7 ^^ ------------ I-packed) (Please read the unintentional matter on the back before filling this page ) Order. 〆 Line 丨 * 丨 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 527602 A7
五、發明說明（ 升讀取資料的準確度。 根據以上所述之目的，本發明提供了一 里用以感測動 態隨機存取記憶體内之電壓的系統及其應用。藉配置、7 的電晶體與内嵌式dram中的記憶胞網路雷 ^ “ f生連接，以及 將參考電壓提升至運作電壓範圍之最高電壓值，冬# 憶胞網路中的任一記憶胞時，同時啟動對應的 2取。己 包日日體，將 參考電壓降低，藉以使得當記憶胞儲存“ π υ的數位訊號 時，參考電壓比記憶胞電壓高，當記憶胞儲 1 的數位 訊號時，參考電壓比記憶胞電壓低，透過增益電路的放大 便可準確獲知記憶胞儲存的數位訊號，解決了低電壓邏輯 製程的内欲式dram於讀取資料時常出現錯亂的問題。 圖式簡單說明： 本發明的較佳實施例將於往後之說明文字中輔以下列 圖形做更詳細的闡述，其中： 第1圖係繪示為習知一種動態隨機存取記憶胞的示意 --------------裝--------訂. (請先閱讀背面之注音？事項再填寫本頁) 線 圖 經濟部智慧財產局員工消費合作社印製 第2圖係繪示為對習知内嵌式DRAM的記憶胞進行讀 取時之電壓對時間的關係圖。 第3圖係繪示為習知内嵌式DRAM於運作時記憶胞中 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 527602 經濟部智慧財產局員工消費合作社印製 15 金 氧 半 導 電 晶 體 25 位 元 線 50 位 元 線 電 壓 曲 線 60 第 一 階 段 70 電 壓 80 第 二 階 段 90 記 憶 胞 電 壓 曲 線 A7 B7 五、發明說明（） 電壓對時間的關係圖。 第4圖係繪示為本發明之一實施例的内嵌式DRAM記 憶胞的配置示意圖。 第5圖係繪示為本發明之一實施例的感測放大器的電 路示意圖。 第6圖係繪示為對根據第4圖的記憶胞進行讀取時之 電壓對時間的關係圖。 第7圖係繪示為對根據第4圖的記憶胞進行讀取時之 電壓對時間的關係圖。 第8圖係繪示為本發明之一實施例的内嵌式DRAM細 胞網路和感測放大器連接的示意圖。 第9圖係繪示為根據第6圖和第7圖而得到之内嵌式 DRAM於運作時記憶胞中電壓對時間的關係圖。 圖號對照說明： 10 記憶胞 20 電容器 30 字元線 55 電壓 65 記憶胞電壓曲線 75 運作電壓範圍 85 位元線電壓曲線 10 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -------------裝·--------訂·---------線 (請先閱讀背面之注意事項再填寫本頁) 527602 A7 B7 五、發明說明（） 經濟部智慧財產局員工消費合作社印製 95 電 壓 100 t己 憶 胞 電 壓 曲 線 105 電 壓 199 1己 憶 胞 網 路 201 1己 憶 胞 203 位 元 線 205 字 元 線 207 記 憶 胞 209 位 元 線 21 1 字 元 線 250 感 測 放 大 器 252 選 擇 電 路 254 增 益 電 路 256 預 充 電 電 路 258 降 壓 電 路 260 致 能 線 262 致 能 線 264 等 位 致 能 線 266 電 晶 體 268 電 晶 體 3 13 第 一 階 段 315 第 二 階 段 3 17 字 元 線 電 壓 曲 線 3 19 位 元 線 電 壓 曲 線 321 位 元 線 電 壓 曲 線 323 記 憶 胞 電 壓 曲 線 325 電 壓 值 327 電 壓 值 329 電 壓 值 331 電 壓 值 333 運 作 電 壓 範 圍 335 電 壓 值 337 預 a又 電 壓 值 339 第 三 階 段 401 基 數 字 元 線 403 偶 數 字 元 線 500 第 一 階 段 502 第 二 階 段 504 第 三 階 段 506 t己 憶 胞 電 壓 曲 線 508 記 憶 胞 電 壓 曲 線 5 10 位 元 線 電 壓 曲 線 512 位 元 線 電 壓 曲 線 -------—— 1·!裝--------訂--------I'線 (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公f ) 527602 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明（) 發明詳細說明： 請參考第4圖，其所繪示為本發明之一實施例的内嵌 式DRAM記憶胞的配置示意圖。在第4圖中，透過位元線 和字元線將眾多的記憶胞電性連接，構成一個記憶胞網路 1 9 9，並與第5圖之感測放大器2 5 0電性連接，以檢測每個 記憶胞中所儲存的電壓，其中每個記憶胞是由電晶體（如P 型金氧半導電晶體，即PMOS)和電容器所組成，每個記憶 胞中的電晶體的閘極電性連接至對應的字元線，源極和汲 極其中之一者和電容器連接，另一者與對應的位元線電性 連接。例如，記憶胞201分別與位元線203和字元線205 電性連接，而記憶胞207分別與位元線209和字元線2 1 1 電性連接。 請參考第5圖，其所繪示為本發明之一實施例的感測 放大器的電路示意圖。第5圖中之感測放大器250是由選 擇電路252、增益電路254、預充電電路256和降壓電路 25 8以及對應的致能線260和致能線262，及等位致能線 2 64所構成。其中選擇電路2 5 2是用以開啟輸出的信號， 而增益電路254則是將從記憶胞網路1 99(如第4圖所示） 中之記憶胞檢測到的電壓放大，以利後續之信號處理。而 在第5圖中之預充電電路256,會將第4圖中之位元線203 和位元線209充電至如第6圖之運作電壓範圍333之最高 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -------------裝--------訂.--------線 (請先閱讀背面之注意事項再填寫本頁) 527602 A7 B7 五、發明說明（ 電壓值32 7，以作為參考電壓。 -------1--- - -- --- (請先閱讀背面之注意事項再填寫本頁) 首先對儲存有“ 〇，，數位訊號的記憶胞2〇丨進行讀取時 作說明，請參考第6圖，其所繪示為對根據第4圖的記憶 胞進行讀取時之電壓對時間的關係圖。在讀取記憶胞2 0 1 的第一階段3 13中，字元線205的電壓如字元線電壓曲線 317所示維持在比運作電壓範圍333還高的電壓值325,位 元線203和位元線209則皆被預充電至運作電壓範圍3 3 3· 之最高電壓值327，而儲存有“ 0”數位訊號的記憶胞201 之電壓約位於運作電壓範圍333之一半的電壓值329，而 並不是位於運作電壓範圍333之最低電壓值331。 經濟部智慧財產局員工消費合作社印製 當讀取第4圖之記憶胞201時，字元線205和第5圖 之致能線262被施壓，於是如第6圖之字元線電壓曲線3 1 7 所示，字元線205的電壓下降，便會啟動記憶胞201中的 PMOS。同時，第5圖之感測放大器250中降壓電路258的 電晶體268 (如PMOS)亦啟動，將位元線209的電壓降低至 預設電壓值3 3 7，如位元線電壓曲線3 2 1所示。同時，由 於記憶胞20 1儲存的數位訊號為“ 〇” ，因此記憶胞20 1的 電壓值329比位元線203的電壓值327低，故記憶胞201 中的PMOS啟動時，位元線203便會對記憶胞201的電容 器快速充電，於是記憶胞20 1的電壓和位元線203的電壓’ 就如第6圖中之記憶胞電壓曲線323和位元線電壓曲線3 1 9 ^紙張尺度適用中_家鮮（CNS)A4規格（ X 297公釐） 527602 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（ 般’在很短的時間内到達第一階段3 1 5中之平衡的電壓值 3 3 5 ^ 當項取第4圖之3己憶胞2 Ο 1時，以位元線2 Ο 9的電壓 值作為參考電壓，由於位元線203對記憶胞201的電容器 充電，因此如第6圖所示，透過對第5圖之降壓電路258 的電晶體2 6 8作適當的設計，可使得在第二階段3 1 5時位 元線203的電壓值3 3 5比位元線209的預設電壓值337(即 參考電壓）低，第5圖之感測放大器250的增益電路254便 可藉預設電壓值337和位元線203的電壓值335之差值作 進一步的放大，所以經過感測放大器25〇的增益電路254 處理後，如第6圖所示·於第三階段3 3 9時，比預設電壓 值3 3 7低的位元線203之電壓值3 3 5被進一步降低至運作 電壓範圍3 3 3之最低電壓值3 3 1，如此即可分辦出此記憶 胞所儲存的數位訊號為“ 〇” 。 接著’對儲存有“ 1 ”數位訊號的記憶胞2 〇丨進行讀取 時作忒明，請參考第7圖，其所繪示為對根據第4圖的記 憶胞進行讀取時之電壓對時間的關係圖。在第一階段3 ! 3 中，子疋線205的電壓如字元線電壓曲線3丨7所示維持在 比運作電壓範圍3 3 3還高的電壓值3 25 ,位元線2〇3和位 元線209則皆被預充電至運作電壓範圍3 3 3之最高電壓值 327，而儲存有“丨，，數位訊號的記憶胞2〇ι之電壓約位於 本紙張尺度適]τ關家標準（CNS)A4規格（21G x 297公餐）----- --------------裝--------訂---------線 ί請先閱讀背面之注意事項再填寫本頁) 527602 A/ __B7 五、發明說明（） 運作電壓範圍333之最高電壓值327。 當讀取第4圖之記憶胞2 01時，字元線2 0 5和第5圖 之致能線262被施壓，於是如第7圖之字元線電壓曲線3 j 7 所示，字元線205的電壓下降，便會啟動記憶胞2〇丨中的 PMOS。同時，第5圖之感測放大器250中降壓電路25 8的 電晶體268(如PMOS)亦啟動，將位元線209的電壓降低至 預設電壓值3 3 7，如位元線電壓曲線3 21所示。此外，由 於記憶胞20 1儲存的數位訊號為“ 1 ” ，因此記憶胞2〇丨的 電壓值與位元線203的電壓值相同。 --------------裝·！ (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 當讀取第4圖之記憶胞2 Ο 1時，是以位元線2 Ο 9的電 壓值作為參考電壓，由於記憶胞201的電壓值與位元線203 的電壓值相同。因此如第7圖所示，透過對第5圖之降壓 電路25 8的電晶體268作適當的設計，可使得在第二階段 3 15時位元線203的電壓值比位元線209的預設電壓值337 (即參考電壓）高，第5圖之感測放大器250的增益電路254 便可藉預設電壓值3 3 7和位元線203的電壓之差值作進一 步的放大。所以經過感測放大器2 5 0的增益電路2 5 4處理 後，如第7圖所示·於第三階段3 3 9時，比位元線2 0 3之 電壓低的預設電壓值337被進一步降低至運作電壓範圍 3 3 3之最低電壓值3 3 1，如此即可分辦出此記憶胞所儲存的 數位訊號為“ 1 ” 。 15 訂 線 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 527602 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（） 同樣的動作原理也會出現在讀取與位元線2 0 9和字元 線2 1 1電性連接的記憶胞2 0 7時，以位元線2 0 3的電壓作 為參考電壓’而且當字元線211被施壓時，致能線260亦 同時被施壓，以啟動第5圖之感測放大器250中降壓電路 258的電晶體266(如PMOS)，將位元線203的電壓降低至 預設電壓值3 3 7。第5圖之增益電路254再對預設電壓值 337和記憶胞207的電壓值之間的差值作進一步的放大。 所以讀取記憶胞20 1和記憶胞207的動作原理皆相同。 請參考第8圖，其所繪示為本發明之一實施例的内嵌 式DRAM細胞網路和感測放大器連接的示意圖。透過適當 的電路設計，例如對字元線加以編號，使得當基數字元線 401被施壓時，感測放大器250中的致能線262亦被施壓， 以啟動電晶體268，將位元線209的電壓降低至預設電壓 值。當偶數字元線403被施壓時，感測放大器250中的致 能線260亦被施壓，以啟動電晶體266，將位元線209的 電壓降低至預設電壓值。而預設電壓值主要係依據：運作 電壓範圍之最高電壓值、記憶胞儲存有“ 0 ”數位訊號時的 電壓值，以及降壓電路中的電晶體266和電晶體268的設 計，以求於讀取存有“ 〇 ”數位訊號的記憶胞時，令與記憶 胞相連的位元線之電壓比參考電壓低，於讀取存有“ 1，，數 位訊號的記憶胞時，令與記憶胞相連的位元線之電壓比參 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ---------裝--------訂---------線 (請先閱讀背面之注音〗事項再填寫本頁) 527602 A7 經濟部智慧財產局員工消費合作社印製 B7 五、發明說明（） 考電壓高。因此增益電路便可進一步將位元線的電壓和參 考電壓此二者之相差值放大以便於感測。 請參考第9圖，第9圖其所繪示為根據第6圖和第7 圖而得到之内嵌式DRAM於運作時記憶胞中電壓對時間的 關係圖。在第9圖中，係包括了讀取記憶胞中儲存的數位 訊號為1 ’和讀取記憶胞中儲存的數位訊號為“ 〇，，時 的兩種情況。於第一階段500時，若記憶胞中儲存的數位 訊號為‘‘ 0”時，則如記憶胞電壓曲線5〇6所示，約位於運 作電壓範圍之一半的電壓值；若記憶胞中 丨〜肥r 1¾存的數位訊號 為‘‘ 1”時，則如記憶胞電壓曲線508所示，約位於運作電 塵範圍之最高電壓值’而位元線皆被充電至運作電壓範圍 之最高電麼值，如位元線電壓曲線510和位元線電壓曲線 512所示。於第二階段502,當讀取 “ ” ϋ U肥中儲存的數位訊 號為“ 0 ”時，位元線電壓曲線5 1 〇會下 ， X T降，而記憶胞的電 壓會上升’直到位元線的電壓約等於 寸％圮憶胞的電壓；當讀 取記憶胞中儲存的數位訊號為“丨，，時， ^ 田於第5圖之降壓 電路258的啟動，使得位元線電壓曲 琛5 12會下降，而記 憶胞的電壓沒有明顯的變化。於第= ^ ^ _ ~ 1 “又5〇4，第5圖之 增益電路254便將記憶胞的電壓和位 疋線的電壓進一步放 大。 同樣的動作原理也會出現在對健 丁储存有“〇，，數位訊號 17 私紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公餐） ------ ----i I · ---- ----^ · I-------^ (請先閱讀背面之注意事項再填寫本頁) 527602 A7 B7 五、發明說明（ 的記憶胞20 1，或儲存有“丨，’數位訊號的記憶胞1進行 讀取時，以位元線203的電壓值作為參考電壓，而第5圖 之致能線260亦同時被施壓以啟動電晶體266(第5圖示 之）。 透過上述之檢測步驟，在讀取和檢測儲存“ 〇，，的數位 訊號或儲存‘‘ Γ的數位訊號之記憶胞時，都可準確分辨出 ‘‘ 0”的數位訊號和“丨”的數位訊號，因此在低電壓運 作’邏輯製程的内嵌式DRAM中應用本發明，可大幅提高 讀取時的準確度，而且實施的成本低廉以及技術困胃難1 低0 ----I--------裝· ！ (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 本發明之優點為提供了一種用以感測動態隨機存取記 憶體内之電壓的系統及其應用，特別係應用在低電壓邏輯 製程的内嵌式DRAM中，用以提高讀取儲存DRAM中資料 時的準確度。由於本發明之感測動態隨機存取記憶體内之 電壓的系統’係透過配置適當的電晶體，以及將參考電壓 提升至運作電壓範圍之最高電壓值，因此儲存有數位訊號 為的記憶胞之電壓亦可相應提高，於是不容易受到沒 漏電流的影響。於讀取記憶胞之電壓時，經過適當配置的 電晶體使參考電壓下降至預設電壓值，就可準確分辨出 ‘‘ 0”的數位訊號和“ 1 ’’的數位訊號，解決低電壓邏輯製 程的内嵌式DRAM於讀取資料時常出現錯亂的問題。 18 訂 線 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公t ) 527602 A7 B7 五、發明說明（ 明範改 發利效 本專等 為請之 僅申成。 述之完内 所 明所圍 上發下範 以本神利 ’定精專 的限之請 解以示申 瞭W揭之 用 所_所述 員 ¥ 明下 人並發在 之 本含 術已離包 技Jft脫應 此例未均 悉施它， 熟實其飾 如佳凡修 較；或 之圍變 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）V. Description of the invention (Accuracy of reading data. According to the above-mentioned purpose, the present invention provides a system for sensing voltage in a dynamic random access memory and its application. By configuration, 7 of the The transistor is connected to the memory cell network in the embedded dram, and the reference voltage is raised to the highest voltage value in the operating voltage range. At the same time, any memory cell in the network is activated at the same time. Corresponding 2. Take the sun and the sun, and reduce the reference voltage, so that when the memory cell stores a digital signal of "π υ, the reference voltage is higher than the voltage of the memory cell. When the memory cell stores a digital signal of 1, the reference voltage The voltage is lower than the memory cell, and the digital signal stored in the memory cell can be accurately obtained through the amplification of the gain circuit, which solves the problem that the internal-type dram in the low-voltage logic process often gets confused when reading data. The diagram is simply explained: The present invention The preferred embodiment of the present invention will be described in more detail in the following explanatory text with the following figures, in which: Figure 1 is a diagram showing a dynamic random access memory cell -------------- Installation -------- Order. (Please read the note on the back? Matters before filling out this page) Figure 2 is a graph showing the relationship between voltage and time when reading a memory cell of a conventional embedded DRAM. Figure 3 is a graph showing the memory cell of a conventional embedded DRAM during operation. Paper size applies to China National Standard (CNS) A4 (210 X 297 mm) 527602 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 15 Metal-oxygen semi-conductive crystals 25-bit line 50-bit line voltage curve 60 First stage 70 Voltage 80 Second stage 90 Memory cell voltage curve A7 B7 V. Description of the invention () Voltage vs. time. Figure 4 is a schematic diagram showing the configuration of an embedded DRAM memory cell according to an embodiment of the present invention. Fig. 5 is a schematic diagram of a circuit of a sense amplifier according to an embodiment of the present invention. Fig. 6 is a diagram showing a relationship between voltage and time when reading a memory cell according to Fig. 4. Fig. 7 It is shown as a note on Figure 4 The relationship between voltage and time when the memory cell is reading. Figure 8 is a schematic diagram showing the connection between the embedded DRAM cell network and the sense amplifier according to an embodiment of the present invention. Figure 9 is shown as The relationship between voltage and time in the memory cell of the embedded DRAM according to Figures 6 and 7 during operation. Comparison of drawing numbers: 10 memory cells 20 capacitors 30 word lines 55 voltage 65 memory cell voltage curve 75 Operating voltage range 85 bit line voltage curve 10 This paper size is applicable to China National Standard (CNS) A4 specification (210 X 297 mm) ------------- Installation ------- --Order · --------- line (please read the precautions on the back before filling this page) 527602 A7 B7 V. Description of the invention () Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs, Consumer Consumption Cooperative 95 Voltage 100 t Memory cell voltage curve 105 Voltage 199 1 Memory cell network 201 1 Memory cell 203 Bit line 205 Word line 207 Memory cell 209 Bit line 21 1 Word line 250 Sense amplifier 252 Selection circuit 254 Gain circuit 256 Advance Electrical circuit 258 Buck circuit 260 enable line 262 enable line 264 equipotential enable line 266 transistor 268 transistor 3 13 first stage 315 second stage 3 17 word line voltage curve 3 19 bit line voltage curve 321 Bit line voltage curve 323 memory cell voltage curve 325 voltage value 327 voltage value 329 voltage value 331 voltage value 333 operating voltage range 335 voltage value 337 pre-a and voltage value 339 third stage 401 base digital line 403 even digital line 500 The first stage 502 The second stage 504 The third stage 506 t The memory cell voltage curve 508 The memory cell voltage curve 5 10-bit line voltage curve 512-bit line voltage curve ----------- 1 ·! 装- ------- Order -------- I 'line (Please read the precautions on the back before filling this page) This paper size is applicable to China National Standard (CNS) A4 specification (210 X 297 male f ) 527602 Printed by A7, Consumer Cooperatives, Intellectual Property Bureau, Ministry of Economic Affairs B7 V. Description of the invention () Detailed description of the invention: Please refer to FIG. 4, which shows a schematic diagram of the configuration of an embedded DRAM memory cell according to an embodiment of the present invention. In FIG. 4, a plurality of memory cells are electrically connected through bit lines and word lines to form a memory cell network 199, and are electrically connected to the sense amplifier 2 500 in FIG. 5 to Detect the voltage stored in each memory cell, where each memory cell is composed of a transistor (such as a P-type metal-oxide-semiconductor crystal, or PMOS) and a capacitor. The gate of the transistor in each memory cell is electrically charged. Is connected to the corresponding word line, one of the source and the drain is connected to the capacitor, and the other is electrically connected to the corresponding bit line. For example, the memory cell 201 is electrically connected to the bit line 203 and the word line 205, respectively, and the memory cell 207 is electrically connected to the bit line 209 and the word line 2 1 1 respectively. Please refer to FIG. 5, which is a schematic circuit diagram of a sense amplifier according to an embodiment of the present invention. The sense amplifier 250 in FIG. 5 is composed of a selection circuit 252, a gain circuit 254, a precharge circuit 256, and a step-down circuit 258, and corresponding enable lines 260 and 262, and equipotential enable lines 2 64. Made up. The selection circuit 2 5 2 is used to turn on the output signal, and the gain circuit 254 is to amplify the voltage detected from the memory cells in the memory cell network 1 99 (as shown in FIG. 4) to facilitate subsequent Signal processing. The pre-charging circuit 256 in FIG. 5 charges the bit lines 203 and 209 in FIG. 4 to the highest operating voltage range 333 as shown in FIG. 6. This paper size applies the Chinese national standard (CNS ) A4 size (210 X 297 mm) ------------- install -------- order .-------- line (please read the note on the back first) Please fill out this page again) 527602 A7 B7 V. Description of the invention (Voltage value 32 7 as reference voltage. ------- 1 -------- (Please read the precautions on the back before (Fill in this page) First of all, the description will be given when reading the memory cell “0 ,, the digital signal 2〇 丨, please refer to Figure 6, which is shown when reading the memory cell according to Figure 4. Voltage vs. time. In the first stage 3 13 of reading the memory cell 2 0 1, the voltage of the word line 205 is maintained at a higher voltage than the operating voltage range 333 as shown by the word line voltage curve 317. Value 325, bit line 203 and bit line 209 are all pre-charged to the highest voltage value of 327 in the operating voltage range 3 3 3 ·, and the voltage of the memory cell 201 storing the "0" digital signal is approximately in the operating voltage range 333 One half of the voltage value 329, but not the lowest voltage value 331 located in the operating voltage range 333. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs When reading the memory cell 201 in Figure 4, the character line 205 and the fifth line The enabling line 262 in the figure is pressed, so as shown in the character line voltage curve 3 1 7 in FIG. 6, the voltage of the word line 205 drops, and the PMOS in the memory cell 201 is activated. Meanwhile, FIG. 5 The transistor 268 (such as PMOS) of the step-down circuit 258 in the sense amplifier 250 is also activated to reduce the voltage of the bit line 209 to a preset voltage value 3 3 7 as shown in the bit line voltage curve 3 2 1. At the same time, since the digital signal stored in the memory cell 20 1 is “0”, the voltage value 329 of the memory cell 20 1 is lower than the voltage value 327 of the bit line 203. Therefore, when the PMOS in the memory cell 201 starts, the bit line 203 The capacitor of the memory cell 201 is quickly charged, so the voltage of the memory cell 20 1 and the voltage of the bit line 203 ′ are as shown in the memory cell voltage curve 323 and the bit line voltage curve 3 1 9 in FIG. 6 ^ paper size Applicable_Home Fresh (CNS) A4 Specification (X 297 mm) 527602 A7 B7 Ministry of Economy Wisdom Printed by the Production Bureau Staff Consumer Cooperatives V. Invention Description (Generally, the equilibrium voltage value in the first stage 3 1 5 is reached within a short period of time 3 3 5 ^ When the item is taken, 3 of Figure 4 has been recalled 2 〇 At 1 o'clock, the voltage value of bit line 2 0 9 is used as the reference voltage. Since bit line 203 charges the capacitor of memory cell 201, as shown in FIG. 6, the voltage of voltage reduction circuit 258 in FIG. The proper design of the crystal 2 6 8 can make the voltage value of the bit line 203 3 3 5 lower than the preset voltage value 337 (that is, the reference voltage) of the bit line 209 at the time of the second stage 3 1 5. The gain circuit 254 of the sense amplifier 250 can further amplify the difference between the preset voltage value 337 and the voltage value 335 of the bit line 203, so after processing by the gain circuit 254 of the sense amplifier 25, as in the first As shown in Fig.6, the voltage value of bit line 203 which is lower than the preset voltage value 3 3 7 at the third stage 3 3 9 is further reduced to the lowest voltage value of the operating voltage range 3 3 3 3 3 1. In this way, the digital signal stored in this memory cell can be divided into "0". Then 'read the memory cell 2 which stores the "1" digital signal, and read it. Please refer to Figure 7, which shows the voltage pair when reading the memory cell according to Figure 4. Diagram of time. In the first stage 3.3, the voltage of the sub-line 205 is maintained at a higher voltage value 3 25 than the operating voltage range 3 3 3 as shown in the character line voltage curve 3 丨 7, and the bit line 203 and Bit line 209 is pre-charged to the highest voltage value of 327 in the operating voltage range 3 3 3, and the voltage of the memory cell 20 stored with "丨, the digital signal is about the size of this paper.] (CNS) A4 specifications (21G x 297 meals) ----- -------------- install -------- order --------- Please read the precautions on the back before filling this page) 527602 A / __B7 V. Description of the invention () The highest voltage value 327 of the operating voltage range 333. When reading the memory cell 2 01 in Figure 4, the character line The enabling line 262 in FIG. 5 and FIG. 5 is pressed, so as shown in the character line voltage curve 3 j 7 in FIG. 7, the voltage of the word line 205 drops, and the memory cell 20 is activated. At the same time, the transistor 268 (such as PMOS) of the step-down circuit 25 8 in the sense amplifier 250 in FIG. 5 is also activated, and the voltage of the bit line 209 is reduced to a preset voltage value 3 3 7 such as the bit The line voltage curve 3 is shown in 21. In addition, since the memory cell 20 1 The stored digital signal is "1", so the voltage value of the memory cell 20o is the same as the voltage value of the bit line 203. -------------- Loading! (Please read first Note on the back, please fill out this page again.) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. When reading the memory cell 2 0 1 in Figure 4, the voltage value of the bit line 2 0 9 is used as the reference voltage. The voltage value of the cell 201 is the same as the voltage value of the bit line 203. Therefore, as shown in FIG. 7, by appropriately designing the transistor 268 of the step-down circuit 25 8 of FIG. 5, the second stage 3 At 15 o'clock, the voltage value of the bit line 203 is higher than the preset voltage value 337 (ie, the reference voltage) of the bit line 209. The gain circuit 254 of the sense amplifier 250 in FIG. 5 can borrow the preset voltage value 3 3 7 and The voltage difference of the bit line 203 is further amplified. Therefore, after processing by the gain circuit 2 5 4 of the sense amplifier 2 50, as shown in FIG. The low preset voltage value 337 of line 2 0 3 is further reduced to the lowest voltage value 3 3 1 of the operating voltage range 3 3 3, so that it can be divided The digital signal stored by this memory cell is “1.” 15 The size of the paper for the thread guide is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 527602 A7 B7 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs Explanation of the invention () The same operating principle will also appear when reading the memory cell 2 0 7 electrically connected to the bit line 2 0 9 and the word line 2 1 1, using the voltage of the bit line 2 0 3 as a reference Voltage ', and when the word line 211 is pressed, the enable line 260 is also pressed at the same time to activate the transistor 266 (such as PMOS) of the step-down circuit 258 in the sense amplifier 250 of FIG. The voltage of the line 203 is reduced to a preset voltage value 3 3 7. The gain circuit 254 of FIG. 5 further amplifies the difference between the preset voltage value 337 and the voltage value of the memory cell 207. Therefore, the operation principles of reading the memory cell 201 and the memory cell 207 are the same. Please refer to FIG. 8, which illustrates a schematic diagram of the connection between the embedded DRAM cell network and the sense amplifier according to an embodiment of the present invention. Through proper circuit design, such as numbering the word lines, when the base digital line 401 is pressed, the enable line 262 in the sense amplifier 250 is also pressed to activate the transistor 268 and set the bit The voltage of the line 209 is reduced to a preset voltage value. When the even digital element line 403 is pressed, the enable line 260 in the sense amplifier 250 is also pressed to activate the transistor 266 and reduce the voltage of the bit line 209 to a preset voltage value. The preset voltage value is mainly based on the highest voltage value in the operating voltage range, the voltage value when the memory cell stores a "0" digital signal, and the design of the transistor 266 and transistor 268 in the step-down circuit in order to When reading a memory cell with a "0" digital signal, the voltage of the bit line connected to the memory cell is lower than the reference voltage. When reading a memory cell with a "1," digital signal, the memory cell The voltage ratio of the connected bit lines is based on the paper size of the Chinese National Standard (CNS) A4 (210 X 297 mm) --------- installation -------- order --- ------ line (please read the note on the back first and then fill out this page) 527602 A7 Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs B7 V. Description of the invention () The test voltage is high. So the gain circuit can be further Amplify the difference between the bit line voltage and the reference voltage for easy sensing. Please refer to Figure 9 which shows the embedded DRAM obtained from Figures 6 and 7 The relationship between voltage and time in the memory cell during operation. In Figure 9, it includes the reading record Cells stored digital signal is a 'and read the digital signal stored in the memory cell is "square ,, the two cases. At 500 in the first stage, if the digital signal stored in the memory cell is "0", as shown in the voltage curve of the memory cell 506, it is located at about half of the operating voltage range. ~ r 1¾ fat stored digital signal is '1 ", the memory cell voltage curve 508 such as shown, is located about the maximum voltage into the operating power range of the dust' and bit line are electrically charged to the highest operating voltage range This value is shown by the bit line voltage curve 510 and the bit line voltage curve 512. In the second stage 502, when the digital signal stored in the “” U fertilizer is read as “0”, the bit line voltage curve 5 1 〇 will decrease, XT will decrease, and the voltage of the memory cell will increase until the bit The voltage of the line is approximately equal to the voltage of the memory cell. When the digital signal stored in the memory cell is “丨,”, the field voltage of the bit line in FIG. 5 is activated, which makes the voltage of the bit line curve. Chen 5 12 will drop, but the voltage of the memory cell does not change significantly. In the first = ^ ^ _ ~ 1 "and 5 0, the gain circuit 254 of Figure 5 will further the voltage of the memory cell and the voltage of the bit line amplification. The same principle of action will also appear in the storage of Jianding with "0 ,, digital signal 17 private paper size applicable to China National Standard (CNS) A4 specifications (210 X 297 meals) ------ ---- i I · ---- ---- ^ · I ------- ^ (Please read the precautions on the back before filling out this page) 527602 A7 B7 V. Description of the invention (memory cell 20 1, or storage When the memory cell 1 with “丨,” digital signal is read, the voltage value of the bit line 203 is used as the reference voltage, and the enable line 260 in FIG. 5 is also pressed to start the transistor 266 (page 5 As shown in the figure, through the above detection steps, when reading and detecting the memory cell that stores "0 ,," or the digital signal that stores Γ, the digital signal and "0" can be accurately distinguished. "丨" digital signal, so the application of the present invention to the embedded DRAM in the logic process of low voltage operation can greatly improve the accuracy of reading, and the implementation cost is low and the technology is difficult. 1 Low 0- --I -------- installed! (Please read the precautions on the back before filling out this page) The advantage of Fei Co., Ltd. printing the present invention is to provide a system for sensing the voltage in the dynamic random access memory and its application, especially applied to the embedded DRAM in the low voltage logic process to improve the read Accuracy when fetching data from DRAM. Because the system of the invention for sensing the voltage in the dynamic random access memory is through the configuration of an appropriate transistor and raising the reference voltage to the highest voltage value in the operating voltage range, Therefore, the voltage of the memory cell where the digital signal is stored can be increased accordingly, so it is not easy to be affected by no leakage current. When reading the voltage of the memory cell, a properly configured transistor will reduce the reference voltage to a preset voltage value. , It can accurately distinguish the digital signal of "0" and the digital signal of "1", and solve the problem that the embedded DRAM in the low-voltage logic process often gets confused when reading data. 18 Dimensions This paper is suitable for China National Standard (CNS) A4 Specification (210 X 297 Gt) 527602 A7 B7 V. Description of the Invention In the end, it is stated that the scope of this article is based on the definition of the "special benefits" to explain the application of W to expose the use of the _ mentioned members. Technical Jft did not fully understand the application of this example, familiar with its decoration, such as Jiafan repair; or the change (please read the precautions on the back before filling this page) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs Paper size applies to China National Standard (CNS) A4 (210 X 297 mm)