TWI234786B - Memory device with high charging voltage bit lines - Google Patents

Abstract

A memory device with high charging voltage bit lines comprises memory cells, sense amplifiers, and high charging voltage bit line circuits. The memory cell stores data and electrically couples with a pair of bit lines. The sense amplifier has a pair of sense nodes. The pair of sense nodes electrically couple with the pair of bit lines and sense the voltage differential across the sense nodes during active cycle. The high charging voltage bit line circuit provides a charging voltage higher than a high logic voltage for charging the memory cell.

Description

V. Description of the invention (1) 1. [Technical field to which the invention belongs] It relates to a memory device having a high-charge potential bit line to make the memory: a potential at a logic high potential. Memory device. -, [Prior art]

The structure of the basic unit M of the dynamic random access memory (Dynamic R ^ AM) is simple m 丄 As shown in Figure -a, the single-electric state is 1 or 0,::: = = ΐ ,? The logical state of a machine accessing a unit of memory is charge. A charge ^ snow; t benefit 1 〇 can store a certain amount of electrons or "empty" capacitor ΪΪ 视为 Valley device is considered as a logical state (τ 丨 ^, 疋. And capacitor 10 due to the leakage current between The stored it-like energy ΐ = the stored charge, resulting in a positive period of time, while maintaining the logical state; ΐ will destroy the charge in the memory, that is, the kinetic energy L ⑨ stored logical state has It is destructive. Therefore, it is necessary to make a chop 5 5 and take 6 memory units after each read operation to perform a 'line-person write-back (charging) operation. So the memory except for each fixed 1234786

After the mother-person continues the fetch operation, it is also necessary to refresh the time interval (refresh)-once again. The single-bit address design, the physical base, the bit memory, and a meta-reading type N4 and refer to the first B diagram, each dynamic random access memory cell m element (Bit), and there is a unique by the column address and row address. To simplify the structure of the memory, dynamic random access memory cannot be read independently. As a result, the multi-report dynamics are connected to the same word line WL (word Une) and the wood line BL (bit 1 ine), forming a matrix structure. The integrated matrix structure passes through a channel element (pass gat〇 ^ = sense amplifier), which is used to amplify (or write) the charge in the inner valley. Among them, the channel element crystal M, N2, and the sensor The amplifier is composed of N-type electric bodies P-type P1 and P2. ^ 1%, refer to the first C diagram, which is a schematic diagram of the operation between the various components. The basic unit of memory M must be set to Active (read and write) before reading and writing. ) State, this state will be maintained for a period of time, as shown in the 14th interval of the first C chart ^ First, the potential of the word line is raised to a high potential, so that the transistor of the basic unit M of the memory丨 2 is turned on, and the transistor N2 and N2 of the component are turned on, so that the logic state of the memory unit% == logical state of the device 10 can be transmitted to the sensing amplifier t via the bit line pair BL and / BL. When the transistor M2 of the basic unit of memory is not turned on, the potential of the pair BL and / BL will be maintained at the initial potential Vbleq, and the electric capacity of 70

1234786 V. Description of the invention (3) When the electric charge of device 10 is stored, the potential of BL or / BL will start to rise upward, as shown by 16 in the first C diagram. Conversely, when capacitor 10 is not stored, When there is any charge, the potential of BL or / BL will start to decrease. Therefore, when the logic state (charge) of the capacitor 10 is different, the potential of the bit line is also different. Then, the NCS potential at the junctions of transistors N3 and N4 drops to a logic low potential Vss, and the PCS potential at the junctions of transistors P1 and P2 rises to a logic high potential-

Vblh. The bit line originally maintained at the potential Vbleq will have its potential drop to a logic low potential Vss, while the bit line whose potential is higher than Vbleq will have its electrical θ potential set to a high potential Vblh. The above process is the write-back of the memory ^ ^. Through this process, the logical state of the memory unit will return to the optimal state of the potential (Vblh, Vss) again. 』Wang Jianji And because dynamic random access memory requires continuous advancement, it is more expensive than other types of memory. The trend is to develop at low power. 卩 Reduce dynamic random access: its development cost. Therefore, in order to achieve low power, the operating voltage of the power storage: power unit will also be continuously reduced (take 5 volts from your brother and recall 2.5 volts, 1.8 volts ...). The bit green from the temple, 3.3 volts to the same has a trend towards low voltage development. The working voltage stored in the capacitor is also Q = C * AV. The amount of charge stored in the hall is △ V = Vblh-Vbleq (1). It can be seen from the hour that when the operating voltage of the bit line changes, The amount of charge Q will also decrease and △ will decrease, and the amount of charge will decrease.

1234786 V. Description of the invention (4) When the first t_16 part of t's, the difference will become smaller or the time required will need to be more recognized t The bit line's induction rate to the capacitor will be slower, and it should be more logical. The reliability of the judgment result will be reduced, and the retention time (Uata retention time) of the state (charge) will also decrease, and the time interval for writing back will also be shortened. me) Therefore, in the dynamic random access # # I how to reduce the operating voltage U as the voltage decreases, the reliability of the induction, the induction rate of the logical 2-bit line, and the logic problem are also Must hold time and so on, which is bound to be encountered. [Summary of the Invention] I In the background of the above invention, the bit line of the feather * memory is reliable in the dynamic random access memory in the low operating voltage of 2 ° technology. Decreased performance, logic: there is a slow induction rate, and the main purpose of logic is to provide a problem with = time becomes shorter. The body is set so that the bit line is in a low operation ^: the memory of the charging potential bit line is stored in the capacitor. In electric houses, more charges can also be stored. Another object of the present invention is to:-make the capacitor storable; the potential bit becomes shorter. Pure drop, logic state retention = $ 8, page 1234786 V. Description of the invention (5) According to the south of the above potential bit line, the charge potential cell, multiple memory pairs in multiple senses are electrically coupled; the multiple pairs induce the multiple The potential difference of memory; the charge action of several memory bodies is charged at a charge potential, and the charge is more reliable under the corresponding reliability. In part, it does not matter how the scale is compared to the stated purpose of the illustration. The present invention provides a device and method with a high-charge memory. The present invention utilizes a memory device with element lines, which includes a plurality of memory crystal amplifiers and a plurality of high-charge potential bit circuits. Its body cell is used to store data and is connected to a plurality of bit lines and a plurality of inductive amplifiers. It has a plurality of pairs of sensing nodes, and the nodes are respectively electrically coupled to the plurality of bit line pairs. Inducting the plurality of pairs of inductive nodes and a plurality of south charging potential bit circuits includes a plurality of circuits that provide a charging potential that is higher than the potential of the plurality of logic high potentials for the plurality of memories. In this way, bit lines can also be stored in capacitors at low operating voltages to improve issues such as slower induction rates, reduced logic sense, and shorter logic state retention times. [Formula] These implementation examples will be described in detail as follows. However, in addition to the detailed invention, it can also be widely implemented in other embodiments, and it is not limited in scope, which is subject to the scope of subsequent patents. = For a clearer description and easier understanding of the present invention, diagram = Drawing according to its relative dimensions, some dimensions are relative to others = Exaggerated; irrelevant details are not completely drawn _ Jie. 1234786 V. Description of the invention (6) According to the first formula of the equation, if we want to increase the stored charge Q, we can increase △ V to achieve, that is, the internal sense sensor's amplifier is a P-type transistor. The contacts of P1 and P2 are on the write-back side, and the logic high potential is Vblh. In the conventional technique, the pc% S potential must be as shown in the first D diagram. When the bPSEm number drops from a high potential and the voltage source circuit is turned on, the P-type transistor P3 is turned on, so that the voltage of the pcs contact will be low. 'Will provide a high potential Vblh. Become vblh ', so only one by one and a preferred embodiment of the present invention, as shown in Figure 2 and 4, increase the charging potential bit line circuit 18' to make PCS_ close to-higher than the logic high, the potential Vblh2 Vblh2 , With 0 i signal switch anode crystal? 4 to control the conduction of the circuit. In addition to the PCS contact, Vb can be provided, and a higher potential Vblh2 can also be provided. Referring to the second diagram B 'is a memory device having the high-charge potential bit line of the present invention, and the second diagram C is a schematic diagram of the main dynamic operation of the memory device of the second diagram B. First, the potential of the word line is raised to a high potential, so that the transistor of the basic unit of the memory is turned on, and then the transistor N2 and N2 of the channel element are also turned on, so that the logic state stored in the capacitor of the memory unit can be passed through the bit. The pair BL and / BL pass to the sense amplifier. The presence or absence of the charge of the capacitor will affect the potential of the bit line BL or / BL. When there is no charge, the potential of the bit line pair BL and / BL will be lower than the initial potential Vbleq, and when there is a charge, the potential of BL or / BL will start to rise upward, so that the potential of the bit line will be increased due to

Page 10 1234786 V. Description of the invention (7) '一------ The electric valley's electric power is beneficial to the township _The contact is like a potential, and the voltage drop is very different. Then, the potential of the pcs at the contact point of the transistor is as low as ^ ss, «Bray of crystal P1 and m #, a I, and private 20, because the bPSET signal is reduced from high to low, and directly to Logic high Vblh. The bit line that was originally maintained at the potential Vble (l, will decrease to a logic low potential VSS; while the potential is higher than Vbleq m, as shown in Process 22, its potential will rise to a logic high potential bPSET signal back to high Potential, so that transistor P3 is turned off, ίρςΜ'υ is turned from high potential to low potential to turn on transistor P4, so that u / process 24 is further increased to Vblh2, and the potential of the bit line is also toward F The potential Vblh2 increases. So its △ v = VMh2_

Vbleq > Vblh-Vbleq, so the amount of charge that the capacitor can store increases from time to time, so that the bit line's induction rate becomes faster and the logic state retention time is increased by three. However, the Vblh2 potential must be higher than the logic high potential VMh. The level of the international potential can be designed with different environments to meet the needs of the design environment. For signal 0, the time for turning on the high-charge potential bit ^ circuit 18 only needs to be no earlier than the time point such as signal two =, and the time difference between the two signals can be adjusted by %%. According to the spirit of the present invention, the voltage source can also be connected during a write-back operation. After a signal, the circuit is started, so that the potential of the PCS becomes Vbih2 directly, without the need for the logic high potential Vblh and then Vblh2. In summary, the present invention discloses a high-charge potential

Page 11 1234786 V. Description of the invention (8) Memory device of Yuan line. According to the present invention, the memory device having a bit line with a high charging potential can provide a potential higher than a logic high potential during a memory write-back operation, so that the bit line can also be stored at a low operating voltage- More charge is in the capacitor. Use capacitors to store more charge to improve issues such as slower induction rates, reduced reliability in logic induction, and shorter logic state retention times. The above is only a preferred embodiment of the present invention, and is not intended to limit the scope of patent application of the present invention; all other equivalent changes or modifications made without departing from the spirit disclosed by the present invention shall be included in the following Application _ Patent Scope.

Page 121234786 Brief description of the diagram V. [Simplified description of diagram] The first diagram A is a schematic diagram of a memory cell in a conventional technique; the first diagram B is a schematic diagram of a memory device in a conventional technique; the first C The diagram is a schematic diagram of the logic state change of the main dynamics of the memory device in the conventional art. The first diagram D is the circuit of the charging potential bit line of the memory device in the conventional technology. The second diagram A is the local charge potential of the present invention. The bit line circuit is not intended, and the second diagram B is a schematic diagram of a memory device with a high-charge potential bit line circuit of the present invention; and the second diagram C is a memory with a high-charge potential bit line circuit of the present invention Schematic diagram of logic state changes of device main dynamics. Symbols of the main parts: 10 capacitors 12 transistors 14 main dynamic range

Page 1312786 Brief description of the diagram 16 Sensing interval 18 High charge potential bit line circuit 2 0 ~ 2 6 Logic state change process BL, / BL bit line WL, / WL word line SA, / SA Sense amplifier Line M basic unit of dynamic random access memory N1 ~ N4 N type transistor P1 ~ P4 P type transistor

NCS, PCS contact Q charge

Vblh logic high

Vblh2 Charge logic high potential V s s logic low potential Vbleq logic balance potential bPSET, 0 1 signal

Page 14

Claims (1)

1234786 VI. Application Patent Scope 1 · A memory device with a high-charge potential bit line, comprising: a plurality of memory cells for storing data, and being electrically coupled to the plurality of bit line pairs; a plurality of inductive An amplifier having a plurality of sensing nodes, the plurality of sensing nodes being electrically coupled to the plurality of bit line pairs, respectively, wherein when the plurality of memory cells are turned on, 'the potential differences of the plurality of sensing nodes are sensed respectively; and High-charge potential bit circuits include: a plurality of charge-potential circuits for providing a charge potential that is higher than a logic high potential of one of the plurality of memories, thereby performing the plurality of memories Unit cell charging action. 2. For a memory device with a high-charge potential bit line as described in item 1 of the patent application range, wherein the plurality of bit lines have the same potential before the plurality of memory cells are turned on. 3. The memory device of the high-charge potential bit line according to item 1 of the scope of the patent application, wherein the plurality of bit lines described above, after the plurality of memory cell cells are opened, and the plurality of memory crystals having a charge The potential of the bit line of the cell electrical coupling rises. 4. The memory device of the high-charge potential bit line according to item 1 of the patent application scope, wherein the plurality of bit lines mentioned above are opened with the plurality of memory cells and the plurality of memories having no charge. Unit cell electrical coupling Page 15 1234786 6. Scope of patent application The potential of the bit line has decreased. 5. The memory device of the high-charge potential bit line according to item 1 of the patent application scope, wherein the plurality of high-charge potential bit circuits further includes a potential circuit to provide the logic high potential of the plurality of memories. The potential. Lu 6. The memory device of the high-charge potential bit line according to item 5 of the patent application range, wherein the order of the potentials provided by the plurality of high-charge potential bit circuits is the logic high potential and the charge potential. 7. For a memory device with a surface charging potential bit line as claimed in item 5 of the patent application, wherein the plurality of potential circuits mentioned above provide the logic high potential, the charging potential circuit is turned off. 8. For a memory device with a high charge potential bit line as claimed in item 5 of the patent application, wherein the plurality of charge potential circuits described above provide the charge potential, the potential circuit is turned off. 9. A memory device having a high-charge potential bit line, comprising: a plurality of memory cell cells for storing data, and being electrically coupled to the plurality of bit line pairs; a plurality of channel elements for storing the When a plurality of memory cells are powered on, the plurality of bit line pairs are opened respectively; Page 16 1234786 6. The scope of the patent application is a plurality of inductive amplifiers with a plurality of pairs of inductive nodes, and the plurality of inductive nodes are electrically coupled to the plurality of bit line pairs, respectively. When the plurality of memory cells are turned on, The potential differences between the plurality of sensing nodes are respectively sensed; and a plurality of high-charge potential bit circuits include: a plurality of charge-potential circuits for providing a charge potential higher than a logic high potential of one of the plurality of memories Potential to perform the charging operation of the plurality of memory cell units. 10. If the memory device of the high-charge potential bit line of item 9 of the patent application range, wherein the above-mentioned plurality of bit lines has the same potential before the plurality of memory cells are turned on. 1 1 · If the memory device of the high-charge potential bit line of item 9 of the patent application range, wherein the plurality of bit lines described above, after the plurality of channel elements turn on the plurality of bit lines, the The potentials of the bit lines that are electrically coupled by the plurality of memory cell cells rise. 1 2. The memory device of the high-charge potential bit line according to item 9 of the scope of patent application, wherein the plurality of bit lines described above, after the plurality of channel elements have opened the plurality of bit lines, have no charge. The potential of the bit lines of the electrical handles of the plurality of memory cell units decreases. 1 3. Memory of the high-charge potential bit line as described in item 9 of the scope of patent application Page 17 1234786 6. Patent application range device, in which the above-mentioned plurality of high-charging potential bit circuits further include a potential circuit to provide the logic high potential of the plurality of memories 〇1. The memory device of the high-charge potential bit line of the item 13 of the range, wherein the sequence of the potential provided by the plurality of high-charge potential bit circuits is the logic high potential and the charge potential. 15. The memory device of the high-charge potential bit line according to item 13 of the patent application range, wherein the charge-potential circuit is turned off when the plurality of potential circuits mentioned above provide the logic high potential. 16. The memory device of the high-charge potential bit line according to item 13 of the scope of patent application, wherein when the plurality of charge potential circuits mentioned above provide the charge potential, the potential circuit is closed. 1 7. —A method for charging a memory cell, which uses a potential higher than the logic potential of the memory device to charge the memory cell of the memory device, including: opening a plurality of memory cells, wherein the plurality The memory cell and the plurality of bit lines are electrically coupled; when the plurality of memory cells are turned on, the potential difference between the plurality of sensing nodes is sensed and amplified respectively; and a high charging potential is provided to perform the plurality of memories. Cell Charge 1234786 VI. Scope of patent application Electrical action, wherein the high charge potential is higher than a logic high potential of one of the plurality of memories. 18. The method for charging a memory cell according to item 17 of the scope of patent application, wherein the charging order of the above-mentioned memory cell is the logic high potential, the high charge potential. 19. The method for charging a memory cell according to item 17 of the scope of patent application, further comprising a plurality of channel elements, and when the plurality of memory cells are powered on, the plurality of bit line pairs are opened respectively. Page 19