TW434563B - Clamping circuit for memory cell plate in dynamic random access memory - Google Patents

Abstract

This invention is about the clamping circuit for memory cell plate in dynamic random access memory (DRAM). The invention mainly includes a control circuit and an output circuit. The aforementioned control circuit is connected with the output circuit stated above and is used to clamp the reference plate voltage level. The aforementioned output circuit has high driving capability and is controlled by the control circuit stated above to maintain the voltage level of reference plate voltage at normal value. The present invention is particularly suitable for use in embedded DRAM to maintain the stability of reference plate voltage VP.

Description

4 $ 4§i $ A7 __B7___ 5. Description of the invention (/) Detailed description = (1) Technical field of the invention: The present invention relates to a semiconductor circuit, and more particularly to a clamp of a dynamic random access memory memory cell plate. Circuit (CLAMPING CIRCUIT FOR CELL PLATE IN DRAM). The clamping circuit (CLAMPING CIRCUIT) is used to clamp the voltage level of the memory cell plate in the dynamic random access memory (DRAM) of the CLAMPING. (II) Technical background of the invention: According to the current design and manufacturing process of Dynamic Random Access Memory (DRAM), the design of One-Transistor Cell has been widely known. A technique used in dynamic random access memory (DRAM). In the design of a DRAM memory cell, each memory cell in the memory is composed of a storage capacitor that stores data, and an access power supply connected to the storage capacitor to provide a data access path. Crystal (Access Transistor). Furthermore, all memory cells form a cell array in a dynamic random access memory (DR AM) chip, and contain some necessary peripheral circuits to determine the address of each memory cell. And processing the stored data 9 Printed by A7 B7, Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention (X) A typical D RAM is a metal-oxide-semiconductor field-effect transistor (MOSFET) and capacitor on a silicon semiconductor substrate. The source (or drain) of the field effect transistor is used to connect the charge storage electrode (Storage Node) of the capacitor to form a memory cell of the dynamic random access memory. A large number of memory cells are aggregated into a memory cell array, which is then supplemented. With auxiliary circuits such as a sensing amplifier (SA), dynamic random access memory is completed. In a memory cell, the pole of each access transistor is controlled by a word line, and its source and drain are connected to a bit line and a storage capacitor in the same memory cell, respectively. In a word, the access transistor system used in dynamic random access memory is an N-type transistor. When selecting to connect all the memory cells on a certain character line, that is, the character line is in a "HIGH" logic state, the corresponding data can be written into the storage capacitor by connecting the bit line of each memory cell Or read from the storage capacitor. First, please refer to Figure 1. Figure 1 is a simplified diagram of a memory cell array in a dynamic random access memory. The figure contains four memory cells (CELLG to CELL3), two word lines (WL0 and WL1), and four bit lines (BLOB and BL0 and BL1B and BL1). Among them, each memory cell is composed of a pair of transistors (NO to N3) and a capacitor. The sense amplifier (S A) determines the data stored in each memory unit, and it is controlled by a sense amplifier enable (S A E) signal. The character line ffLO is used to control the first memory cell CELL1, the second transistor N2, and the second capacitor composed of the first transistor N1 and the first capacitor. The paper size is applicable to Chinese national standards (CNS > A4 specification (210 X 29 + mm) ™

Consumption cooperation by employees of the Intellectual Property Bureau of the Ministry of Economic Affairs. Du V. Invention Description (>) The second memory unit CELL2; and the character line WL1 is used to control the third transistor NO and the third capacitor. The fourth memory cell CELL3 composed of the three memory cells CELLO, the fourth transistor N3, and the fourth capacitor is general. In general, the number of memory cells controlled by each word line is fixed. When the word line WLG selects the first memory cell and the second memory cell, that is, the transistors N1 and N2 are turned on, the data signal can be written into the first and second capacitors from the bit lines BLG and BL1, or from the first The first and second capacitors are read. When the word line WL1 selects the third memory cell and the fourth memory cell, that is, the transistors NG and N3 are turned on, the data signal can be written into the third and fourth capacitors from the bit lines BLOB and BL1B, or from the first The third and fourth capacitors are read out. In addition, in the design of dynamic random access memory (DRAM), the voltage of the memory cell electrode of the capacitor in the memory cell is maintained at a reference plate voltage VP (see Figure 1), and the other electrode of the capacitor It is connected to the access transistor in the same memory cell. The selection of the reference panel _VP is usually between the low voltage source Vss and the high voltage source VDD (such as 1 / 2Vdd, if the operating voltage is between 0V and VDD). The main purpose of designing the reference plate voltage VP of the memory cell is to reduce the voltage drop across the capacitor in the memory cell, so that the voltage intensity across the capacitor is reduced. However, because the reference plate voltage is between the low voltage source Vss and the high voltage source VDD, a static current will be generated in the dynamic random access memory, resulting in a waste of maintaining current and power. This paper size applies to China National Standard (CNS) A4 (210 X 29 ^ mm) {Please read the precautions on t-page before filling out this page) Binding: Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs and Consumer Cooperatives _7 __Β7__ 5 2. Description of the invention (f) Therefore, it is necessary to maintain a small quiescent current to avoid the consumption of standby power in a dynamic random access memory (DR AM) chip. Therefore, the design of the circuit must keep the sustain current (Standby Cuirent) within a certain range and reduce the cost of maintaining power in the chip. Referring again to FIG. 2, FIG. 2 shows a typical reference plate voltage (VP) generator 10, which is a circuit used in conventional dynamic random access memory (DRAM) to generate a reference plate voltage VP. Generally speaking, if the quiescent current is large, the output impedance of the reference plate voltage (VP) generator 10 is lower and has a higher drive capability; otherwise, the reference plate voltage (VP) generator 10 The output impedance is higher and it has lower driving capability. The reference plate voltage (VP) generator 1G includes a bias circuit 12 and an output circuit 14. The bias circuit 12 is composed of transistors P10, N10, P16, and N17. The output circuit 14 is composed of a transistor P11 and Nil. The bias circuit 12 provides an appropriate bias voltage to the output circuit 14 and causes the reference plate voltage (VP) generator 1G to generate a predetermined memory cell electrode voltage VP. Among the transistors P 10 and N 17 The size ratio is used to determine the level of the reference plate voltage VP, and the size ratio of the transistors N1G and P 16 (relative to the transistors P 10 and N 17) is used to determine the output The circuit 14 can provide the quiescent current of the reference plate voltage (VP) generator 10. This paper size applies to Chinese National Standard (CNS) A4 (210 X 2 mm) (Please read the notes on the front of the page before filling in this page) Binding · A7 B7 V. Description of the invention (/) (Please first (Please read the notes on the back and fill in this page.) When the memory is accessed, all the memory cells connected to the "selected" character line will be enabled and the data will be stored through the corresponding bit line. Take action. That is, once the corresponding access transistor is turned on, the current on the bit line can charge or discharge the storage capacitor of the "select" memory cell, that is, the current surge can flow out during the read / write cycle / Into the storage capacitor. In order to avoid the consumption of Standby Power in the dynamic random access memory (D RAM) chip, the quiescent current must be kept small. However, this "low quiescent current characteristic" has caused a serious problem in the memory access process. problem. As mentioned above, because the output impedance of the reference plate voltage (VP) generator 10 is high and the driving capability is extremely small, it cannot provide sufficient current to charge / discharge the storage capacitor. Therefore, voltage noise occurs in the memory cell voltage. Noise generated during memory access, especially negative noise, is prone to interfere with data in memory units that are not accessed by the memory. The Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs has printed a memory unit that has not been accessed. The gate of the access transistor is connected to a grounded word line so that the access transistor is turned off; therefore, unless The access transistor is turned on, and the negative voltage noise (lower than the normal reference plate voltage VP) on the electrode of the memory cell cannot charge or discharge the storage capacitor. The access transistor in the memory cell is turned off, so that the voltage at the other end of the storage capacitor rises and falls with the noise of the electrode terminal of the memory cell, and the stored value in the access transistor that has not been accessed by the memory is When the logic state is "low" or "0", and the noise is higher than the starting voltage of the access transistor, the access transistor will be turned on, so that the current on the connected bit line is directly applicable to China. National Standard (CNS) A4 specification (210 X 2 in mm) 434'fli A7 ____B7 _ 5. Description of the invention (L) flows into the storage capacitor and further disturbs the data in the memory unit. Even though the intensity of the noise is small, the sub-threshold current on the access transistor will still increase β. Please refer to Figure 7. Figure 7 is a waveform diagram generated by conventional technology. Among them, The data stored in the first memory unit (CELL1) and the second memory unit (CELL2) shown in Fig. 1 are "1" (the potentials of D1 and D2 are high voltage sources VDD), the third memory unit (CELLG) and the first memory unit The data stored in the four memory cells (CELL3) is "0" (the potential of D0 and D3 is the ground voltage (GND)). Generally, before the start of the access cycle, the potential of each bit line is 1 / 2VDD. When the word line WLG is selected, the corresponding access transistors N1 and N2 are turned on. Because the potentials of D 1 and D 2 are VDD, and the potentials of bit lines BLG and BL 1 are 1/2 V]) D, the discharge current flows from D 1 and D 2 to the bit lines BL0 and BL1, respectively. When the voltage levels are the same, the discharge current will stop. Due to the low drive capability of the reference plate voltage (VP) generator, the discharge current will generate a voltage surge. Since the discharge current flows from D 1 and D 2 to the bit lines BLG and BL 1, the potentials of D 1 and D 2 decrease, and the reference plate voltage VP is lower than a normal value. When the reference plate voltage VP decreases, the potentials of D 0 and D 3 are lower than the ground potential. Therefore, although word line 1 is not selected, negative noise (below the normal reference plate voltage) will turn on the transistors NO and N3 that are not accessed. In view of this, there are two common methods to solve the interference effect caused by the negative noise of the memory cell electrodes. The first is to use an access transistor with a high threshold voltage VT to increase the tolerance of the access transistor to negative noise (Noise. Li> 4d4ii§ _____B7_____ 5. Description of the invention (7)

Margin), but the access transistor slows down the memory access speed. The other is to add a negative voltage to the word lines that are not “selected” to reverse-bias the access transistor (Reverse-Bias). However, this method requires additional control of the decoding and decoding of each word line. Drive, waste more area and electricity. In U.S. Patent No. 5,734,603, a circuit and method for reducing memory cell electrode noise (Ceil Plate Noise) is disclosed. Its main purpose is not to lose access speed and does not require additional control. Under the circuit, reduce the noise of the electrode of the memory cell. Please refer to FIG. 3, which is a circuit diagram of a circuit 2G for reducing noise of a memory cell electrode disclosed in US Patent No. 5,734,603. The circuit 20 includes a comparison circuit 22, a sampling circuit 24, and a charging device 26. The comparison circuit 22 includes transistors PI, P0, N1, N0, and N2, the sampling and holding circuit 24 includes a capacitor and a PM0S transistor P2, and the charging device 26 includes a PM0S transistor P3. The comparison circuit 22 is a control element. Transistors P1 and P 0 provide a current mirror load to the differential transistor pair N1 and NG. Transistor N2 is a control transistor for enabling. Or fail (0138 & 16) the comparison circuit 22. The PM0S transistor P 2 is connected between the capacitor and the reference electrode voltage VP, and is controlled by the uniform energy signal. The enable signal in the dynamic random access memory can be used to determine the state of the memory access. Since the memory cell electrode noise occurs during memory access and is predictable, the enable signal can be arranged at a "low" level when the memory access is not performed. The paper standard is applicable to Chinese national standards (CNS > A4 specification (210 X 29f mm) 434S63 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs V. Invention description (y), the comparison circuit 22 is closed at this time, so it will not cause static current in the DRAM. When the enable signal is in the "low" logic state, the transistor P 2 of the sampling circuit 24 is turned on, so that the source voltage and the drain voltage are the same, which is the normal memory cell electrode voltage VP. Because no current flows from the memory unit or The voltage of the memory cell is stable without noise. The sampling circuit 24 maintains a sampling voltage SVP, which is the same as the voltage of the electrode of the memory cell at a normal level when no memory access is performed. At this time, the The voltage of the electrode of the memory cell is sampled and stored as a reference voltage SVP. ^ Once any reading or writing operation is performed, the enable signal is converted to " Logic state, the comparison circuit 22 is turned on and the transistor P 2 is turned off, so that the sampling voltage SVP can maintain the normal level of the memory cell electrode voltage. Therefore, when the memory cell electrode voltage VP is generated by the memory access, the memory cell electrode noise is generated. At this time, the memory cell electrode voltage VP with noise can be compared with the stored sampling voltage. The comparison circuit 22 compares the captured sampling voltage SVP with the memory cell electrode voltage VP with noise and generates a node A The difference voltage corresponding to the noise of the electrode of the memory unit is used to judge the noise of the electrode of the memory unit. This difference voltage should be appropriately enlarged so that when negative noise occurs during access, the memory unit electrode voltage corrects the memory unit based on the difference voltage. When the electrode voltage is used to reduce the noise of the memory cell electrode, the sensitivity in the step of correcting the voltage of the memory cell electrode can be improved. (谙 Please read the notes on the poor side before filling in this page) Binding. Standard (CNS) A4 specification (210 X 2 # mm) A7 434563 B7 V. Description of the invention (7) The differential voltage of node A can be used to control The above-mentioned charging device 26 is controlled. When the difference voltage obtained by the node A indicates that the voltage of the memory cell electrode has negative noise, the transistor P 3 is turned on and can supply a current to the memory cell electrode of the storage capacitor to pull. Pull up the potential of the node, the aforementioned charging device 26 provides a temporary large current to the voltage of the memory cell electrode VP 〇 amplifies the difference voltage, that is, the noise of the electrode of the memory cell, and makes the transistor P controlled by node A 3 provides a current to the memory cell electrode voltage VP. At this time, the transistor P 3 provides a comparison circuit 22-a negative feedback path, so that the noise on the memory cell electrode voltage VP can be compressed accordingly. However, in US Patent No. 5,734,603, the circuit and method for reducing the noise of the memory cell electrode, although the voltage of the memory cell electrode can be sampled, the voltage of the memory cell electrode containing the noise and the stored sampling voltage can be compared and controlled. The charging device may cause excessive charging of the electrode unit voltage VP of the memory unit. (3) Brief description of the invention: In view of the lack of the conventional technology, the present inventor proposed a clamp circuit of a dynamic random access memory memory cell plate, which can effectively solve the invention of the lack of the conventional technology, namely: the present invention One object is to provide a clamp circuit for a dynamic random access memory memory cell tablet, which can solve the possibility of US Patent No. 5, 73i, 6G3 § the problem of overcharging the electrode voltage VP of the memory cell, and Reduce the electrode noise of the memory unit. [illi—1 ----- (Please read the precautions for face-free, and then fill out this page) M6 r4 · Printed on the paper by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, the paper size applies to the Chinese National Standard (CNS) A4 specification (210 X 2 Cai Gong Chu) 4345 6 3 A7 B7 V. Description of the invention (丨 ο) Another object of the present invention is to provide a clamp circuit for a dynamic random access memory memory cell plate, which can solve the negative and negative electrode of the memory cell. The interference problem caused by noise is avoided to avoid the use of negative noise to turn on the transistor that has not been accessed. Another object of the present invention is to provide a clamp circuit for a memory cell panel of a dynamic random access memory, which can avoid the loss of memory access connectivity that is reduced by the conventional access transistor, and does not require additional control circuits. Causes waste of area and electricity. In order to achieve the above-mentioned object, the present invention is a clamp circuit for a dynamic random access memory memory cell plate. The clamp circuit mainly includes a control circuit and an output circuit. The control circuit is connected to the output circuit for clamp reference. Flat voltage level, the output circuit has high driving ability, and is controlled by the control circuit to maintain the voltage level of the reference flat voltage at a normal value. The present invention is particularly suitable for embedded dynamic random access memory In the body, the stability of the reference plate voltage VP can be maintained. In order to allow your reviewers to further understand and understand the features, objectives, and effects of the present invention, the detailed description with the drawings is as follows: (4) Brief description of the drawings: Figure 1 shows a dynamic random Schematic diagram of memory cell array in access memory. Figure 2 is a circuit diagram of a typical reference plate voltage (VP) generator. This paper size applies to China National Standard (CNS) A4 specifications (210 X 2 mm) Packing-< please read the business matters on t side and fill in this page) 434563 A7 _B7__ V. Description of the invention (1 /) Figure 3 is a circuit diagram showing a circuit for reducing the noise of a memory cell electrode in US Patent No. 5,734, 6 (33). Figure 4 is a preferred implementation of the present invention The block diagram of the relationship between the clamp circuit and the flat voltage (VP) generator of the memory cell in the example. Figure 5 is the first circuit diagram of Figure 4 which shows the circuit diagram of the first clamp circuit. Figure 6 is the second of Figure 4 Circuit diagram, which shows the circuit diagram of the second clamp circuit. Figure 7 shows waveforms generated by conventional technology. Figure 8 shows waveforms generated by the clamp circuit of the present invention. Figure No. Description: ---- ------- Install --- (Please read the precautions on f-page and then fill out this page> Printed by SA Consumer Products Cooperative Society of Intellectual Property Bureau of Ministry of Economic Affairs SA Sense Amplifier S AE Sense Amplifier Enable Signal OB , BLG, BL1B, BL1 bit line rule, WL1 word line CELL1 Cell CELL2 Second memory cell CELLO Third memory cell CELL3 Fourth memory cell N1 First transistor N2 Second transistor NO Third transistor N3 Fourth transistor 10 Panel voltage (VP) generator This paper is applicable to China Standard (CNS) A4 specification (210 = < 2 good mm). Q ·

4S4SII A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economy V. Invention Description (>) 12 14 P0-P3, P10, P11, P16 N0_N2, N10, N11, N16 20 22 24 26 30 32 34 50 60 70 80 INVO 'INV1 R0, R1 P21, P25, P35 N21, N25, N35 bias circuit output circuit PMOS transistor NMOS transistor circuit to reduce electrode noise comparison circuit sampling circuit charging device I flat voltage (VP) clamp circuit First clamp circuit Second clamp circuit Control circuit Output circuit Control circuit Output circuit Inverter word line PM0S transistor NM0S transistor (5) Detailed description of the invention: The invention is mainly a dynamic random access memory Please refer to Figure 4, Figure 5, Figure 6 and Figure 8 for the clamp circuit of the body memory unit plate. It is drawn from paper, and it is extracted from China Solid Macro Standard (CNS) A4 (210 X 2). 1 Speech f- Read Back-Refill 1 item Binding 4 3 4Ϊ β Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 5. The description of the invention (M) shows the silver voltage level according to the embodiment of the present invention The circuit is detailed below with reference to the drawings A detailed description of the preferred embodiment of the clamp circuit of the dynamic random access memory memory cell plate of the present invention. [Preferred embodiment] First, the first memory cell of the memory cell array in the dynamic random access memory ( The data stored in CELL1) is "1" (the potential of D1 is the voltage source VDD), and the data stored in the third memory unit (CELLG) is "0" (the DO potential is the ground voltage), please refer to Figure 1. When the word is selected When the element line WLQ is turned on, the corresponding access transistors N1 and N2 are turned on. The potential of the word line WLG rises from the ground voltage, the current flows from D 1 to the bit line BLO, the potential of D 1 decreases, and the potential of the bit line BL0 rises, D The voltage drop of 1 will reduce the reference plate voltage VP. As the reference plate voltage VP drops, the D0 potential will be lower than the ground potential, please refer to Figure 7 "Bit line BLG and reference plate voltage VP and bit line BLOB and There is a parasitic capacitor between the reference plate voltage VP. The rise of the potential of the bit line BLG and D 1 will increase the reference plate voltage V3P, and the drop of the potential of the bit line BLGB will cause the reference plate voltage VP to decrease. Therefore, the reference plate voltage VP is not In order to eliminate the variation of the reference plate voltage VP, before the word line WL0 is turned on, the clamp lead circuit is started to clamp the reference plate voltage VP voltage level. However, after the sensing process is completed, the clamp circuit is stopped to reduce Sustain current to avoid sustaining power consumption in dynamic random access memory (DRAM) chips (t read the precautions on r side before filling out this page)

The test of P is made by: the pain of Shi Puhan, the ancient border, f, the wide range, oin w oA4 \ 434iif, printed by B7 of the Consumers ’Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of the invention (丨 f) Dynamics of the preferred embodiments of the present invention The clamp circuit of the RAM memory cell plate is a simpler solution. In memory access, the clamp circuit clamps the voltage level with the clamp circuit, no additional control circuit is needed, and the circuit can be reduced. The wiring area does not cause excessive charging of the memory cell plate voltage VP. Please refer to FIG. 4, which shows the interaction between the memory unit plate voltage σ) generator 10 and the plate voltage (vp) clamp circuit 30 in the preferred embodiment of the present invention in the form of a block diagram. The plate voltage (VP) clamp circuit 3 0 is connected to the memory unit plate voltage (VP) generator 10, and the clamp refers to the voltage level of the plate voltage VP. The circuit diagram of the first clamp circuit 32 in the embodiment of the present invention refers to the voltage level of the flat panel voltage VP. As shown in FIG. 5, the first clamp circuit 32 includes a control circuit 50 and an output circuit. 60, the control circuit 50 has resistors R0, R1 and an inverter INV1, and the output circuit 60 has a PMOS transistor P35 and an NMOS transistor N35. The NM0S transistor N 3 5 is connected between the resistor R 1 and the ground voltage, and is controlled by a clamp signal; the PM0S transistor P 3 5 is connected between the resistor R 0 and the voltage source VDD, and the molybdenum signal And inverter INV1 control. Among them, the PMOS transistor P 3 5 and the NMOS transistor N 3 5 are selected from large-sized transistors, so that they have a high driving capacity. Before the potential of the word line WL0 rises, the controlled clamp signal is set to a "high" logic state. However, when the clamp signal is in the "high" state, the PM0S transistor P 3 5 and the NMOS transistor N 3 5 are turned on synchronously, and the first clamp circuit 32 is activated. (Please read the precautions of Jingshen Noodle before filling in this page)-; Install i — 丨 ____Order, 丨 ------ Ann 4β Feng / Guang MCYAyl Progressive 01/01 / ν, 434§Tooth§ A7 __; _ B7

V. Description of the invention (/ iO By adjusting the resistors R 0 and R1, the voltage level of the reference plate voltage VP can be maintained at a normal level. The first clamp circuit is used to perform memory access operations. At this time, the charge / discharge reference plate voltage VP is clamped to the level of the reference plate voltage VP, and the voltage level of the reference plate voltage VP is maintained at a normal value. After the sensing process is completed, the control clamp signal is set to "low" Logic state, PM0S transistor P 3 5 and NM0S transistor N 3 5 are turned off, the first clamp circuit 3 2 stops operating, reduces the maintenance current, and avoids the power consumption of the dynamic random access memory (DR AM) chip. Please refer to FIG. 6 again, which shows a circuit diagram of the second clamp circuit 34 in the embodiment of the present invention, in which a resistor is used to replace the resistance of the first clamp circuit 32 shown in FIG. 5. As shown in the figure, the second clamp circuit 34 includes a control circuit 70 and an output circuit 80. The control circuit 70 has a PM0S transistor P 2 1, an NM0S transistor N 2 1 and an inverter INV0. , The output circuit 8 0 has PM0S transistor P 2 5, NM0S Crystal N2 5. NM0S transistor N 2 5 is connected to PM0S transistor P 2 1 and printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economics and Grounding. I nn H] ϋ ^^ ίίν — — I 1 (谙 4? Read the back (Notes for filling in this page)

Pressure and controlled by a clamp signal. The PM0S transistor P 2 5 is connected between the voltage source VDD and the NM0S transistor N 2 1 connected to the PM0S transistor P 2 1, and is controlled by the clamp signal and the inverter IM0. The PM0S transistor P 2 1 is the same as the PM0S transistor P 1 1 and is controlled by a CP signal. The transistor N 2 1 is the same as the transistor N 1 1 and is controlled by a CN signal. Among them, PM0S transistor P 2 1, P 2 This paper size is applicable to Chinese national standard (CNS > A4 specification (210 X 29 ^ gongchu)) 5. Description of the invention (/ 厶) 5 and NMOS transistor N 2 1, N 2 5 Select a large-sized transistor to make it have a higher driving capacity. When the clamp signal to be controlled is set to a "high" logic state, the PMOS transistor P 2 5 and the NMOS transistor N 2 5 are turned on, and the second clamp The circuit 3 4 operates. By turning on the transistor, the reference plate voltage VP can be controlled to maintain the voltage level of the reference plate voltage VP at a normal level. When the second clamp circuit is used, the clamp reference plate voltage VP level, keep the reference plate voltage VP voltage level at normal value. After the sensing process is completed, change the control signal to "low" logic state, PMOS transistor P 2 5 and NMOS transistor Ν 2 5 is closed, the second clamp circuit 34 is stopped, the maintenance current is reduced, and the power consumption of the dynamic random access memory (D RAM) chip is avoided. Finally, please refer to FIG. 8, which illustrates the use of the present invention Waveform generated by the clamp circuit 3 0 The data stored in the first memory cell of the memory cell array is “1” (the potential of D 1 is the voltage source VDD), and the data stored in the third memory cell (CELLO) is “0” (the potential of D 0 is the ground ⑽ D) Voltage) ° Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. When the character line WL0 is selected, the corresponding access transistors N1 and N2 are turned on. The clamp signal rises to the "high" logic state, the potential of the word line WLG also rises from the ground voltage, and the current flows from D 1 to the bit line BLG. The potential of D 1 decreases, and the potential of the bit line BL0 rises. Before the word line WLQ potential rises, the control clamp signal is in a "high" logic state, the clamp circuit 30 operates, and the charging / discharging refers to the plate voltage VP, and the clamp references the plate voltage to the middle level, maintaining the reference plate. The Zhang scale applies to the Chinese National Standard (CNS) A4 specification (210 X 2 # / ^ ali) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 434563 A7 ______B7 V. Description of the invention (7) The voltage level of the voltage VP is normal value. After that, the clamp signal to be controlled is set to a "low" logic state to stop the operation of the clamp circuit 30. Because the clamp circuit 30 is controlled by the clamp signal, the clamp reference plate voltage VP level, so the voltage drop of D 1 cannot reduce the reference plate voltage VP, and the reference plate voltage νρ will not be caused by the bit line BLG. The rising or falling of the bit line BLOB changes up and down, so that the voltage level of the reference plate voltage VP is maintained at a normal value. At the same time, the D o potential will not drop below the ground potential. The invention has a simpler design and is particularly suitable for embedded dynamic random access memory (DRAM). Because the number of memory cells hung by bit lines is small, only about 3 or 64 are available. With less parasitic capacitors and the reference plate voltage VP is relatively unstable, the voltage level of the reference plate voltage VP can be clamped by a clamp circuit to maintain the voltage level of the reference plate voltage VP at a normal value. The clamp circuit of the above-mentioned dynamic random access memory memory cell plate fully shows the progressiveness of the purpose and efficacy of the present invention, which is of great value for the industry and is unprecedented in the market. The invention fully meets the requirements of the invention patent, and the application is filed according to law. The above are only the preferred embodiments of the present invention, and it should not be used to limit the scope of implementation of the present invention. That is to say, all equal changes and modifications made according to the scope of the patent application of the present invention should still fall within the scope of the patent of the present invention. I ask your reviewers to make a clear reference and pray for it. 0 This paper is applicable to the country of China. Standard (CNS) A4 specification (210 X 2 sand mm) — — — III — — — — l · I · 11 (please 'read Jing's business matters before filling out this page): Order .. ο

Claims (1)

D A8 B8 C8 D8 6. Scope of patent application 4. A clamp of a dynamic random access memory memory cell plate (please read the precautions on the back before filling this page), which includes a control circuit and an output Circuit, the control circuit is connected to the output circuit to clamp the reference plate voltage level, and the output circuit has a high driving capability "and is controlled by the control circuit to maintain the voltage level of the reference plate voltage at normal 2. The clamp circuit of a dynamic random access memory memory cell plate as described in item 1 of the scope of the patent application, wherein the control circuit further includes two resistors, and the resistors are adjustable. 3 . The clamp circuit of the dynamic random access memory memory cell plate according to item 2 of the patent application scope, wherein the control circuit further includes an inverter, and the inverter can be used to invert a clamp signal. 4. The clamp circuit of a dynamic random access memory memory cell plate as described in item 1 of the scope of patent application, wherein the output circuit further includes a switching element, The switching element is controlled by a clamp signal to be turned on / off. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. The clamp circuit of the dynamic random access memory memory cell tablet as described in the patent application No. 4 Wherein, the switching element further includes two transistors, and when the transistor is turned on, the clamp circuit moves X f = φ. 6. The dynamic random access memory described in item 3 or 5 of the scope of patent application The clamp circuit of the body memory unit plate, wherein the control circuit includes an inverter for inverting a clamp signal, and the paper size of the switch element is applicable to China National Standard (CNS) A4 (210X 7) (Mm) A8 B8 C8 D8… tlf patented patent contains two transistors to control the action of the clamp circuit. 7 · Dynamic random access memory memory unit as described in item 6 of the scope of patent application A clamp circuit of a flat plate, wherein the transistor system is a PMOS mold crystal and an NMOS transistor, and the clamp signal controls the NMOS transistor, and is controlled by the inverter to invert the PMOS transistor. Body 8—A clamp circuit of a dynamic random access memory memory unit plate, which includes a control circuit and an output circuit, the control circuit is connected to the output circuit, and is configured with a plurality of transistors for clamping With reference to the plate voltage level, the output circuit has high driving ability and is controlled by the control circuit to maintain the voltage level of the reference plate voltage at a normal value. 9 · Dynamic randomness as described in item 8 of the scope of patent application A clamp circuit for accessing a memory memory cell plate, wherein the control circuit further includes an inverter, the inverter can be used to invert a clamped molybdenum signal. 10. As described in item 8 of the scope of patent application The clamp circuit of the DRAM memory cell plate, wherein the output circuit includes two transistors, and the clamp circuit is in operation when the transistor is turned on. 11. The clamp circuit of a dynamic random access memory memory cell plate according to item 9 or 10 of the scope of patent application, wherein said control circuit includes an inverter for inverting a clamp signal, said The transistor system is a PMOS transistor and an NMOS transistor. Please read the cautions before filling in this page.) 4J · Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X He 7 male f '434S83 A8 B8 C8 D8. 6. Apply for a patent Fan State signal to control the NMOS transistor to turn on / Closed, and inverted by the inverter, to control the PMOS transistor on / off. (Please read the precautions on the back before filling out this page) -install., Tx. The paper size printed by the consumer cooperative is applicable to China's national standards (CNS > A4 now (210X2397 mm)