TW527536B - Method to trace in system on chip architecture - Google Patents

Method to trace in system on chip architecture Download PDF

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Publication number
TW527536B
TW527536B TW89107346A TW89107346A TW527536B TW 527536 B TW527536 B TW 527536B TW 89107346 A TW89107346 A TW 89107346A TW 89107346 A TW89107346 A TW 89107346A TW 527536 B TW527536 B TW 527536B
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Taiwan
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data
tracking
interface
trace
priority
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TW89107346A
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Chinese (zh)
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Dirk Amandi
Winfried Glaeser
Alexander Mircescu
Robert Winter
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Siemens Ag
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    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/36Preventing errors by testing or debugging software
    • G06F11/362Software debugging
    • G06F11/3636Software debugging by tracing the execution of the program

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Debugging And Monitoring (AREA)

Abstract

In a system on chip arrangement, the data states of a plurality of components are tested, selected, and it is provided with a source identifier and a time stamp, and the data gather together according to their priorities and are distributed to an interface so that it can be utilized. The width of the trace interface (the number of pins on the chip) and the complexity of the tracer are minimized.

Description

527536 A7 _B7^____ 五、發明說明(i ) 本發明的目的是有關一種方法以追蹤在一裝置中的資 料及其狀態,在其中的半導體晶片(SoC)具有多個元件。 在晶片上糸統(SoC,System on Chip)的結構中是在晶 片上設置有不同的元件,例如微處理器、隨機存取記億 體(RAM)、與複雜的硬體(HW)控制邏輯。為了測試SoC設 計,是絶對必要能夠在晶片中”向裡面看”,即追蹤内部 資料流。為了符合测試的要求,通常必須各個元件的資 料流,可以平行地(即,以精確的彼此之間時間的關係) 而追蹤。 截至目前為止,此少量資料流的平行穿過繞線,例如 只有一個記億體界面在追蹤匯流排上即足夠,並且由複 雜至可能。此晶片上条統(S 〇 C )結構增高的複雜性使得 追蹤多個元件是值得要求在追蹤匯流排上各個元件界 面之平行穿過繞線,首先顯得在實際上不可能。 本發明的目的以此問題為基礎,其規範說明一種方法 其藉由將追蹤的複雜性減至最小,而在追蹤匯流排上追 蹤多個在晶片上条統(SoC)之元件。 此問題藉由申請專利範圍第1項之特徽而達成。 本發明之目的是,使用此理解,例如在RAM界面上在 -------------------訂----------線 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 環 循 候 等 在 潛 此 由 0 中 令 指 取 讀 η 候 等 此 〇 在置 且位 並問 訊 的 資他 蹤其 追至 含導 包傳 要鑛 須繼 \ 以 趣可 興訊 有資 沒蹤 其追 , 中 在璟 存循 利 有 為 是 的 S 目的 之多 明能 發可 本儘 供 件 元 數 總 的 腳 接 上 片 晶 提在 κ(\ 以 可 料 資 的 上 面 界 蹤 追 在 度 寬 的 面 界 蹤 追 將 時 同 且 並 器 蹤 追 此 上 本 基 在 及 以 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 527536 A7 B7 五、發明說明(2 ) 的複雜度減至最小。此外,由於外部媒體(硬體追蹤器 HWT )追蹤深度的限制,則將資料減少為有利。 (請先閱讀背面之注意事項再填寫本頁) 本發明目的之其他有利的發展,是於申請專利範圍附 屬項中説明。 本發明之目的是以下作為實施例,在對理解所必須的 範圍中,根據圖式作進一步的説明,其顯示: 圖忒之簡g說明 第1圖是根據本發明之追蹤条統之説明。 第2圖是在根據本發明之追蹤条統中的流程圖,以及 第3 p是在根據本發明之追蹤条統中之另一値流程圖。 在這些圖式中相同的符號代表相同的元件。 在追蹤之中的是在某個詢問位置T A P (代表:追蹤接達 點)上資料狀態的詢問以理解資料狀態的蓮用。 第1圖顯示一在晶片上条統裝置S 〇 C ,在其中實現本 發明之目的,在此晶片上条統(S 〇 C )的結構中在晶片上 配置不同的元件,例如微處理器。RAM,以及複雜的硬 體(HW)控制邏輯。 經濟部智慧財產局員工消費合作社印製 此在第1圖中的裝置具有代表用於多個元件對於未進 一步説明的元件A、B、C與D其所屬的詢問位置T A P A、 TAPB、TAPC、TAPD。用於此追蹤方法之可能的SoC資料 之追蹤點為: -微處理器核心(processor kernels), -記億體元件(RAM, storage elements), -硬連線磁蕊元件,控制零件,膠#邏輯, -4 - 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 經濟部智慧財產局員工消費合作社印製 527536 A7 B7_ 五、發明說明(3 ) -匯流排界面(bus interface), -感測器界面(sensor interfaces), -至周邊部份界面, -積體化之場可程式閘極陣列(F P G A s ) ( F i e 1 d Programmable Gate Array)〇 此詢問位置的資料是由一觸發裝置TR (代表:Trigger) 所提供,它在某一個条統參數接通或切斷時(例如當滿 足錯誤之條件時,接通此觸發器)提供此追蹤。此經由 觸發裝置而偵測的資料a 1 ... a 6、b 1——b 4、c 1 . · . c 4 與dl——d4是由各個過濾器FI所提供,在那裡它相對應 於測試的要求取決於某個糸統參數而被選擇。此所選擇 的資料al...a4,bl...b3,cl、c4與dl、d2是在來源辨 識器,SI中(代表:source identifier)稱作為有關的 元件。 時間間隔控制器TSC(Time slot control)每一時鐘周 期一個接一個地相對應其TAP的優先權而詢問所須的資 料〇 (此u所須”是經由T A P之信號位元而顯示)。此所須 的TAP資料是以來源辨識器提供。因此在處理後之晶片 外之TAP資料可以再被列入(總括於特別的資料,表格, 統計數字、等之中)。另外設置3時間標記(time stamp) (例如是一個蓮轉計數器的計數值)。這些資料,其於相 同的時間周期中施加,得到相同的時間標記,並且相對 應其優先權被提供追蹤一資料記億體TD FIF0(追蹤資料 先進先出)(Trace Data First In First Out)。因此在 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) --------------------訂---------線 (請先閱讀背面之注意事項再填寫本頁) 527536 A7 _B7_ 五、發明說明(4 ) 處理後可以將時間順序正確的算出。若畤間標記作為蓮 轉的計數器而實現,當此追蹤資料記億體沒有施加湓流 狀態(ον)(溢流先進先出狀態)(overflow FIFO state) 時,則出現此時間間隔控制器在每一個計數器返回 (return)中,使用一保持活性狀態字元(keep alive Trace Word)(例如以Si=0)。此還是有利的是當在重設 (R e s e t )後活化此追蹤器,因為以收到此保持活性狀態 字元已經證實連接的建立。在將追蹤字元遞交給追蹤資 料記億體T D F I F 0期間,若出現溢流先進先出狀態,因 此此字元沒有傳送,而傳送具有最高優先權的TAP追蹤 字元是在原則上一直可能〇當資料損失時(第1圖.·如 同以D L d 2來表示:資料損失d 2 )經由溢流,此狀態經由 在追蹤字元中的溢流位元而表示其特徵,這還可以在溘 流狀態中傳送,並且如同此未傳送的追蹤字元具有相同 的時間標記(第1圖:此追蹤字元具有d 2之前的a 3 )。還 有在湓流狀態中,此傳送每値時脈週期的追蹤字元總是 可能〇當在沒有T A P的時脈周期(c 1 〇 c k c y c 1 e )中必須置 放資料時,此F I F 0的溘流狀態於是減少,而可以撤消溢 流位元。 -------------衣--------訂---------線 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 在個 是 一 中每 元在 字 , 蹤中 追置 於位 入此 插在 元是 位FO 流FI 溢此 將 〇 及行 以進 理中 管FO 之FI FO料 FI資 此蹤 追 TA每 於 , 應示 對顯 相圖 期 1 周第 脈 〇 時中 於 存 儲 元 字 蹤 追 將 而 數 總 的 在 多 至 期 周 脈 時 個 存 儲 中 當 權 先 優 其 應 對 相 此 因 元 字 蹤 追 個 三 此 在 時 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 經濟部智慧財產局員工消費合作社印製 527536 A7 _B7_ 五、發明說明(5 ) al、bl、cl/dl。在FIFO的出口是每一個時脈周期將一 追蹤字元寫在追蹤界面TI (代表Trace Interface)上,其 與硬體追蹤器(HW追蹤器、標準追蹤裝置)相一致。此逍 蹤界面TI是具有在殼體上形成的多個端子,其容納SoC 元件。此追蹤界面ΤΙ的端子總數是明顯地較,當對於殼 體的一個分別的界面上之多個追蹤點T A P A ... T A P D的每 一個配置時少。 經由一値在硬體追蹤器H W T上的P C界面,可以使用程 式作處理後之使用。 在根據本發明目的的追蹤方法/算法中是介於必要 與非必要的追蹤資料之間相對應於測試的要求而區分 (資料選擇)。一個合理的資料選擇在事實上是原則上一 直可能。因此其為可能,在時間間隔(T i hi e S 1 〇 t )的方法 中,此不同的SoC元件之所施加必要的追蹤資料在追蹤 匯流排上一個接一個地産生。此時間資訊藉由使用時間 標記(tirae stamp)而完全保存,因此資料的時間行為彼 此在處理後中可以再度産生。此在FIFO中順序資料的中 間儲存儘可能地將資料爆增(D a t a B u r s t )櫥截。藉由可 調整的過濾器與觸發點而在必要資料中達成資料的減少 。在基本上是可能,將任何數目不同的SoC元件以時間 間隔(t i m e s 1 〇 t )法追蹤,其中的時間間隙經由優先權 詢問原則(polling)而給予。當在統計的方法中,SoC元 件資料流的總和超過追蹤界面的傳送率,則發生資料損 失〇此具有最高優先權的SoC元件的追蹤字元(word)在 一 Ί 一 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) --------------------訂---------線 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 527536 A7 __B7__ 五、發明說明(6 ) 每一種情況中傳送。 第2圖顯示此追蹤方法的迫蹤算法。 在201中是算法的開始,在202中是將所有設置於開始 狀態中(reset all)。在203中是一個根據第3圖的程序 以執行處理具有優先權1的追蹤點(processing TAP w i t h p r i ο 1 )。在2 0 4中是一個根據第3圖的程序以執 行具有優先權2追蹤點之處理(processing TAP with prio 2)。在205中是一個根據第3圖之另外的程序,以 執行處理一此追蹤點。在2G6中是一個根據第3圖的程 序以執行處理具有優先權N的追蹤點(p r 〇 c e s s i n g T A P v/ith prio N)。在207中更新此時間標記(update time s t a m p )。在2 0 8中是執行一詢問,是否此時間標記己達 到其最高狀態(timestanip=niax?)。若此非此種情形, 則以N表示(代表N 0 ),而在2 1 1中繼續。若是此種情形 ,則以Y表示(代表Y E S ),而以2 0 9繼續。在2 0 9則被詢 問是否。追蹤資料記億體F I F 0 T D之F I F 0沒有溢流(N 0 FIFO overflow)。若此以N表示,則沒有此種情況,而 以2 1 1繼籲。若此以Y表示,則有此情形,而在2 1 0中將 保持活性狀態字元寫入計算資料- FIF0(write keep alive t o F I F 0 )。在2 1 1中此”最老”的一單資料由追蹤資料F I F 0 至追蹤界面ΤΙ繼續傳導(將最後的FIFO資料寫入蹤界面) (write lowert FIFO entry to trace interface)。在 212中則等待下一個時脈周期開始(wait for next clock cycle〉,以便在201中繼績。 -8 - 本紙張尺度適用中國國家標準(CNS)A4規格(210 χ 297公釐) -----------· --------訂 -------- (請先閱讀背面之注意事項再填寫本頁) 、 527536 A7 _B7_ 五、發明說明(7 ) 第3圖顯示具有給定優先權之追蹤點之處理(processing T A P w i t h p r i ο N )。在3 0 1中開始之後則在3 0 2中被詢問, 是否已施加追蹤點資料。若這不是此種情況(沒有),則 以N表示,而以3 0 9繼續。若是此種情形(有)則以Y表 示,而以3 0 3繼續。在303那裡被詢問,是否追蹤資料FLF0 沒有溘流(η 〇 F I F G 〇 v e r f 1 〇 w ?)。若這不是此種倩形, 別以N表示,而以3 0 9繼續。若是此種情形,則以Y表 示,而以3 0 4繼續,在那裡將追蹤資料寫入追蹤字元N (將T A P資料寫入追蹤字元N )。在3 0 5中將來源辨識器S I 加上追蹤字元 N (add source identifier totrace word N)。在306中將時間標記加上追蹤字元N(add time stamp to trace word N)。在307中將追蹤字元N寫入追蹤資 料 FIFO(writ.e trace word M to FIFO)。在 308 中將追 蹤資料FIFO的狀態更新(update FIFO state)〇在3G8中 則返回(g 〇 b a c k )。 在此所介紹的方法是由一同步的晶H上条統(S o C )設 計開始。然而在基本上還可以連接此時脈同步蓮作的時 間間隔控制器與非同步的元件,並且然後以時脈周期蓮 作。 經濟部智慧財產局員工消費合作社印製 符號之説明 FI........過濾器 SI........來源辨識器 S 〇 C.......半導體晶片527536 A7 _B7 ^ ____ V. Description of the Invention (i) The purpose of the present invention is a method for tracking data and its status in a device in which a semiconductor chip (SoC) has multiple components. In the system on chip (SoC, System on Chip) structure, different components are arranged on the chip, such as a microprocessor, a random access memory (RAM), and complex hardware (HW) control logic. . In order to test the SoC design, it is absolutely necessary to be able to "look in" on the chip, that is, to track the internal data flow. In order to meet the requirements of the test, the data flow of the individual components must usually be tracked in parallel (ie, in a precise time relationship with each other). Up to now, this small amount of data flows through the windings in parallel. For example, only one physical interface is sufficient to track the bus, and it is from complex to possible. The increased complexity of the stripe structure on this wafer makes tracking multiple components worthwhile requiring parallel crossing of windings at the interface of each component on the tracking bus, which first seems practically impossible. The object of the present invention is based on this problem, and it specifies a method for tracking a plurality of components on a chip (SoC) on a tracking bus by minimizing the complexity of tracking. This problem was solved by applying for the special emblem of item 1 of the patent scope. The purpose of the present invention is to use this understanding, for example, in the RAM interface, order the ---------- line (please first (Please read the notes on the back and fill in this page again.) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, etc. Printed by the circle of waiting, etc. The order will be obtained by 0 Orders, etc. Waiting for this information. Tracing to the main mine with the guide package must follow \ Yiqu Ke Xingxun has nowhere to go after chasing it, and there are so many goals in the depository that can be used to make good progress. Connected to the film crystal in κ (\ with the upper boundary of the material can be traced to a wide range of surface traces to follow the same time and parallel traces. The basic and in accordance with this paper standard apply Chinese national standards (CNS ) A4 specification (210 X 297 mm) 527536 A7 B7 5. The complexity of the description of the invention (2) is minimized. In addition, due to the limitation of the tracking depth of the external media (hardware tracker HWT), the data is reduced to the advantage (Please read the notes on the back before filling out this page) Other advantageous developments for the purpose of this invention It is described in the appended item of the scope of patent application. The purpose of the present invention is as an example, in the range necessary for understanding, further explanation according to the diagram, which shows: Is a description of a tracking system according to the present invention. FIG. 2 is a flowchart in the tracking system according to the present invention, and FIG. 3 p is another flowchart in the tracking system according to the present invention. The same symbols in these drawings represent the same components. What is being tracked is the query of the data status at a certain query position TAP (Representative: Tracking Access Point) to understand the status of the data. Figure 1 shows a The strip device SOC is implemented on a wafer, in which the object of the present invention is achieved. In this structure of the strip system (SOC), different components such as a microprocessor, a RAM, and a complex are arranged on the wafer. Hardware (HW) control logic. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. This device in Figure 1 has a representative for multiple components. For components A, B, C, and D, which are not described further, their enquiries Bit TAPA, TAPB, TAPC, TAPD. The possible tracking points for SoC data used for this tracking method are:-microprocessor cores,-RAM, storage elements,-hard-wired magnetics Core components, control parts, glue # logic, -4-This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 527536 A7 B7_ V. Description of the invention ( 3)-bus interface,-sensor interface,-to peripheral interfaces,-integrated field programmable gate array (FPGA s) (F ie 1 d Programmable Gate Array) 〇 The data of this query position is provided by a triggering device TR (Representative: Trigger), which is turned on or off when a certain system parameter is turned on (for example, when the error condition is met, the trigger is turned on) Provide this trace. The data detected by the triggering device a 1 ... a 6, b 1-b 4, c 1. ·. C 4 and dl-d4 are provided by each filter FI, where it corresponds The test requirements are selected depending on certain system parameters. The selected data al ... a4, bl ... b3, cl, c4 and dl, d2 are in the source identifier, and the SI (representative: source identifier) is called the relevant component. The time interval controller TSC (Time slot control) inquires the required information corresponding to the priority of its TAP every clock cycle one by one (this required) is displayed via the signal bit of the TAP. This The required TAP data is provided by the source identifier. Therefore, the TAP data outside the processed chip can be included again (collected in special data, tables, statistics, etc.). In addition, 3 time stamps are set ( time stamp) (for example, the value of a lotus turn counter). These data, which are applied in the same time period, get the same time stamp, and are provided with a priority corresponding to their data. Trace Data First In First Out. Therefore, the Chinese National Standard (CNS) A4 specification (210 X 297 mm) applies to this paper size -------------- ------ Order --------- line (please read the precautions on the back before filling this page) 527536 A7 _B7_ V. Description of the invention (4) The time sequence can be calculated correctly after processing. If the intercalation mark is implemented as a counter of lotus rotation, when This tracking data indicates that when the flow rate (ον) (overflow FIFO state) is not applied to the billion body, this time interval occurs. The controller uses a keep-alive function in each counter return. Keep alive Trace Word (for example, Si = 0). It is also advantageous to activate this tracer after resetting (Reset), because the connection has been confirmed to have received the keepalive status word Established. During the submission of the tracking character to the tracking data record billion TDFIF 0, if an overflow FIFO status occurs, this character is not transmitted, and the TAP tracking character with the highest priority is always transmitted in principle. Possibly. When the data is lost (Figure 1 ·· as represented by DL d 2: data loss d 2) via overflow, this state is characterized by the overflow bit in the tracking character, which can also be It is transmitted in the streaming state and has the same time stamp as the untransmitted tracking character (Figure 1: This tracking character has a 3 before d 2). Also in the streaming state, this transmission is Clock cycle It is always possible to track characters. When the data must be placed in the clock period (c 1 ckckc 1 e) without TAP, the flow state of this FIF 0 is reduced, and the overflow bit can be undone.- ------------ Clothing -------- Order --------- Line (Please read the precautions on the back before filling this page) Intellectual Property Bureau of the Ministry of Economic Affairs Employee consumer cooperatives print each word in a word, track it in place, insert it in this place, FO flow, FI overflow, will be 0, and follow the management of the FO's FI, FO, and FI. Every time you track TA, you should show the phase of the phase diagram in the first week at 0 o'clock in the storage element, and the total number of traces in the storage at most up to the period of the clock. The traces are in accordance with the Chinese standard (CNS) A4 specifications (210 X 297 mm) at this time. Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs and Consumer Cooperatives 527536 A7 _B7_ V. Description of the invention (5) , Cl / dl. At the exit of the FIFO, a trace character is written on the trace interface TI (for Trace Interface) every clock cycle, which is consistent with the hardware tracker (HW tracker, standard tracking device). This free interface TI is provided with a plurality of terminals formed on the case, which accommodate SoC components. The total number of terminals of this tracking interface T1 is significantly smaller than when multiple tracking points T A P A ... T A P D are arranged on a separate interface of the casing. Via the PC interface on the hardware tracker H W T, the program can be used for processing. In the tracking method / algorithm according to the purpose of the present invention, a distinction is made between necessary and non-essential tracking data corresponding to the requirements of the test (data selection). A reasonable choice of information is in fact always possible in principle. Therefore, it is possible. In the method of time interval (TihieS10), the necessary tracking data applied by the different SoC components is generated one after another on the tracking bus. This time information is completely saved by using a tirae stamp, so the time behavior of the data can be generated again after processing. This intermediate storage of sequential data in the FIFO pops up the data as much as possible (D a t a B ur s t). Reduce data in the necessary data with adjustable filters and trigger points. It is basically possible to track any number of different SoC elements at a time interval (ti m e s 100) method, where the time gap is given via the polling principle of priority. When in the statistical method, the sum of the data flow of the SoC components exceeds the transmission rate of the tracking interface, data loss occurs. The tracking word of the SoC component with the highest priority is in a paper standard applicable to China. Standard (CNS) A4 specification (210 X 297 mm) -------------------- Order --------- line (Please read the Please fill in this page again for attention) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 527536 A7 __B7__ V. Description of Invention (6) In each case. Figure 2 shows the pursuit algorithm for this tracking method. In 201, the start of the algorithm, and in 202, reset all. In 203 is a program according to FIG. 3 to perform processing on a tracking point with a priority of 1 (processing TAP w i t h p r i ο 1). In 2004, a program according to Fig. 3 is used to perform processing with priority 2 tracking points (processing TAP with prio 2). In 205 is another procedure according to Fig. 3 to perform processing of this tracking point. In 2G6 is a procedure according to Fig. 3 to perform processing of a tracking point with a priority N (p r c c s s i n g T A P v / ith prio N). This time stamp is updated in 207 (update time s t a m p). In 2008, a query is performed as to whether this time stamp has reached its highest state (timestanip = niax?). If this is not the case, it is represented by N (for N 0), and continues in 2 1 1. If this is the case, it is represented by Y (representing Y E S) and continues with 209. Asked at 2 0 9 whether to. The tracking data records that there is no overflow (N 0 FIFO overflow) in F I F 0 T D F I F 0 T D. If this is represented by N, this is not the case, and the call is continued with 2 1 1. If this is represented by Y, this is the case, and the keep alive character is written into the calculation data-FIF0 (write keep alive t o F I F 0) in 2 1 0. In 2 1 1 this "oldest" piece of data is transmitted from the trace data F I F 0 to the trace interface T1 (write the last FIFO data to the trace interface) (write lowert FIFO entry to trace interface). In 212, wait for the next clock cycle (wait for next clock cycle), so as to repeat the results in 201. -8-This paper size applies the Chinese National Standard (CNS) A4 specification (210 χ 297 mm)- --------- · -------- Order -------- (Please read the notes on the back before filling this page), 527536 A7 _B7_ V. Description of the invention (7 ) Figure 3 shows the processing of a tracking point with a given priority (processing TAP withpri ο N). After starting in 301, it is asked in 302 whether the tracking point data has been applied. If this is not the case In this case (no), it is represented by N, and it is continued as 3 0 9. If this is the case (if), it is represented by Y, and it is continued as 3 0 3. It is asked at 303 whether the tracking data FLF0 is not flowing. (Η 〇FIFG 〇verf 1 〇w?). If this is not the case, don't use N and continue with 309. If this is the case, use Y and continue with 304. Write the tracking data there to the tracking character N (write the TAP data to the tracking character N). Add the source identifier SI plus the tracking character N ( add source identifier totrace word N). Add time stamp to trace word N in 306. Write trace character N to trace data FIFO (writ.e trace word M in 307). to FIFO). In 308, the status of the tracking data FIFO is updated (update FIFO state). In 3G8, the status is returned (g 〇back). The method introduced here is a synchronized crystal H system (S o C) The design is started. However, it is basically possible to connect the time-interval controller of the pulse synchronization lotus and the non-synchronous components at this time, and then use the clock cycle to lotus. Description FI ........ Filter SI ........ Source identifier S 〇C ..... Semiconductor wafer

ΤΑΡΑ......追蹤連接點A -9 一 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 527536 A7 B7 五、發明說明(8 ) TAPD......追蹤連接點 器 制 控 面置記隔 界裝標間 蹤發間間 追觸時時 (請先閱讀背面之注意事項再填寫本頁) 果--------訂--------- 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐)ΤΑΡΑ ... Tracking connection point A -9 A paper size is applicable to Chinese National Standard (CNS) A4 specification (210 X 297 mm) 527536 A7 B7 V. Description of the invention (8) TAPD ... Tracking point device control surface setting compartment compartment labeling room tracking room tracking room (please read the precautions on the back before filling this page) Fruit -------- Order ----- ---- This paper is printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs, and the paper size applies to the Chinese National Standard (CNS) A4 (210 X 297 mm)

Claims (1)

527536 A8 B8 C8 D8 六、申請專利範圍 1· 一種追蹤在一裝置中之資料與其狀態之方法,其中一 半導體晶片(S 〇 C )具有多個元件,其待徽為: -一些追蹤點的資料(ΤΑΡΑ.…TAPD)依照一觸發裝置 (Τ Κ )而被偵測, -産生多個追蹤點, -此等資料依據過攄器(FI)的調整而被選擇, -此等資料具有所設的來源辨識器(S I )與時間標記 (t s ), -時間間隔控制器(T S C )詢問此等追蹤點, -此等資料繼續傳導至半導體晶片之追蹤界面(TI)上。 2 ·如申請專利範圍第1項之方法,其中 此時間間隔控制器依據其優先權而詢間迫蹤點。 3 ·如申請專利範圍第2項之方法,其中此等資料根據其 優先權繼續傳導至追蹤界面上。 4·如申請專利範圍第1-3項中任一項之方法,其中此等 資料作為時間標記,而具有所設之周期性繼續的計數 器狀態。 ------------IMW (請先閱讀背面之注意事項再填寫本頁) . I — II 經濟部智慧財產局員工消費合作社印製 -11- 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐)527536 A8 B8 C8 D8 6. Application for Patent Scope 1. A method for tracking data and its status in a device, in which a semiconductor chip (SOC) has multiple components, and its pending status is:-data for some tracking points (TAPA .... TAPD) is detected in accordance with a triggering device (TK),-multiple tracking points are generated,-this data is selected according to the adjustment of the FI (FI),-this data has the set Source identifier (SI) and time stamp (ts),-time interval controller (TSC) interrogates these tracking points,-this data continues to be transmitted to the tracking interface (TI) of the semiconductor chip. 2 · The method according to item 1 of the patent application range, in which the time interval controller queries the imperative point according to its priority. 3. The method as described in item 2 of the patent application scope, where such information continues to be transmitted to the tracking interface in accordance with its priority. 4. The method according to any one of claims 1 to 3, wherein the information is used as a time stamp and has a counter state which is set to continue periodically. ------------ IMW (Please read the notes on the back before filling out this page). I — II Printed by the Consumers' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs -11- This paper size applies to Chinese national standards (CNS) A4 size (210 X 297 mm)
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US7069176B2 (en) * 2003-08-07 2006-06-27 Arm Limited Trace source correlation in a data processing apparatus
US7149933B2 (en) * 2003-08-07 2006-12-12 Arm Limited Data processing system trace bus
DE102015121940A1 (en) * 2015-12-16 2017-06-22 Intel IP Corporation A circuit and method for attaching a timestamp to a trace message

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