經濟部中央標準局貝工消費合作社印製 A7 B7__ 五'發明説明（l) 【發明之詳细說明】 【發明所靨之技術領域】 本發明係W於單晶片時鐘同步式記憧裝置，具有邏輯分 析埔能内《之記憶钃，可正確地分析動作中之系統内的記 憧艚之動作。 【先前之技術】 在搭載著上述類型時鐘同步式記憶體之習知糸統中，當 發生不良分析時，係在記惕體之控制信號接»，位址信號 接脚及數據信虢接腳等設置探針*用Μ覼察此等各信號之 時序，並使用通輯分析器檢测認為不遽合之信號。對於該 檢査所箱之探針教目;最低宜為30至40支，但由於邏梅分析器 之機能性乃物理性的問題，造成如此多數之探針的使用通 常會有困難，所Μ僅選擇使用10多支探針設置檢査及分析。 但是，近年來之系統，特別是在PC (個人電臞）等除了使 櫬能複雜化之外》搭載於PC之記憧體也成為要使用168接 腳模组等大規横之記憶體，為了正確分析記憶體之動作， 必需設置接近160支探針，再者，將168接脚模組插入於2 Η糸統時，則需設置接近3 20接腳之探針Μ滿足對於分析 記憧體動作之要求。該要求係特別僅在使霣際之懕用軟體 動作時在分析引起不良的情形下才會確切產生。 【發明所欲解決之問囲】 如上所述，習知系統中的不良之分析係使用邏輯分析器Printed by the Central Standards Bureau of the Ministry of Economic Affairs, Shellfish Consumer Cooperative, A7 B7__ Five 'invention description (l) [Detailed description of the invention] [Technical field of the invention] The present invention is a single-chip clock synchronous recording device, which has Logical analysis of the "memory cards" in Pune, can correctly analyze the recorded actions in the system in action. [Previous technology] In the conventional system equipped with the above-mentioned type of clock synchronous memory, when a bad analysis occurs, the control signal connection of the memory body, the address signal pin and the data signal pin Set the probe * to check the timing of each of these signals with 覼, and use the general analyzer to detect the signals that do not agree. The minimum number of probes in the inspection box is 30 to 40. However, because the function of the Logistic Analyzer is a physical problem, the use of so many probes is usually difficult, so only Choose to use more than 10 probes for inspection and analysis. However, in recent years, especially in the case of PCs (personal computers), in addition to complication, the memory on PCs has also become a large-scale memory that uses 168-pin modules. To correctly analyze the movement of the memory, it is necessary to set close to 160 probes. Furthermore, when inserting a 168-pin module into the 2 system, a probe close to 3 20 pins must be set to meet the analysis memory. Action requirements. This requirement is specifically generated only when the analysis software causes a problem when the software of the world is operated. [Questions to be Solved by the Invention] As described above, the analysis of defects in the conventional system uses a logic analyzer
I 而進行，籍此能用以檢测不良•但通常之理輯分析器將如 此多数之探針設置在記憶體之接酈係有所困難，又會有產 本紙張尺度適用中國國家標準（CNS ) Α4規格（210X 297公釐） - -- 1_ - _ . ^^1 _ - - I ^^^1 in - - · f^τβ (請先閲讀背面之注意事項再填寫本頁) 4 經濟部中央橾準局貝工消費合作社印製 A7 B7 五、發明説明（2 ) 生 費用之問題。 又，近年來，對於搭載有高速化且複雑化之單晶片時鐘 同步式記憶裝置的系统，業界有愈來愈高的要求其進行更 有效且正確之不良分析°本發明係提供一種時鐘同步式記 憶装置*為了解決此等問題，使用内藏邏輯分析櫬能之記 憧體。 本發明係為解決上述問題而完成，其乃提供一種單晶片 時鐘同步式記植装置，其目的在於，藉由内酾邏輯分析櫬 能而可正碓、容易且有效地實現糸統動作之分析。 【解決問題之手段】 本發明之簞晶片時鐘同步式記憶裝置，其特微在於具備 有：記億髖，其包括通常數據記憧領域及顚序記憶領域， 而由控制信號、數據信號、位址信號所構成之邏輯顒序數 據係以顒序方式分別記憶於顒序記憶領域；數據領域控制 電路，對通常數據記憶領域用以控制數據之寫入及讀出； 及理輯順序數據記憶構件，收取邏輯顒序數據並寫入於前 述顒序記憶領域。 又，本發明之單晶片時鐘同步式記憶裝置，其中前述* 梅顒序數據記憶構件，其特激在於具備有：暫存器•·暫存 器轉送控制電路；行*列位址計數器；及比較器。 又，本發明之單晶片時鐘同步式記憧裝s，其特微在於 具備有：記憶髓•其包括通常數據記憧領域顒序記憤領域 ，而由控制信號、數據信虢、位址信諕所構成之邏輯類序 數據係Μ_序方式分別記憧於顚序記植領域；數據領域控 本紙張尺度適用中國國家標準（CNS ) Α4規格（210X297公釐） n 1 I 1_ - !1- I ;衣 n I—I ill —I- 11 (請先閱讀背面之注意事項再填寫本頁) 5 經濟部中央標準局員工消費合作社印製 A7 B7 _ 五、發明説明（3 ) 制電路，對通常數據記憶領域用Μ控制數據之寫入及謓出 :理輯順序數據記憶構件，收取理輯顒序數據並寫入於前 述顧序記憶領域，及顒序記憶領域設定構件，用以設定前 述順序記憶領域之大小。 又，本發明之單晶片時鐘同步式記憶裝置，其中前述顒 序記憶領域設定構件，其特徵在於，含有行•列位址計數 器，在模式暫存器之設定時用Μ設定前述順序記憶領域之 開始位址並加以計数者。 又，本發明之單晶片時鐘同步式記憶裝置，其中前述顯 序記憶領域設定構件，其特戡在於：使用暫存器模組時， 將設定於暫存器模組上之EEPROM的開始位址加Μ謓出並設 定於行·列位址計數器。 又，本發明之單晶片時鐘同步式記憶装置，其中前述理 輯顒序數據記憶構件，其特徴在於：將邏輯順序數據在每 時鐘信號下轉送於順序記憶領域。 【發明之實施形態】 Μ下，根據随附之圖式，將本發明之實施形態Κ圖1至 圆8作詳细說明。 霣施形態1 首先·參考園1至圖5，對於本發明之實施形態1中之 單晶Η時鐘同步式記憶装置的構成加Μ說明。 圖1係顯示本發明實拖形態1中之内藏理輯分析欐能之單 晶片時鐘同步式記憶裝置的構成之方塊圖，圖2係顧示將 圈1所示單晶片時鏟同步式記憶裝置記錄設定於理輯分析 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） m nn tm tnn mt am·— n^i ^^^^1 fm* tm HI— ^ ^ - - - , 不 i (請先閱讀背面之注意事項再填寫本頁) 6 Λ7 B7 經濟部中央標準局員工消費合作社印製I can use it to detect defects. However, it is difficult for common analyzers to set so many probes in the memory connection, and the paper size of the production paper is applicable to Chinese national standards ( CNS) Α4 specifications (210X 297 mm)--1_-_. ^^ 1 _--I ^^^ 1 in--· f ^ τβ (Please read the notes on the back before filling this page) 4 Economy Printed A7 B7 by Shellfish Consumer Cooperatives of the Ministry of Standards and Technology of the People's Republic of China 5. Description of the invention (2) The problem of cost. In addition, in recent years, for systems equipped with a high-speed and complex single-chip clock-synchronized memory device, the industry has increasingly demanded that it perform more effective and accurate failure analysis. The present invention provides a clock-synchronized type Memory device * To solve these problems, the built-in logic is used to analyze the memory of energy. The present invention is made to solve the above problems, and it is to provide a single-chip clock synchronization type recording device, and the purpose thereof is to realize the analysis of the system's movements accurately, easily and effectively by internal logic analysis function. . [Means for solving the problem] The chip-chip clock synchronous memory device of the present invention is characterized in that it includes: a memory of 100 million hips, which includes a general data recording field and a sequence memory field, and consists of control signals, data signals, and bits. The logical sequence data constituted by the address signals are stored in the sequence memory area in a sequential manner; the data area control circuit is used to control the writing and reading of data in the general data memory area; and the sequence data memory component , Receive logical sequence data and write it into the aforementioned sequence memory field. In addition, the single-chip clock synchronous memory device of the present invention, wherein the aforementioned * plum sequence data storage member is particularly equipped with: a register • a register transfer control circuit; a row * column address counter; and Comparators. In addition, the single-chip clock-synchronized recording device of the present invention is characterized by having: a memory core, which includes a general data recording field, a sequence recording field, and a control signal, a data signal, an address signal The logical sequence data constituted by 系 is recorded in the _ sequence recording field; the paper size in the data field is controlled by the Chinese National Standard (CNS) Α4 specification (210X297 mm) n 1 I 1_-! 1 -I; clothing n I—I ill —I- 11 (Please read the notes on the back before filling out this page) 5 Printed by A7 B7 of the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economy The writing and output of M control data in the general data memory field: the sequence data memory component, which collects the sequence data and writes it into the aforementioned Gu sequence memory area, and the sequence memory area setting component for setting The size of the aforementioned sequential memory field. In addition, the single-chip clock synchronous memory device of the present invention, wherein the aforementioned sequential memory field setting means includes a row / column address counter, and when the mode register is set, M is used to set the sequential memory field. Start address and count. In addition, the single-chip clock synchronous memory device of the present invention, in which the aforementioned explicit sequence memory field setting means, is characterized in that when using a register module, the start address of the EEPROM set on the register module is set. Add M and set it to the row and column address counter. In addition, the single-chip clock synchronous memory device of the present invention, wherein the above-mentioned serial data storage means is characterized in that the logical sequence data is transferred to the sequential memory field under each clock signal. [Embodiment of the invention] In the following, according to the accompanying drawings, the embodiment K of the present invention will be described in detail in FIGS. 1 to 8. Implementation Mode 1 First, with reference to FIGS. 1 to 5, the structure of a single crystal clock synchronization type memory device according to Embodiment 1 of the present invention will be described. FIG. 1 is a block diagram showing the structure of a single-chip clock-synchronized memory device capable of built-in logic analysis in the first embodiment of the present invention, and FIG. 2 is a diagram showing the single-chip time-shovel synchronous memory shown in circle 1. The device records are set in the logical analysis. The paper size applies the Chinese National Standard (CNS) A4 specification (210X 297 mm) m nn tm tnn mt am · — n ^ i ^^^^ 1 fm * tm HI— ^--- -, Not i (Please read the notes on the back before filling this page) 6 Λ7 B7 Printed by the Staff Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs
五、發明説明 ( 4 ) I 1 模 式 之 流 程 Η $ 圈3係顯示做為圖1所示記憶艚將内藏埋輯 1 1 I 分 析 櫬 能 之 同 步 DRAM(SDRAM)的動作例之示意圓，圓4係顯 1 1 1 示 對 圈 1所示單晶片時鐘同步式記憶装置以指令發動觸發 請 先 Bfl 1 1- 器 記 錄 記 憶 邏 輯 顒序數據之動 作（第3寫入方法）的流程圆 阅 背 I 1 $ 圖 5係顬示對Hi所示單晶片 時鐘同步式記憶裝置Μ指令 面 之 注 1 發 動 觸 發 器 9 記 錄記憶觸發器 之前及後的邏輯顚序數據之 意 事 項 1 動 作 (第4寫 入 方 法）的流程圈 > 再 填 ί 1 ΒΒ 寫 本 本 1係顯不本發明之實施形態1中內藏具有具備邏輯順序 頁 1 Ι 數 據 之 記 憧 體 的 邏輯分析機能 之單晶片時鐘同步式記憶装 1 1 罝 的 構 成 之 方 塊 画。圖1中，1係暫存器，分別將控制信號 1 1 Λ 位 址 信 號 及 數 據信號等之埋 輯顯序數據（將邏輯數據以 1 訂 顚 序 方 式 表 示 )暫時加以記憶 > 2係記憶體内之通常數據記 1 I 憶 領 域 3係數據領域控制電路，用Μ控制数據記憶領域2 1 1 I 之 寫 入 / 讀 出 4係記憶體内之理輯順序記憧機能’為了 1 1 用 以 記 憶 控 制 信 號、位址信號 及數據信號等之邏輯顒序數 1 據 (使控制信號 ‘位址信虢、數據信號等Μ顚序方式輪入 i 並 在 保 持 此 等 順 序之狀態下被 記憶），與數據記憶領域2匾 1 I 別 而 另 設 置 之 順 序記憶領域， 5係暫存器轉送控制®路， 1 1 I 將 暫 存 器 1之内容轉送到顒序記憶領域4並進行控制。 1 1 又 6係行 列位址計數器 為顯示顚序記植領域4之何 1 1 行 及 何 列 應 寫 入 邏輯順序數據 ，7係比較器，應發動觸發 1 1 器 (後面加以陳述）用Μ記憶邏 輯顚序數據並在暫存器1與 1 I 依 顒 序 被 _ 入 之 敝據加以比較 而在二者一致時用Μ控制發 1 1 ι 動 觸 發 器 9 8係η 支之記憶控剌 信猇綸入接腳8，M RASA 1 I 本紙浪尺度適用中國國家標隼（CNS ) A4規格（210X297公釐） -7 - 經濟部中央標準局貝工消费合作社印裝 A7 B7__ 五、發明説明（5 ) CAS等所代表由記憶驩構件外部所供給，9係支之位址信 號（AO、A1)输入接鼷9，由記憶體構件外部所供給· 10係 數據信號（DQ〇、DQ1)接脚，對記憧體樽件進行數據信號之 _出入，11係時鐘（CLK)输入接脚11，使成為記憧髓構件 之基本的時雄信號由記憧B構件之外部所供給，12係平行 匯流排，具有連结暫存器1及顒序記憶領域4(η + · + Ρ)之寬 幅。遢有，藉由比較器7及記憶艚之顧序記憶領域4用Μ溝 成理輯顒序數據記憶構件，並在單晶片時鐘同步式記憶装 置内用Κ構成理輯分析機能。 其次*請同時參考圖1及圖2，以說明本發明之實施形態 1中將内藏理輯分析機能之單晶片時鐘同步式記憧装置的 動作。Η2係顯示對本實《δ形態中之簞晶片時鐘同步式記 憶装置為了用Μ設定遍輯分析模式之流程_。_2之步驟 101中*未設定埋辑分析模式時係進入到步驟106並進行通 常記憧動作，有設定邏輯分析模式時係進入到步驟102並 在模式暫存器（在記憶髖之外，於此未圖示）用Κ設定邇輯 分析棋式。在步《103中完成運輯分析模式之設定，在通 常數據記憧領域2記憧输入數據（步驟104)，在顚序記憶領 域4用以記憶邏輯顚序數據（步驟105)。當僅使用做為通常 之記憶體時，則使用不設定理輯分析模式。 謦如，對於同步DRAM(SDRAM)，在動作開始時進行棋式 暫存器之設定*所以此時在棋式暫存器設定«輯分析横式 。遢有，對埋輯分析横式之設定及後述之記憶體的顒序記 憶領域4之邏輯順序敝據之寫入係藉由CPU (未圖示）所進行 本紙張尺度適用中國國家標準（CNS ) A4規格（210 X 297公釐） 1 -» I - - _^^1 I n HI ] I In II n - ^^1 , (請先閲讀背面之注意事項再填寫本頁) 8 經濟部中央標準局貝工消费合作社印製 A7 B7 五、發明説明（6 ) 。本實施形態中，程序記植領域4之大小係被固定’所W 不必設定記憧體之數據記憶領域2之大小及順序記憶領域4 之大小。設定順序記植領域4之大小的例子係在實施形態2 中加Μ說明。Μ下為說明設定理輯分析横式後之動作。 β 3係顯示做為記憶體並内藏理輯分析櫬能之同步 DRAM(SDIiAM)的動作例之示意_。同步DRAM(SDRAM)中’設 定著通輯分析我式，則使寫入於順序記憶領域4並用K控 制缠輯顒序數據之暫存器1，暫存器轉送控制霣路5’行· 列位址計数器6及比較器7成為可動作狀態*由記惕控制信 號输入接腳8，位址信號（AO、A1)輸入箝岬9及數據信號（DQO 、DQ1)接B10等輸入之控制信號、位址信號及數據信號， 係在時鐘CL1(信號之立起界限中收取於暫存器1，做為此時 之通輯顚序數據係Μ各1時鐘信號依順序記憶於記憶體之 嘁序記憶領域4。 圈3之動作例更具通而言，則在時點π)中，各控制信號 及數據信號（RAS，CAS，WE，CS，DQM)之理輯係成為（〇、1 、1、1、0)。同樣的，其後的各時點（2)· (3)，（4)，（5) ’ （6)中，分別成為（〇、1、1、〇、〇)，（〇、1、1、ι、〇) ,(1、0、0、〇、〇), (1、〇、〇、1、”，（1、0、0、〇、 1)°此等之埋輯順序數據係寫入於設定在記憶艚之順序記 憧領域4°如此·藉由寫入邏輯順序數據而且縝出時，利 用此等败據即可分析記憶體動作。因此，對記憧髓之所有 接腰I不必如習知技g般設置探針，便可正確容易且有效進 行記憶盟動作之分析。 本紙張尺度適用中國國家標準（c叫八4規格（2ωχ 297公趁） -J—-----^- - J--衣-.11 ----訂 Vi ... (請先閲讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作社印策 Α7 Β7 五、發明説明（7 ) 以下為說明記惕《之顚序記憶領域4的邏輯顒序數據之 寫人方法。 做為第1之寫入方法，傜如上述之SDRAH例’在每時鐘信 號用Μ記憧遍輯顚序數據之方法。換言之，由外部之控制 信號、位址信號及數據信號等係進入到通常數據領域控制 霄路3及同時收容於暫存器1。收容於暫存器1之邏輯順序 數據，係蘋由暫存器轉送控制電路5之控制而連结暫存器1 及顧序記憶領域4，通通平行匯流排12轉送到顚序記憧領 域4而被記憶。 當理輯順序數據每次被記憶時，行*列位址計数器6則f增 如此![確取徒在順序記憶領域4之哪行及列是否被記憶。«輯 順序數據之寫入到達記憶體之最终位址结束時*由開始位 址再度進行邏輯顒序敏據之寫入。在顚序記憶領域4寫入 理輯順序數據時 ，也對通常記憶91領域2進行記憶動作。 其次，參考H3說明第2寫入方法。 第2寫入方法係僅對有效指令之邏輯顚序數據之取入方 法。以圖3之例而言，則CS(晶片選擇）成為低霣平之各時 點（2)，（4)，（6)中僅使（〇、1、1、〇、0)，（1、0、〇、〇 、0>，（1、0、0、0、1)之邏輯_序數據為有效，所K僅 將該邇輯顚序數據轉送到顚序記憶領域4。 其次，參考_4說明第3寫入方法。 做為第3寫入方法，係輅由CPU(未圖示）K某指令對寫入 發動觸發器*僅將經發動觸發器後之理輯順序數據取入於 Μ曼序記憧領域4之方法。圖4傜以指令對寫入能用以記憧發 本紙張尺度適用中國國家標準（CNS ) Α4規格（210X 297公梦_ ) ~" ' -10 - (請先閲讀背面之注意事項再填寫本頁) 、1Τ 經濟部中央標準局貝工消費合作社印製 Α7 Β7 五、發明説明（8 ) 動觸發器後之理緝順序數據的第3寫入方法之流程圔。Μ 下，對於寫入之觸發器的掛法加以說明。 首先，步》107中，將欲取之理輯順序數據設定於比較 器7。進入到步骤1〇8，將比較器7之内容與記憶於暫存器1 之邏輯顚序數據加以比較。二者不一致時係w下次之數據 再度進行比較，二者一致時係進入到步嫌109 ’將暫存器1 之内容的通輯顚序數據記憶到顚序記憶領域4並開始動作 ，藉由行.列位址計數器6之計算來進行記憶直到順序記 憶領域4之最後行為止，於此终止邏輯順序數據之取入（步 驟 110) 0 接著，參考圈5說明 第4寫入方法。 第4寫入方法愫藉由CPU(未圈示）K某指令對寫入 由發動觸發器之前將输入之理輯顚序數據記憶於作序記憶 領域4，以某時點藉由CPU發動觴發器，進而將發動觸發器 之後的理輯順序數據記憶於顚序記憶領域4之方法。圔5係 對用Μ記憶在指令發動觴發器之前及之後的理輯顚序数據 之第4寫入方法的流程圔。 首先*在步驟111中，將檢測之理輯_序數據設定於比 較器7，用Μ開始邏輯顚序數據之寫入。進入到步驟112· 檢査行洌位址計敝器6是否已進展到顒序記憶領域4之一半， 當行.吵纽計數器6進雇到顒序記憧領域4之一半時，即進入到步 驟113，將比較器7及暫存器1之内容加以比較，若二者一 致*則Μ寫入到最後行為止並终止理輯顒序數據之取入（ 步嫌114)。 本紙張尺度適用中國國家標準（CNS ) Α4規格（210X 297公釐） 1^---„--：---：-I 衣------，1Τ (請先閲讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消费合作社印製 A7 B7 五、發明説明（9 ) 上述之步驟113中，當比較器7及暫存器1之内容非一致 時*則進入到步驟115，使理輯顒序數據之寫入到達最後 行為止，並由開始位址再度繼鳙埋輯順序數據之寫入，並 取出觸發器Μ上述同樣方式動作。 堪有，由順序記憶領域4講出邏輯顒序數據之方法5嚓 將理輯分析模式解除，並如同通常数據信號經由數據痒跗 (DQ)謓出。 簧施形態2 以下，參考圓6至園8，對於本發明之實施形態2中內藏 埋輯分析檄能之單晶片時鐘同步式記憶裝置的構成加以詳 细說明。圖6係顯示本發明之實施形態2中内藏理輯分析機 能之單晶片時鐘同步式記憶裝置的構成園，圈7係顯示_6 所示單晶片時鐘同步式記憶装置中記錄順序記憶領域之設 定方法的流程圈，圖8係顯示將圖6所示單晶片時鐘同步式 記憶装置搭載於記憶體模組時記錄顒序記憶領域之設定方 法的流程圈。 在圔6中與圖1所示符號為相同符號之構成要素係具有與 圖1者同樣之機能，所以於此省略其說明。可是，2a係通 常數據記憶領域，4a係設於通常數據記憶領域23内大小可 變更之顒序記憶領域。遢有，藉由暫存器轉送控制電路5 、行♦列位址計數器6、比較器7及記憶體之顒序記憶領域 4a而構成理輯順序數據記憶構件，並在單晶片時鐘同步式 記憶裝置内用Μ構成理輯分析機能。又*本寊施形態中， 行·列位址計數器6係用以設定記憶體之順序記憶領域4a 本紙張尺度適用中國國家標準（CNS ) Α4規格（210X 297公釐） 1,. J . ~ 訂 .ξ -(請先閲讀背面之注意事項再填寫本頁) 經濟部中央標準局貝工消費合作社印裝 A7 __. _B7__ 五、發明説明（ίο) 之两始位址並構成顚序記憶領域設定構件，藉由變更其設 定内容而變更顚序記憶領域4a之大小。 其次*參考圓7*對於顒序記憧領域4a之設定方法加以 說明。圆7所示順序記憧領域4a之設定方法，係藉由CPU( 未圔示）之控制用以設定横式暫存器（未圈示）時，與缠輯 分析横式之設定一起，Μ決定顒序記憶領域4a之大小而將 開始行·列位址_入並加Μ設定。K下對於其設定方法加 Μ說明。 在圖7之步驟116中，判定是苔箱設定邏輯分析棋式*未 設定時係進到步驟122進行通常之記憶動作，有設定時則 係進到步驟117，在設定模式暫存器時將纒輯分析模式加 Κ設定並進到步驟118，將順序記憶領域4a之開始位址設 定於行•列位址計數器6。在步驟119中，當完成«輯分析 横式之設定及開始位址之設定時*則在通常數據記憶領域 4a記憶输入數據（步驟120)*在順序記憶領域4a用K記憶 遜輯顚序數據（步骤121)。 接著，參考圃8，對於顒序記憶領域4a之其他設定方法 加以說明。圈8所示顚序記憶領域4a之設定方法的情形， 係將本發明中之單晶片時鐘同步式記憧装置搭載於記惕體 横組時決定順序記憶領域4a之容量及開始位址的方法。當 係SDRAM搭載模狙時，其搭載著用以記憶模姐之羼性數據 等之EEPR0M，所W在該EEPR0M預先寫人順序記憧領域4a之 容量及開始位址•在進入到邇輯分析模式時讀出該數據並 設定於行·列位址計数器6。讀出設定於該EEPR0M之開始 本紙張尺度適用中國國家標準（CNS ) Ad規格（210X 297公釐） n - I —II —^1·'-1 pig I I tn —I— m SI t^n (請先閲讀背面之注意事項再填寫本頁) 13 A7 B7 經濟部中央標準局員工消費合作社印製 五、發明説明（ 地址並設定於行·列位址計數器6之構件係藉由CPU之控制 加K動作，Μ砍體或硬體皆可實現。堪有，上述以外之動 作係與圈2所示理輯分析模式之設定為相同者。 在圖8之步驟123中，若未設定理輯分析模式，則進到步 驟130並進行通常記憶動作，但若有設定邏輯分析模式， 則進到步驟124，判定EEP ROM是否有順序記憶領域4a之容 量及開始位址之設定數據，若未設定数據，則進到步驟130 並進行通常記憶動作，但若有設定數據，則 進到步驟 125。在步驟125中，在設定模組暫存器時將邏輯分析模式 加以設定並進入步驟126，將顒序記憶領域4a之開始位址 設定到行·列位址計數器6。在步驟127中，當完成理輯分 析模式之設定時，在通常數據記憶領域2a記憶輪入數據（ 步驟128)，並在顒序記憶領域4a記憶邇輯顆序數據（步驟 129) ° 【發明之效果】 本發明*係如上述之構成，特別是，藉由内藏邏輯分析 機能，除了可正確、容易且有效實現系統動作之分析，並可 藉由改煸程式而變更將記憶體之通常 數據記憶領域及顒 序記憶領域之大小，如此可容易且有效進行動作中之系統 的不良分析。 【圔式之簡單說明】 圖1係顯示本發明之簧施形態1中内藏邏輯分析櫬能之單 晶片時鐘同步式記憶裝置的構成之方塊圈。 圈2係顧示將圖1所示之單晶片時》同步式記憶裝置設定 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -- II - - 111 1 - - ! n I I - 1 - ---* . < - . · 牙 、vd (請先閲讀背面之注意事項再填寫本頁) 14 經濟部中央標準局員工消費合作社印策 A7 B7 五、發明説明（12 ) 於埋輯分析模式並記錄動作之流程圖。 圖3係顬示做為圓1所示内藏理輯分析機能之同步 DRAK(SDRAM)的動作例之示意圔。 圖4係顧示對圖1所示單晶片時鐘同步式記憶裝置K指令 發動觸發器用Μ記憶邏輯顒序數據並記錄動作（第3寫入方 法）之流程圓。 圈5係顯示對圈1所示單晶片時鐘同步式記憶装置以指令 發動觸發器，用Κ記憶觴發器之前及之後的邏輯順序數據 並記錄動作（第4寫入方法）之流程圈夂 圈6係顥示本發明之實施形態2中内藏邏輯分析機能之單 晶片時鐘同步式記憶裝置的構成之方塊围。 圖7係顯示圈6所示之單晶片時鐘同步式記憶裝置中記錄 順序記憶領域之設定方法的流程園。 圖8係顯示將圃6所示單晶片時鐘同步式記憶裝置搭載於 記憶體模组時記錄顧序記憶領域之設定方法的流程圈。 【元件編號之說明】 1…暫存器，2…通常數據記憶領域，2a…通常数據記 憶領域2，3…數據領域控制霄路，4…顧序記憶領域，4a …順序記憶領域，5…暫存器轉送控制電路，6行·列位 址計數器， 7…比較器，8…記憶控制信號輪入接腳，9 …位址信號榆入接腳， 10…數據信號输出入接腳，11…時 鐘信號輪入接腳，12…平行匯流排。 本紙張尺度適用中國國家標準（CNS ) A4規格（210 X 297公釐） -—I nn m^— n^i . ^ n n ^^^1 - J. • . · « 、-口 (請先閲讀背面之注意事項再填寫本頁) 15V. Description of the invention (4) The flow of the I 1 mode. The circle 3 is shown as the memory shown in Figure 1. The embedded circle is a schematic circle of an example of the operation of a synchronous DRAM (SDRAM). The circle 4 system display 1 1 1 shows the single-chip clock synchronous memory device shown in circle 1 as a command to trigger. Please Bfl 1 1- device record the sequence of memory logic sequence data (the third writing method). Fig. 5 shows the note 1 on the M instruction side of the single-chip clock synchronous memory device shown in Hi. 1 Start the trigger. 9 Record the logical sequence data before and after the memory trigger. 1 Action (No. 4 Writing method) Flow circle> Refill ί 1 ΒΒ Script 1 shows the single chip clock synchronization in the first embodiment of the present invention, which has a logic analysis function with a logic sequence page 1 Ι data memory A block picture of the composition of 1 1 罝 style memory. In Figure 1, the 1-series register temporarily stores the embedded display sequence data of the control signal 1 1 Λ address signal and data signal (representing the logical data in a 1-order sequence mode) for temporary storage> 2 series memory Normal data record in the body 1 I Memory field 3 series data field control circuit, use M to control the data memory field 2 1 1 I write / read 4 series memory body sequence order recording function 'for 1 1 It is used to memorize the logical sequence numbers of control signals, address signals, and data signals, etc. (make control signals such as address signals, data signals, and other sequential sequences into i and be memorized while maintaining these sequences ), The sequence memory field which is set up separately from the data memory field 2 plaque 1 I, 5 series of register transfer control ® road, 1 1 I transfers the contents of register 1 to sequence memory field 4 and controls. 1 1 and 6 series of row and column address counters are used to display the sequence and record of the field 4 of the 1 1 row and column. Logical sequence data should be written. The 7 series of comparators should trigger the 1 1 device (described later). The logic sequence data is memorized and compared in the registers 1 and 1 according to the sequence of _ data. When the two are consistent, the M control is used to send a 1 1 ι trigger 9 9 series memory control. Letter 猇 猇 8, M RASA 1 I The standard of this paper is applicable to China National Standard (CNS) A4 (210X297 mm) -7-Printed by the Shelling Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs A7 B7__ 5. Description of the invention (5) Representatives such as CAS are supplied from the outside of the memory component, and the address signals (AO, A1) of the 9 series branch are connected to 9 and are supplied from the outside of the memory component. · 10 series data signals (DQ0, DQ1) Pins for inputting and outputting data signals to and from the body parts. The 11-series clock (CLK) input pin 11 enables the basic clock signal that becomes the core component to be supplied from the outside of the component B. The 12 series are parallel. Bus with link register 1 and sequence memory 4 (η + · + P). In other words, the comparator 7 and the memory area 4 of the memory are used to form a logical sequence data storage component by using the M groove, and a single chip clock synchronous memory device is used to form a logical analysis function. Secondly, please refer to FIG. 1 and FIG. 2 at the same time to explain the operation of the single-chip clock synchronization type recording device with a built-in logic analysis function in Embodiment 1 of the present invention. Η2 shows the flow of the 箪 chip clock synchronous memory device in the δ mode in order to set the traversal analysis mode by using _. In step 101 of _2 *, if the embedded analysis mode is not set, it goes to step 106 and performs the normal recording action. When there is a logic analysis mode, it goes to step 102 and the mode register (outside of the memory hip, in (This is not shown) Use KK to set the series to analyze chess moves. In step 103, the operation analysis mode is set. Input data is recorded in the normal data recording area 2 (step 104), and logical sequence data is stored in the sequence memory area 4 (step 105). When only the normal memory is used, the non-setup analysis mode is used. For example, for synchronous DRAM (SDRAM), the chess register is set at the beginning of the operation * so at this time, the chess register is set to «Edit Analysis Horizontal Mode". Yes, the setting of the embedded analysis horizontal mode and the logical sequence of memory area 4 described later are written by the CPU (not shown). This paper size applies the Chinese National Standard (CNS) ) A4 size (210 X 297 mm) 1-»I--_ ^^ 1 I n HI] I In II n-^^ 1, (Please read the precautions on the back before filling this page) 8 Central Ministry of Economy A7 B7 printed by Shelley Consumer Cooperatives of the Standards Bureau 5. Description of Invention (6). In this embodiment, the size of the program memory area 4 is fixed, so it is not necessary to set the size of the data memory area 2 and the sequence memory area 4 of the memory. An example of setting the size of the sequence recording field 4 is described in Embodiment 2. The next step is to explain the actions after setting the analysis mode. The β 3 series shows an example of the operation of a synchronous DRAM (SDIiAM) that is a memory and has built-in logic analysis capabilities. In the synchronous DRAM (SDRAM), the general analysis mode is set, and the register 1 written in the sequential memory field 4 is used to control the sequence data, and the register is transferred to the control path 5 'rows and columns. The address counter 6 and the comparator 7 become operational. * Control signals are input to pin 8. Address signals (AO, A1) are input to clamp 9 and data signals (DQO, DQ1) are connected to control signals such as B10. The address signal and the data signal are collected in the register 1 in the clock CL1 (the rising limit of the signal) as the general sequence data at this time. Each 1 clock signal is sequentially stored in the memory. Sequence memory area 4. The operation example of circle 3 is more general. In the time point π), the logical system of each control signal and data signal (RAS, CAS, WE, CS, DQM) becomes (0, 1,, 1, 1, 0). Similarly, in the following time points (2), (3), (4), (5) '(6), they become (0, 1, 1, 0, 0), (0, 1, 1, respectively). ι, 〇), (1, 0, 0, 〇, 〇), (1, 〇, 〇, 1, ", (1, 0, 0, 〇, 1) ° These embedded sequential data are written This is set to 4 ° in the order of the memory area. By writing logical sequence data and extracting it, you can use these failures to analyze the memory movement. Therefore, it is not necessary to have all the waistlines of the memory. Setting the probe like the conventional technique g can accurately, easily and effectively analyze the action of the memory union. This paper size is applicable to the Chinese national standard (c is called 8-4 specification (2ωχ 297)) -J —----- ^--J-- 衣 -.11 ---- Order Vi ... (Please read the notes on the back before filling out this page) Imprint of Employees' Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs Α7 Β7 V. Description of Invention (7 ) The following is a description of the writing method of the logical sequence data in the "Sequence Memory Field 4". As the first writing method, as in the above-mentioned SDRAH example, "M is recorded every clock signal." Sequential data method In other words, external control signals, address signals, and data signals enter the normal data field to control Xiaolu 3 and are simultaneously stored in the temporary register 1. The logical sequence data stored in the temporary register 1 is temporarily stored by Ping. The register transfer control circuit 5 is connected to the register 1 and the sequential memory area 4, and is transferred to the sequence memory area 4 through the parallel bus 12 to be stored. When the sequence data is memorized each time, * The column address counter 6 is incremented by f! [Determine which row and column in the sequence memory area 4 are memorized. «When the sequence data is written to the end of the memory's final address * from the start bit The address is again written in the logical sequence. When the sequence data is written in the sequence memory area 4, the normal memory 91 area 2 is also memorized. Next, the second writing method will be described with reference to H3. The writing method is a method of taking only the logical sequence data of valid instructions. Taking the example in Fig. 3, CS (chip selection) becomes each time point of low level (2), (4), (6) Only make (〇, 1, 1, 〇, 0), (1, 0, 〇, 〇, 0 > The logical sequence data of (1, 0, 0, 0, 1) is valid, so K only transfers this sequence data to sequence memory field 4. Next, the third writing method will be described with reference to _4. As the third writing method, the CPU (not shown) K triggers a write to a write instruction. * Only the sequence data of the sequence after the trigger is triggered is entered into the M-man sequence record area 4 Method. Figure 4: Writing with instructions can be used to record the paper size. The paper size applies the Chinese National Standard (CNS) Α4 specification (210X 297 public dream_) ~ " '-10-(Please read the notes on the back first (Fill in this page again), 1T Printed by the Central Standards Bureau of the Ministry of Economic Affairs, Shellfish Consumer Cooperative, A7, B7 5. Description of the invention (8) The third method of writing the wanted sequence data after the trigger is activated. The following describes how to write the triggers. First, in step "107, the desired sequence data is set in the comparator 7. Go to step 108, and compare the content of the comparator 7 with the logic sequence data stored in the register 1. When the two do not match, the next time the data is compared again. When the two do not match, it enters step 109. 'Save the general sequence data of the contents of the register 1 to the sequence memory field 4 and start the action. The calculation is performed by the row and column address counter 6 until the last action in the sequential memory area 4 is ended, and the logical sequence data fetching is terminated (step 110). Next, the fourth writing method will be described with reference to circle 5. The fourth writing method: by the CPU (not shown) K, a certain instruction pair is written before the trigger is started. The input sequence data is stored in the sequence memory field 4 and is issued by the CPU at a certain point in time. Controller, and then the sequence data of the sequence after the trigger is stored in the sequence memory field 4 method. (Fifth series) The flow of the fourth writing method of the sequence data before and after the commander is started by using the M memory. First * In step 111, the detected logic_sequence data is set to the comparator 7, and the writing of the logic sequence data is started with M. Proceed to step 112. Check whether the line address calculator 6 has progressed to one-half of the sequence memory area 4. When the line-up counter 6 is hired to one-half of the sequence memory area 4, enter the step. 113. Compare the contents of the comparator 7 and the register 1. If they are the same *, M is written to the last line and the access of the sequence data is stopped (step 114). This paper size applies to Chinese National Standard (CNS) Α4 specification (210X 297 mm) 1 ^ --- „-: ---: -I clothing ------, 1T (Please read the precautions on the back first (Fill in this page again.) Printed by the Consumer Standards Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs. A7 B7. 5. Description of the invention (9) In the above step 113, when the contents of the comparator 7 and the register 1 are not consistent, go to step 115. , So that the writing of the sequence data reaches the end, and the writing of the sequence data is resumed from the start address, and the trigger M is operated in the same manner as described above. It is worth mentioning in the field of sequence memory 4 Method 5 for generating logical sequence data: The logic analysis mode is released, and the data signal is output through the data tick (DQ) as usual. Spring application mode 2 hereinafter, referring to circles 6 to 8 for the implementation of the present invention The structure of a single-chip clock synchronous memory device with built-in analysis capability in mode 2 will be described in detail. FIG. 6 shows a single-chip clock synchronous memory device with built-in analysis function in embodiment 2 of the present invention. Composition circle, circle 7 series display single chip clock shown in _6 FIG. 8 is a flowchart showing a method for setting a sequential memory field in a step memory device. FIG. 8 is a flowchart showing a method for setting a sequential memory field when the single-chip clock synchronous memory device shown in FIG. 6 is mounted on a memory module. In 圔 6, the constituent elements having the same symbols as those shown in FIG. 1 have the same functions as those in FIG. 1, so descriptions are omitted here. However, 2a is a general data memory field, and 4a is a general data memory field. The sequence memory area whose size can be changed in the area 23. There is a logic sequence composed of a register transfer control circuit 5, a row and column address counter 6, a comparator 7, and a memory sequence memory area 4a. The data memory component, and the logic analysis function is formed by M in the single-chip clock synchronous memory device. In the present embodiment, the row / column address counter 6 is used to set the sequence memory area of the memory 4a paper Standards are applicable to China National Standard (CNS) Α4 specifications (210X 297 mm) 1, J. ~ Order .ξ-(Please read the notes on the back before filling this page) Company printing A7 __. _B7__ V. The two start addresses of the invention description (ίο) constitute the sequence memory field setting component, and the size of the sequence memory field 4a can be changed by changing its setting content. Secondly, * Reference circle 7 * The setting method of the sequence recording field 4a will be described. The setting method of the sequence recording field 4a shown in circle 7 is to set the horizontal register (not shown) by the control of the CPU (not shown). At the same time, along with the horizontal analysis setting, M determines the size of the sequence memory area 4a and sets the starting row and column address_in and adds M. Add K to the setting method under K. In Figure 7 In step 116, it is determined that the moss box is set for logic analysis. * If not set, go to step 122 to perform the normal memory action. If there is a setting, go to step 117. When the mode register is set, edit the analysis mode. Add K to set and proceed to step 118, and set the start address of the sequence memory area 4a to the row / column address counter 6. In step 119, when the «set analysis horizontal mode setting and start address setting are completed *, input data is stored in the normal data storage area 4a (step 120) * K sequence data is stored in the sequential storage area 4a. (Step 121). Next, referring to the garden 8, other setting methods of the sequence memory area 4a will be described. The setting method of the sequence memory area 4a shown in circle 8 is a method for determining the capacity and starting address of the sequence memory area 4a when the single-chip clock synchronous recording device of the present invention is mounted on a mindset horizontal group. . When the SDRAM is equipped with a mold, it is equipped with EEPR0M, which is used to memorize the sexual data of the model sister. Therefore, the EEPR0M is written in advance in order to record the capacity and starting address of field 4a. This data is read in the mode and set to the row / column address counter 6. Read out at the beginning of the EEPR0M. The paper size applies the Chinese National Standard (CNS) Ad specifications (210X 297 mm) n-I —II — ^ 1 · '-1 pig II tn —I— m SI t ^ n ( Please read the precautions on the back before filling this page) 13 A7 B7 Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the invention (Address and set the row and column address counter 6 The components are controlled by the CPU and added K action, M cut body or hardware can be realized. It is possible that actions other than the above are the same as the setting of the logic analysis mode shown in circle 2. In step 123 of FIG. 8, if no logic analysis is set Mode, proceed to step 130 and perform the normal memory operation, but if there is a set logic analysis mode, proceed to step 124 to determine whether the EEP ROM has the setting data of the sequence memory area 4a and the start address. If the number is not set, Data, then proceed to step 130 and perform the normal memory operation, but if there is setting data, proceed to step 125. In step 125, when setting the module register, set the logic analysis mode and enter step 126, Sequence Memory Field 4a The start address is set to the row / column address counter 6. In step 127, when the setting of the logic analysis mode is completed, the data is rotated in the normal data memory area 2a (step 128), and in the sequence memory area 4a Memory sequence data (step 129) ° [Effects of the invention] The present invention * is structured as described above. In particular, the built-in logic analysis function, in addition to the analysis of system actions, can be performed correctly, easily, and effectively, and The size of the normal data memory area and sequence memory area of the memory can be changed by changing the program, so that the bad analysis of the system in operation can be easily and effectively performed. [Simple description of the formula] Figure 1 shows this The circle of the structure of the single-chip clock synchronous memory device with built-in logic analysis function in the first embodiment of the invention of the invention. The circle 2 is when the single-chip device shown in FIG. Applicable to China National Standard (CNS) A4 specification (210X297 mm)-II--111 1--! N II-1---- *. ≪-. · Please read the precautions on the back first Fill out this again ) 14 Instruction A7 B7, Consumer Cooperative of the Central Standards Bureau, Ministry of Economic Affairs 5. Description of the Invention (12) Flowchart of recording analysis mode and recording actions. Figure 3 shows the built-in logic analysis function shown in circle 1. Figure 4 shows an example of the operation of a synchronous DRAK (SDRAM). Fig. 4 shows the sequence of data using the M memory logic to trigger the K instruction on the single-chip clock synchronous memory device shown in Fig. 1 and record the operation (the third writing method). ). Circle 5 shows the single-chip clock-synchronized memory device shown in circle 1 to start a trigger with instructions, and to record the logical sequence data before and after the transmitter with Κ and record the action (the fourth writing method) The flow circle 6 is a block circle showing the structure of a single-chip clock synchronous memory device with a built-in logic analysis function in Embodiment 2 of the present invention. Fig. 7 is a flow chart showing a method for setting a recording sequence memory field in the single-chip clock synchronous memory device shown in circle 6. FIG. 8 is a flow chart showing a method for recording a sequential memory field setting when the single-chip clock synchronous memory device shown in the garden 6 is mounted on a memory module. [Explanation of component numbers] 1 ... register, 2 ... usual data memory field, 2a ... usual data memory field 2, 3 ... data field control channel, 4 ... gu sequence memory field, 4a ... sequence memory field, 5 … Register transfer control circuit, 6 row · column address counter, 7… comparator, 8… memory control signal round-in pin, 9… address signal elm pin, 10… data signal output pin, 11 ... clock signal turns into the pin, 12 ... parallel bus. This paper size applies to China National Standard (CNS) A4 (210 X 297 mm)--I nn m ^-n ^ i. ^ Nn ^^^ 1-J. •. · «, -Mouth (please read first (Notes on the back, please fill out this page) 15