WO2000063777A1

WO2000063777A1 - Method for tracing in system-on-chip architectures

Info

Publication number: WO2000063777A1
Application number: PCT/DE2000/001165
Authority: WO
Inventors: Dirk Amandi; Winfried Gläser; Alexander Mircescu; Robert Winter
Original assignee: Siemens Aktiengesellschaft
Priority date: 1999-04-20
Filing date: 2000-04-13
Publication date: 2000-10-26
Also published as: DE10081032D2; TW527536B

Abstract

The invention relates to a system-on-chip arrangement, wherein the data states of a plurality of components are detected, selected, provided with a source identifier and a time stamp, brought together according to the priority thereof and outputted at an interface in order to be evaluated. The width of the trace interface (number of the pins on the chip) and the complexity of the tracer are minimised.

Description

description

Procedure for tracing in system on chip architectures

The subject matter of the application relates to a method for tracking data and their states in an arrangement in which a semiconductor chip (SoC) has a plurality of components.

With System on Chip (SoC) architectures, various components, e.g. Microprocessors, RAMs and complex hardware control logic housed on one chip. In order to test a SoC design, it is essential to be able to "look" into the chip, i.e. record internal data streams. In order to meet the test requirements, it must generally be possible to trace the data streams of the individual components in parallel (i.e. with the exact temporal relationship to one another).

Up until now, parallel wiring of a few data streams, e.g. only one memory interface on the trace bus, was sufficient and the complexity was possible. The increasing complexity of SoC architectures makes tracing a large number of components desirable. Parallel wiring of the individual component interfaces to the trace bus initially appears to be practically impossible.

The object of the application is based on the problem of specifying a method for tracing a large number of SoC components on a trace bus while minimizing the tracer complexity.

The problem is solved by the features of claim 1.

The subject of the application makes use of the knowledge that, for example, a RAM interface latency with a read command caused by the RAM latency that none contain interesting / necessary trace information, and trace information from other query points can be forwarded in these waiting cycles.

It is an advantage of the subject of the application to be able to transfer the data of as many SoC components as possible to a trace interface and at the same time to minimize the width of the trace interface (number of pins on the chip) and basically the complexity of the tracer. Furthermore, due to the limited recording depth of the external media (hardware tracer HWT), data reduction is advantageous.

Advantageous further developments of the subject of the application are specified in the subclaims.

The subject of the application is explained in more detail below as an exemplary embodiment to the extent necessary for understanding with reference to figures. 1 shows a representation of the trace system according to the application. FIG. 2 shows a flow diagram in the trace system and

3 shows a further flow chart in the trace system according to the invention.

In the figures, the same designations denote the same elements.

Tracing is understood to mean the query of the data status at a specific TAP query point (for: trace access point) for evaluating the data status.

1 shows a system on chip arrangement SoC in which the subject of the application is realized. With system on chip architectures, various components, such as microprocessors, RAMs and complex HW (hardware) control logic, are arranged on one chip. The arrangement in FIG. 1 represents a large number of components for the components A, B, C and D set up these assigned interrogators TAP A, TAP B, TAP C and TAP D. Possible SoC data recording points for the trace procedure are:

- microprocessor kernels (processor kerneis) - storage elements (RAMs, storage elements)

- hardwired core would be, control parts, glue logic

- Bus interfaces

- interfaces of sensors (sensor interfaces)

- interfaces to peripheral parts - integrated FPGAs (Field Programmable Gate Array).

The data data of an interrogation point are fed to a triggering device TR (for: trigger) which switches on or off the tracing in the case of certain system parameters (for example the trigger switches on if the fault condition is met). The data al..a6, bl..b4, cl..c4 and dl..d4 recorded by the triggering device are fed to a respective filter FI, where they are selected according to the test requirements as a function of certain system parameters. The selected data al..a4, bl..b3, cl, c4 and dl, d2 are referred to in a source identifier SI (for: source identifier) as for the component in question.

A time slot control TSC (for: Time slot control) asks per clock cycle one after the other (polling) according to the priority of a TAP for a necessary date ("necessary" is indicated by a signal bit from the TAP). The necessary data of the TAP are provided with a source identifier so that data of a TAP can be reassigned outside the chip in post-processing (summarized in a separate file, table, statistics, etc.). In addition, a time stamp is assigned (eg counter value of a revolving counter). Data that are in the same clock cycle are given the same time stamp and are offered according to their priority to the TD FIFO recording data memory (for: Trace Data First In First Out). In post-processing processing, the time sequence can thus be determined exactly. If the time stamp is implemented as a revolving counter, it is advisable that the time slot controller uses an active status word (keep alive trace word) for every counter return (e.g. with si = 0) if there is no overflow status (ov) of the recording data memory (overflow FIFO state) is present. This is also useful when activating the tracer after a reset, since a connection setup is already proven when the keep alive words are received. If an overflow FIFO state occurs during the transfer of a trace word to the TD FIFO, this is not transferred; the transmission of the trace word from the TAP with the highest priority is always possible. In the event of data loss (Fig. 1: as denoted by DL d2 for: Data Loss d2) due to overflow, this state is identified by an overflow bit in the one trace word, which can also be transmitted in the overflow state and which has the same time stamp, how the non-transmitted trace word has (Fig. 1: the trace word with a3 before d2); It is always possible to transfer a trace word per clock cycle, even in the overflow state. The overflow state of the

FIFOs are broken down if data required by no TAP are created in a clock cycle; Cancellation of the overflow bit.

The management of the FIFO and the insertion of the overflow bit in the trace word is done in the trace data FIFO. The FIFO is able to store trace words in the FIFO per clock cycle according to the number of TAPs; 1 shows that a maximum of 3 trace words per clock cycle are stored in the FIFO, that is, according to their priority at ts = 1 here al, bl, cl / dl. At the FIFO output, a trace word is written to the recording interface TI (for: trace interface) per clock cycle, which corresponds to the HWT (HW Tracer, standard recording device). The recording interface TI is formed with a plurality of connections on the housing that accommodates the SoC components. The number of connections of the recording interface TI is considerably smaller than if for each of the plurality of recording points TAP A..TAP D a separate interface would be arranged on the housing.

Programs for post-processing can be used via a PC interface on the HWT.

In the trace procedure / algorithm according to the object of registration, a distinction is made between necessary and unnecessary trace data according to the test requirements (data selection). Practical data selection is always possible in practice. This makes it possible to transfer the necessary trace data from the various SoC components to the trace bus one after the other in a time slot process. The time information is fully preserved through the use of a time stamp, so that the time behavior of the data with respect to one another can be restored in postprocessing. The buffering of the sequentialized data in a FIFO enables data bursts to be intercepted. Adjustable filters and trigger points reduce the data to the necessary data. In principle, it is possible to trace any number of different SoC components using the time slot method, with the time slots being assigned using a prioritized polling principle. If on average the total of the data streams of the SoC components exceeds the transmission rate of the trace interface, a data loss will occur. The trace words of the SoC component with the highest priority are always transmitted.

2 shows the trace algorithm of the trace method

The algorithm is started at 201, everything is reset to 202 at 202 (reset all). At 203, a procedure according to FIG. 3 for processing a recording point with priority 1 (processing TAP with priority 1) is carried out. At 204, a procedure according to FIG. a recording point with priority 2 (processing TAP with priority 2). At 205 further procedures according to FIG. 3 for processing a recording point (other TAP s) are carried out. At 206, a procedure according to FIG. 3 is carried out for processing a recording point with priority N (processing TAP with priority N). At 207, the time stamp is updated (update time stamp). at

208 a query is made as to whether the timestamp has reached its maximum (timestamp = max?). If this is not the case, the process continues at 211 as denoted by N (for: No).

If this is the case, as indicated with Y (for: Yes), with

209 continued, where it is queried whether the recording data FIFO TD FIFO has no overflow (No FIFO overflow?). If this is not the case, as denoted by N, continue with 211. Is this, as denoted by Y, the

In this case, at 210 an active status word is written into the evaluation data FIFO (write keep alive to FIFO). At 211, the oldest entry from the recording data FIFO is forwarded to the recording interface TI (write west FIFO entry to trace interface). At 212, the wait for the next clock cycle is waited to continue at 201.

FIG. 3 shows the processing of a recording point with a given priority (processing TAP with priority N). After starting at 301, a query is made at 302 whether the processing point has data present. If this is not the case, as denoted by N, proceed to 309. If this is the case, as denoted by Y, the process continues with 303, where it is queried whether the recording data FIFO has no overflow (no FIFO overflow?). If this is not the case, as denoted by N, proceed to 309. If this is the case, as denoted by Y, the process continues with 304, where the recording data are written into the recording word N (write TAP data in trace word N). At 305, an origin identifier SI is added to the record word N (add source identifier to trace word N). At 306, one becomes Add time stamp to trace word N. At 307, record word N is written to record data FIFO (write trace word N to FIFO). At 308, the state of the record data FIFO is updated (update FIFO state). At 309 there is a go back.

The procedure presented here is based on a synchronous SoC design. In principle, however, asynchronous components can also be connected to the time-slot control, which operates in isochronous mode, and then clocked in.

Claims

claims

1. A method for tracking data and its states in an arrangement in which a semiconductor chip (SoC) has a plurality of components, accordingly,

- the data (data) of a recording point (TAPA..TAPD) are recorded in accordance with a triggering device (TR),

- there are several recording points,

- the data are selected according to the setting of a filter (FI),

- the data are provided with an origin indicator (SI) and a time stamp (ts),

a time slot controller (TSC) which queries recording points, the data are forwarded to a recording interface (TI) of the semiconductor chip.

2. The method according to claim 1, characterized in that the time slot controller polls the recording points in accordance with their priority.

3. The method according to claim 2, characterized in that the data are forwarded to the recording interface in accordance with their priority.

4. The method according to any one of the preceding claims, characterized in that the data are provided as a time stamp with a cyclically continuous counter reading.