TW526575B - Electronic part - Google Patents
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- Publication number
- TW526575B TW526575B TW090129921A TW90129921A TW526575B TW 526575 B TW526575 B TW 526575B TW 090129921 A TW090129921 A TW 090129921A TW 90129921 A TW90129921 A TW 90129921A TW 526575 B TW526575 B TW 526575B
- Authority
- TW
- Taiwan
- Prior art keywords
- electronic component
- substrate
- bumps
- bonded
- weight
- Prior art date
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
- H03H9/02—Details
- H03H9/05—Holders; Supports
- H03H9/058—Holders; Supports for surface acoustic wave devices
- H03H9/059—Holders; Supports for surface acoustic wave devices consisting of mounting pads or bumps
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05573—Single external layer
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- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/05624—Aluminium [Al] as principal constituent
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- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
- H01L2224/05666—Titanium [Ti] as principal constituent
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- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/061—Disposition
- H01L2224/0612—Layout
- H01L2224/0615—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
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- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
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- H01L2224/13144—Gold [Au] as principal constituent
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
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Landscapes
- Physics & Mathematics (AREA)
- Acoustics & Sound (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Surface Acoustic Wave Elements And Circuit Networks Thereof (AREA)
- Wire Bonding (AREA)
Description
526575 A7 _______B7_______ 五、發明說明(() 技術領域 本發明有關一種電子部件,該電子郵件包含一電子元 件以及一基板,該基板上安裝該電子元件。 發明背景 近年來’包含電子元件及其上安裝該等電子元件之基 板的電子部件之大小及高度已漸增地變小。在此等情勢中 ,常採用所謂倒裝片製程(flip-flop process)即,其中一電 子元件之一預定表面與一基板之一預定表面係藉由導電凸 塊而機械地或電性地相互連接的方法。 第1A及1B圖係利用相關技術普遍所使用之倒裝片法 電子部件10之個別不同的縱向橫剖面圖。 如第1A及1B圖中所示,電子部件1〇包含一電子元 件20以及一基板30,且該基板30上安裝該電子元件20。 如第1A圖中所示,電子元件20之一預定之功能性表 面120係定位以便以一特定方向(第1A圖中向下地)面向, 且相反於基板30之一預定之安裝表面130,該電子元件20 與基板30藉由金屬凸塊40而彼此電性地及機械地連接, 該金屬凸塊40則插置於該電子元件20與基板30之間。此 外,如第1B圖中所示,爲強化該連接,例如在半導體裝 置領域之中,一般熟知的是充塡樹脂90於電子元件20與 基板30間的方法,使用於上述目的之樹脂90則大致地稱 爲下方充塡物。 然而,在其中電子或類似物係配置於諸如表面聲波元 件之電子元件的功能性表面上且若樹脂黏著於該等功能性 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) (請先閱讀背面之注意事項再填寫本頁) Φ 訂i -線丨— 526575 A7 ____B7 ___ 五、發明說明(>〇 表面時該等元件之功能無法充分地達成時,則無法施加該 下方充塡物。因此,該等電子元件係僅藉由凸塊而機械地 連接於基板的安裝表面,若以電子元件之重量爲主之該等 凸塊之總接觸面積小時,則由於掉落,振動等所造成之外 部機械性負荷,將造成其中電子元件從凸塊脫開之問題, 而劣化了電子部件本身之功能。 發明槪要 本發明已鑑於上述問題而想出。本發明之目的在於提 供一種電子部件,其中一電子元件與一基板可以足夠的強 度相互機械性地接合。 ' 爲達成上述目的,本發明之電子部件含有一電子元件 及該電子元件安裝於其之一基板,電子元件與基板係利用 至少三個凸塊而電性地或機械地相互連接,其特徵爲:藉 電子元件之重量來除接合該電子元件之該等凸塊的總接合 面積所獲之値以及藉電子元件之重量來除接合於基板之該 等凸塊的總接合面積所獲得之値兩者均至少爲8.8mm2/g。 有利的是,若藉電子元件之重量來除接合於該電子元 件之該等凸塊的總接合面積所獲得之値以及藉電子元件之 重量來除接合於該基板之該等凸塊的總接合面積所獲得之 値兩者均至少爲11.6 mm2/g。 此外,較佳地,本發明之電子部件係其中該等凸塊由 Au或一含有Au爲主要成分的合金所構成。 而且,較佳地,本發明之電子部件係其中電子元件及 基板僅藉由凸塊而相互機械性地連接。 4 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) (請先閱讀背面之注意事項再填寫本頁) _ϋ· ϋ ·ϋ n n —1 n 一— ον f ϋ ϋ— n —ϋ n n n I n A7 526575 _ B7____ 五、發明說明(3 ) 而且,在本發明之電子部件中,電子元件可爲一表面 聲波元件,包含·至少一形成在壓電基板上的IDT電極。 根據本發明之電子部件可獲得足夠強度之機械接合, 即使是用於諸如含有其中下方充塡物無法使用以接合電子 元件於基板之表面聲波元件的電子部件之表面聲波裝置。 圖式簡單說明 第1A及1B圖係利用相關技術普遍所使用之倒裝片法 的電子部件之個別不同的縱向橫剖面圖; 第2圖係根據本發明一實施例之電子部件的立體圖; 第3圖係第2圖實施例之電子元件的縱向橫剖面圖; 第4圖係當作一實例電子元件之表面聲波元件的立體 圖,其功能性表面係定位於圖中之上側之上;以及 第5圖係一圖表,顯示藉電子元件的重量來除金屬凸 塊的總接合面積所取得之値與藉掉落測試所測量之故障比 例間之關係。 元件符號說明 (請先閱讀背面之注意事項再填寫本頁) 訂丨丨 •線丨-- 1 電子部件 2 電子元件 3 基板 4 凸塊. 10 電子部件 20 電子元件 21 IDT電極 22 電極墊 5 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 526575 A7 _B7 五、發明說明(Lf ) 30 基板 31 內電極端子 32 外電極端子 40 金屬凸塊 90 樹脂 130,131 安裝表面 較佳實施例之詳細說明 下文中將參照第2至4圖說明本發明一實施例。 第2·圖係根據本發明一實施之電子部件1的立體圖; 第3圖係此實施例之電子部件1之縱向橫剖面圖;此外, 第4圖係一電子元件2之立體圖,其在此實例中係一表面 聲波元件,具有一定位於其上側之上的功能性表面12,當 配向如圖中所示。 在此實施例中,該電子部件1係一表面安裝部件,且 係安裝於一主機板(未圖示)之上。如第2、3、及4圖中所 示,電子部件1包含電子元件2及基板3,例如電子元件2 爲一表面聲波元件,具有至少一 IDT電極形成於一壓電基 板之一預定功能性表面上;基板3係由諸如陶質材料,樹 脂,或類似物所製成,且具有一安裝電子元件2於上之預 定安裝表面。具有電子元件2安裝於該處之基板3覆蓋有 一蓋,且電子元件2亦覆蓋有蓋,雖然並未顯示於第2、3 、及4圖中。 如第4圖中所示,在一表面聲波元件之電子元件2之 中,用於發射一接收一表面聲波之TDT(內指狀)電極21及 6 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) (請先閱讀背面之注意事項再填寫本頁) -------訂---------線~ 526575 A7 _ B7_.___ 五、發明說明(f ) 電極墊_ 22係形成於其一預定功能性表面12之上,該IDT 電極21及電極墊22係形成使得可獲得預定的電性特徵, 例如由金或含有金爲主要成分之合金所構成之金屬凸塊4 係形成於電極墊22之上。在此實施例中,如第4圖中所示 ,一金屬凸塊4係形成於4個金屬墊22之各金屬墊22之 上,用於該等金屬凸塊之形成係採用眾所皆知之打線凸塊 法(wire-bumping method) 〇 若金屬凸塊係以總數1或2個形成時,則可由掉落或 類似者造成之機械性衝擊會將立即施加一諸如動量之力於 電子部件1,所以對於衝擊而言,電子部件1之耐久性將 劣化,爲此理由,較佳地,該等金屬凸塊4係以至少3個 的數目形成。 電極墊22包含導電電極,各導電電極含有鋁(A1)爲主 要成分,其係形成一底部電極上而具有一接點金屬(含有鈦 (T〇、鎳(Ni)、鉻化鎳(NiCr)或類似物爲主要成分之薄膜)插 置於該等墊與底部電極之間,該底部電極係與IDT電極22 同時藉眾所皆知之光成像術所形成,雖然並未顯示於第4 圖之中。 如第2及3圖中所示,內電子端子31係配置於基板3 之預定安裝表面13之上且連接於金屬凸塊4。此外,藉其 可表面地安裝電子部件於一主機板(未圖示)上之外電極端 子32係形成於基板3相反於安裝表面13之面上,內電極 端子31與外電極端子32係藉由形成於基板3之面上之導 體而相互地電性連接。在此實施例中,內電極端子31,外 __ 7 本紙張尺度適用中國國家標準(CNS)A4規格 χ 297公釐) (請先閱讀背面之注意事項再填寫本頁) --------訂---------線""· 526575 A7 ___B7____ 五、發明說明(t ) 電極端子32,及連接該等端子之導體含有鎢(W)爲主要成 分且具有鎳及金分別地依電鍍於該處之上。 在此實例中爲表面聲波元件之電子元件2係藉例如眾 所皆知之倒裝片接合法,利用超音波及熱量二者皆有地經 由金屬凸塊4而電性地及機械地連接及固定於形成在基板 3安裝表面13上的內電極31,電鍍有金之內電極端子31 的表面可由於金-金接合而充分地接合於由金所構成或包含 金之金屬凸塊。應注意的是,並未使用下方充塡物或類似 物,因爲電子元件2爲表面聲波元件。 在上述電子部件1之中,藉電子元件2之重量來除其 中金屬凸塊4與電子元件2相互接合的總面所獲得之値以 及藉電子元件2之重量來除其中金屬凸塊4與基板3相互 接合的總面積所獲得之値二者係設定於8.8 mm2/g,也就是 說,因爲並未使用下方充塡物,此係執行以便防止電子元 件2與基板3之間的機械接合劣化。 下文中將參照第5圖說明藉掉落測試所測量之電子部 件1之故障比例,藉電子元件2之重量來除其中金屬凸塊 4與電子元件2相互接合的總面積所獲得之値,·以及藉電 子元件2之重量來除其中金屬凸塊4與基板3相互接合的 總面積所獲得之値之間的關係。 第5圖係一圖表,顯示藉電子元件2的重量來除其中 金屬凸塊4與電子元件2相互連接之總面積所取得之値與 藉掉落測試所測量之故障比間的關係。 用於掉落測試,製備1〇〇個各含有當作電子元件2之 8 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) (請先閱讀背面之注意事項再填寫本頁) -------訂·-------I 丨 -- 526575 A7 __—_____________B7_____ 五、發明說明() 具有3·52 mm2/g重量之鋰氧鉅(Li Ta 03)之表面聲波元件的 樣品且安裝於基板及接受荷重掉落測試,測量故障比例, 尤其該測試係執行於假設該電子部件將使用於行動電話中 。一樣品係固定於100g重量的上面(即,相反於該重量掉 落時將接觸於地面之面)而以將測量之電子元件2之六面中 的一表面接觸於該重量的上面,使該樣品從1.5米之高度 掉落16次,此係執行用於具有實質矩形平行四邊形的電子 元件2的六面之一。在此掉落測試中,接合於基板3之金 屬塊4的總接合面積係比接合於電子元件2之金屬凸塊4 的總接合面積更大。 在此實施例中,接合於電子元件2之金屬凸塊4的總 接合面積以及接合於基板3之金屬凸塊4的總接合面積將 確定如下。 關於接合於電子元件2的金屬凸塊4的總接合面積, 在倒裝片接合法之中,含有金當作一主要成分之金屬凸塊 4係接觸於含有鋁爲主要成分而形成於電子元件2之上的 電極墊22,而施加超音波或熱量以使金與鋁相互擴散,使 形成金與鋁的合金層,該合金屬會促成接合,所以該合金 層的接合面積係視爲總接合面積。爲確定總接合面積,將 本發明之電子部件1浸入於塩酸之內以溶解含有鋁爲主要 組件的電極墊,藉此,含有金爲主要成分之金屬凸塊4會 分離自電子元件2。金屬凸塊4之表面的觀察顯示金在顏 色上爲金色的’而包含金及鋁之合金層爲灰色,測量分離 前接觸電極墊22以及其上形成鋁及金合金層之各金屬凸塊 9 本紙張尺度適用中酬家標準(CNS)A4規格(210 X 297公爱) ' " " (請先閱讀背面之注意事項再填寫本頁) -------訂·-------. I -- 526575 A7 ____B7___ 五、發明說明( 4之表面部分的面積,該等面積之總計係視爲接合於電子 元件2之金屬凸塊4的總接合面積,利用可執行計算之顯 微鏡來計算其上形成鋁及金合金層之金屬凸塊4部分的面 積。 關於接合於基板3之金屬凸塊4的總接合面積,基板 的接合面積電鍍有金,而金屬凸塊4含有金當作主要成分 ,所以基板3與金屬凸塊4係利用相同形式材料相互接合 。因此,測量各凸塊4之接合面積,且取總面積爲接合於 基板3之金屬凸塊4的總接合面積。各凸塊4之接觸面積 藉紅色檢查法或類似法予以測量,根據紅色檢查法,電子 部件係浸入於組色油墨之內使得電子部件之表面著色紅色 ,之後,使金屬凸塊分離自基板,及測量該基板來著色紅 色之部分的面積。 如第5圖中所示地,對於藉電子元件2之重量來除接 合於電子元件2之金屬凸塊4的總接合面積所獲得之6.000 mm2/g値而言,藉掉落測試所獲得之電子部件1的故障率 爲 3 1 % 〇 此外,對於藉電子元件2之重量來除接合於電子元件 2之金屬凸塊4的總接合面積所獲得之8.000 mm2/g之値而 言,藉掉落測試所獲得之電子部件1的故障率爲15%。 另一方面,對於藉電子元件2之重量來除接合於電子 元件2之金屬凸塊4的總接合面積所獲得之8.800 mm2/g 之値而言,藉掉落測試所獲得之電子部件1的故障率低, 亦即7%。 10 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) (請先閱讀背面之注意事項再填寫本頁) 訂--- 線丨-- 526575 a? B7 ----------^---— 玉、發明說明(了) 用於8.800mm2/g之此値’只有限少數之例子,例如其 中當由於使用者不小心而掉落行動電話小於100次之時, 所以當故障率降低至7%時,可認爲該電子部件1之耐久性 在其實際的使用中實質地沒有問題。 因此,較佳地,藉電子元件2之重量來除接合於電子 元件2之金屬凸塊4的總接合面積所獲得之値係設定於 8.8mm2/g或更高,藉此,可提供具有由掉落所造成之故障 率低的高品質電子部件。更佳地,藉除接合於電子元件2 之金屬凸塊4的總接合面積所獲得之値可設定於 11.6mm2/g或更高,在此例中,掉落測試顯示0%的故障率 ,在實用上可實質較佳地防止掉落所造成的故障。 應注意的是,此掉落測試係涉及其中接觸於基板3之 金屬凸塊4的總接觸面積比接合於電子元件2之金屬凸塊 4的總接合面積更大的例子。相似的結果亦獲得於其中接 合於電子元件2之金屬凸塊4的總接合面積比接觸於基板 3之金屬凸塊4的總接觸面積更大的例子。 雖然上述說明給定了根據本發明一實施例之電子部件 的較佳結構及性質的細節,但應瞭解的是,本發明並未受 限於其中所述之特定處。更特別地,可作成許多修正及變 化。 例如,在此實施例中該等金屬凸塊4係藉打線凸塊法 所形成,但未受限於此方法,例如可藉電鍍法來形成該等 金屬凸塊4。 此外,在此實施例中,可疊層含有鋁爲主要組件的導 _ 11 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) (請先閱讀背面之注意事項再填寫本頁) 訂i 線丨-- A7 526575 _ B7___ 五、發明說明(le) 電材料與接觸金屬來當作電極墊22之結構的實例,但該疊 層並無限制性,該等電極墊22可以同時地與IDT電極21 藉光成像術來形成,層的數目可視需要地選擇。此外’ IDT電極21與電極墊22的組態並未受限於第4圖中所示 之該等組態。 在此實施例中,雖然內電極端子31,外電極端子32 ,以及連接該等電極之導體各具有其中鎳及金係電鍍於鎢 (W)上的結構,但並未受限於此。較佳地’最上層係由金 所製成以用於其對於由金或由含有金爲主要成分之合金所 製成的金屬凸塊的充分連接性。 而且,在此實施例中,雖然該倒裝片接合法採用超音 波及熱量,但可應用使用熱量或超音波之倒裝片接合法而 無任何問題。 此外,在本發明之此實施例中,雖然採用安裝於一$ 機板上之表面安裝部件當作電子部件1以作爲一實例,但 共未受限於此。無庸置疑地,本發明可應用於一包含直接 安裝於主機板上之電子元件的電子部件(圖中未示出)。 產業利用性 根據本發明之電子部件,藉電子部件之重量來除接合 於該電子元件之複數個凸塊的總接合面積所獲得之値以及 藉電子元件之重量來除接觸於基板之凸塊的總接觸面積所 獲得之値二者係設定於8.8mm2/g或更高,或較佳地設定於 11.6mm2/g或更高,因此,可獲得足夠強度的機械性接合 ,即使是用於諸如各含有一表面聲波元件的表面聲波裝置 12 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) (請先閱讀背面之注意事項再填寫本頁) 訂------
-ΙΊ n la ϋ n ϋ n ϋ n I 526575 A7 __B7___五、發明說明(Μ )之其中下方充塡物無法使用於接合電子元件於基板的電子 部件。 (請先閱讀背面之注意事項再填寫本頁) 訂— -線丨·! 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐)
Claims (1)
- 526575 B8 C8 D8 六、申請專利範圍 (請先閲讀背面之注意事項再塡寫本頁) 1. -種電子部件(1),其含有一電子元件(2)及該電子元 件(2)安裝於其上之一基板(3),該電子元件(2)與該基板(3) 係利用至少三個凸塊(4)而電性地或機械性地相互連接,其 特徵爲:藉該電子元件(2)之重量來除接合於該電子元件(2) 之該等凸塊(4)的總接合面積所獲得之値以及藉該電子元件 (2)之重量來除接合於該基板(3)之該等凸塊(4)的總接合面 積所獲得之値二者均至少爲8.8mm1 2/g。 2. 如申請專利範圍第1項之電子部件(1),其中藉該電 子元件(2)之重量來除接合於該電子元件(2)之該等凸塊(4) 的總接合面積所獲得之値以及藉該電子元件(2)之重量來除 接合於該基板(3)之該等凸塊(4)的總接合面積所獲得之値二 者均至少爲11.6mm2/g。 3. 如申請專利範圍第1或第2項之電子部件(1),其中 該電子元件(2)及該基板(3)僅藉由該等凸塊(4)而相互機械 性地連接。 4. 如申請專利範圍第1項之電子部件(1),其中該等凸 塊(4)係藉由金或一含有金爲主要成分的合金所製成。 5. 如申請專利範圍第1項之電子部件(1)’其中該電子 元件(2)爲一表面聲波元件,包含至少一形成在一壓電基板 上的IDT電極(21)。 1 2 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐)
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US20030160334A1 (en) | 2003-08-28 |
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WO2002061834A3 (en) | 2003-06-12 |
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