TW525277B - Base-free semiconductor encapsulation and method for producing the same - Google Patents

Abstract

The present invention relates to a base-free semiconductor encapsulation and a method for producing the same. The invented method comprises providing a temporary base; covering a solder mask on the surface of the temporary base; forming a plurality of lead layers and die pad layers on the portion of the surface of the temporary base which is not covered by the solder mask, in which the die pad layers are adhered with a chip, which is electrically connected to the lead layers through a plurality of solder lines; covering an encapsulation on the chip, the solder lines, the solder mask, the lead layers and the die pad layers; after cutting off the semiconductor encapsulation, etching off the temporary base to obtain a base-free semiconductor encapsulation.

Description

525277

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525277 Case No. 89124710 Description of the invention (3) The wire mining 3 is placed on a heat block 9 and a pressure plate 10 (Window Clamp) is pressed above the lead frame 3. The pressure plate 10 and the heating block 9 are used. Holding the guide pin 3 1 up and down to stabilize the guide pin 3 1 to facilitate the wire bonding work, the front side of the chip 1 is connected to the guide pin 3 1 with a bonding wire 5 conductively; however, the general qFN product is due to its guide pin 3 1 area Smaller and higher pitch (Pi tch), the guide pin 3 丄 is not easy to be held by the pressure plate 10 and the heating block 9 during the wire bonding process, and the guide pin 3 丄 is easy to shake during the wire bonding process, thus causing wire bonding. Then the yield was poor. As mentioned above, the use of a pre-made leadframe 3 to provide the wafer 1 with a-circuit connection means, it must be designed for each product manufacturing gas leadframe 3, the design and manufacturing must take a considerable amount of time; θ; • ^ ^, and for a semiconductor package, the lead frame 3 also accounts for the considerable thickness and volume of the semiconductor package, which is an urgent need for improvement for the packaging technology trending towards _thin development. .仏 4 Mounting = National Patent No. 5, 8 6 '9 0 5 as an example, the semiconductor sealing structure is designed to increase the thickness of the semiconductor package to improve the lead frame, and the design of the lead frame is omitted. It provides a side sheet through hole through which the back of the wafer is adsorbed, and then the bonding wire on the front side of the wafer is connected to the top of the wafer and the f side is called the bonding wire process. Then, the aforementioned semiconductor package is provided with a through-hole: the wafer 3 and the bonding wires are enclosed on the surface of the package. In the above-mentioned U.S. Patent No. 5,869 π η R .. t structure of the Yuxian Line, because the semiconductor package is not as old as it is / y, the semiconductor package is still ancient and can effectively reduce the size of the package. Body borrowing

It has the following several disadvantages: "Volume of clothing, 525277, amended case number 89124710, V. Description of the invention (4) 1. ϋΓ 5,8 6 9,9 0 5 semiconductor package 77 ^ structure, the wafer is used The vacuum method says that when there is a thick seam in the package junction 2, it is easy to ... If the surface of the adsorbed object is displaced (MSPUCementKS = t lowered), which causes the wafer to be processed during the wire bonding process, j: 纟 "t ^ ，，， Λ 进 仃The bonding wire manufacturing process; at this time, the wafer and the substrate are not-the vacuum is sucked on the surface of the substrate by the vacuum), the I state 2 is coupled to the f state (but the displacement is temporarily used, which causes the bonding wire to be disconnected, and the mold ^: :: force There will be a relative shape. 、 L and private clothing will also overflow. The semiconductor package will be broadcast. The material is lost.-Weight: L :: Slightly designed for the lead frame, so that = = installed; exposed; = body package. The welding wire of the piece is violently sealed and the zinc is connected to Dianqiqi. ^ The area is too small and + conducive to the future, you need to seal the clothes after the seal A soil, if you want to increase the cost of welding area. "Add additional processes later This in turn adds a lot of [invention purposes] The existence of the main B of the present invention, the present invention is connected to Solving the above-mentioned defects, avoiding the deletion and manufacturing method, so that the structure of the outer stomach, a semiconductor package without a base, and the other base pin of the present invention will not cause the overflow of glue. To improve the overflow of glue, it is possible to It replaces the original adhesive tape on the base of the strong wire for the bonding process, and provides a higher rigidity and bonding yield during the bonding process, which makes the transmission of the bonding power more complete. The bonding on page 7 525277

Another object of the present invention is that the structure of the present invention uses a generation of traditional lead frame and is tightly combined with the-base, so that it: the thickness of the package, and does not need to be traditionally determined in the wire bonding process. The guide pins on the bismuth solid lead frame are used for wire bonding work, so the situation that the disjoint parts and the guide pins are shaken can also provide semiconductor seals, and the diameter can be provided, which is helpful for the subsequent process. Another important purpose of the branch is that the structure and manufacturing method of the present invention are simple, and the reform is necessary. The benefit of the packaging process and the improvement of the quality yield of the package. To achieve the above object, the present invention provides a temporary storage base, which is covered with a welding cover on the storage base, and a plurality of guide layers are formed on a part of the surface of the temporary storage base which is not covered with the welding cover. And the wafer base layer, the guide pin layer, the wafer base layer and the welding cover are appropriately distributed on the surface of the temporary storage base, and the temporary base provides a stable support base when the bonding wire is in progress. After the molding process is completed, trimming (Trim / Form) is performed, and then the temporary storage base is removed by etching (Etching). The detailed description and technical contents of the present invention are described below with reference to the drawings: 凊 Refer to "Figure 4", which is the manufacturing flow chart of the present invention, as shown in the figure: First, provide a copper material The temporary storage base 1 1 has a proper thickness, and then the surface is coated with a layer of polyimide (Pol yi mi de) or ultraviolet-type green paint, and imaged by light lithography ( (Photolithography) process to form a solder mask 12, and electroplating conductive materials such as nickel (Ni) and gold (Au) to form a lead layer 13 and a wafer seat layer 1 4 through the wafer Wafer process, wire bonding

525277 month — case number 89124710 V. Description of the invention (6) Pressing process' and then cutting the part 2 into the base i i and removing it with the last name engraving method to obtain the semiconductor package. Please refer to "Figure 5 A", "Figure 5 B", "Flute e", "Figure 5D", "Figure p 5c", p kk ^ bE "," Figure 5 " ^ Figure :; Figure 5H "shows the steps of the embodiment of the present invention: Figure 1 shows: First, as shown in Figure 5A, 2: 2: A temporary storage base with a material and an appropriate thickness The second copper is a series of 1 with a warrior named Xiben and · 1 & Bali temporary storage base 1-, the surface of the thousand, and, as shown in Figure 5B and 5γιΙ! ^ =; The temporary storage base 1 1 All surfaces are covered with a suitable layer of photosensitive and water-sensitive lithography, such as arsenide or ultraviolet green paint, m_uth〇graphy) = = ^ Mask with circuit pattern (Mask) is used for soldering Through the layout and shadowing step, the welding mask i 2 is exposed on the surface of the aeration well f. The area of the surface is covered with:;, and then only covers the surface of the temporary storage base η :: ,, : 1st = multiple exposed areas exposed to the seat 1 1 are plated on the surface of the upper layer:: the base guide layer 13 and the wafer seat layer 14 are temporarily stored in the 5th floor. The aforementioned welding cover 1 = 1 3 and the wafer holder layer on the surface of the base; then, as described in Section 5E = and all ^ are attached to the temporary storage so that the wafer holder layer is "provided to the wafer", the glue 2 is adhered to the wafer holder On the surface of layer τ 4, the back side of the sheet 1 is used for the silver wire bonding process, and the sheet i is positive, and the lead layer 1 3 is a bonding wire made by the one provided; 2 = Junction of conductive material recording process; as shown in Fig. 5 F, 丄 3 I surface conductive connection; complete the "i, 525277 _ case number 89124710 of the welding wire 5 V. Description of the invention (7)-modified wafer seat layer 1 4, welding cover 1 2, guide 1 encapsulates the colloid 6, and completes the molding. After quoting 1 3 with the welding wire 5 and molding, as shown in FIG. 5 G, fresh ore is in the aforementioned encapsulating colloid. 6Cure Seal the package with the cutting tool according to the preset cutting path. 5 Depth to the temporary storage base i ...,? f body 6 is suitable for cutting from above] It is necessary to avoid covering the encapsulant 6 =.彳 The cutting path of the cutter 15 is tied to the working surface T of the temporary storage base i, f: and the welding wire 5, and the cutting depth: so that the package is still fixed after shear molding = storage base 1 1 俾As shown in Fig. 5 丨, after the cutting is completed, the J base 1 1 surface is removed; the temporary storage base 1 1 is removed, so that the masker / ”engraving method exposes the bottom surface of the aforementioned copper 1 4 to the entire semiconductor = Du guide foot layer 3 and the wafer. ,, and the semiconductor package of the base. A ,, and the lower surface to get a pair of two parameters :: the first cover? R Ming the other-implementation = Figure, the second 2κπ5α ^: Put the wafer on the chip), you can provide it to the wafer id w to make it into; ^ 2 = = ^? Modify the light army cloth, the surface is appropriate, and attach the wafer 1 with silver glue 2 to the welding army. ? Placed in the same process, while the guide foot layer 1 3 is to retain the original design 2 table to encapsulate the gel 6 to cover the crystal and sheet 1, the welding mask " ten meals by phase 1 2 and the foot guide sound ,: p After the above-mentioned shear molding and etching processes, the following results are obtained: The upper 3 bottom surface is exposed to the entire semiconductor package, and the semiconductor package without a base is covered. The upper surface, in the process, by Brass temporary storage base 1 1 Presence, page 10 525277

Layer 1 3 bottom guide layer 1 3 base 1 1 can also be compared at the same time, tightly combined with the molding system 6 on the molded layer 1 4 the bottom surface 3 and the wafer seat on the temporary wire rack can reduce the approach; If exposed to the whole, it will be provided to the subsequent ones. Only the metal material line force of the invention can be changed and the relative force can be generated. Therefore, it is possible to provide 1 2 and guide pin 1 1 with the remaining colloid penetrating on the surface to avoid spillage. Compared with the method, the lower surface of the conductor package can also be mentioned. The substrate process makes the preferred embodiment. According to the present invention, the guide wire 5 can be provided and then carried out in the chip 1 and temporary line process. Yield rate; furthermore, the seat base layer 1 4 only encapsulates the gel 3 and the wafer base, and the guide pin layer 1 is an electrically conductive material with a package guide member for heat dissipation. 1 3 The bottom surface is an appropriate area, but the above can be done within a limited range. Within range. In the stable energy range where a ## surface is stable, it is not easy to be affected by external forces. There are many welding covers during the temporary storage of the base. Therefore, the layer 1 4 can be avoided by the thickness of the entire surface of the base. It is within the scope of the present invention that the semiconductor package is soldered to the circuit, that is, the modification should be carried out by the base to allow the welding to pass, and the crystal to be displaced. This can be prevented from occurring to the lead layer 1 when the bonding wire is bonded to the layer 13 and the crystal. In addition, guide semiconductors such as gold and nickel are used for semiconductor sealing, and the lead layer can be used for this purpose. Only when the patent application is unknown

$ ΠPage525277 _Case No.89124710_A simple explanation of the revised version of the drawing [Simplified description of the drawing] Figure 1 and Figure 1 A Figure 1 is a schematic diagram of the conventional semiconductor package structure and glue overflow situation. Figure 2 A Figure 2B is a schematic diagram of a conventional method for preventing glue overflow. Figure 3 is a schematic diagram of a conventional fixed guide pin method. Figure 4 is a manufacturing flowchart of the present invention. Figure 5 A Figure 5 B Figure 1 Figure 5 C, Figure 5 D Figure y Figure 5 E, Figure 5 F Figure 5 G and Figure 5 are schematic diagrams of the steps of the embodiment of the present invention. Figure 6 It is a schematic diagram of another embodiment of the present invention. [Description of Symbols of the Drawings] Chip 1 Silver Adhesive ·· _ .2 Lead Frame 3 Guide Pins · < C 3 1 Chip Holder 3 2 Bonding Wires · <. 5 Encapsulated gel 6 Overflow glue. ≪ .7 Adhesive tape 8 Heating block * * .9 Pressure plate 1 0 Temporary base ·.] L 1 Welding cover 1 2 Guide pin layer <.] L 3 Wafer seat layer 1 4 cutting tools ·] L 5

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Claims (1)

525277 六 2. 5. Case No. 89124710, the scope of patent application. A base of a semiconductor package without a base-temporary storage base; structure of the structure, including: if cover, is configured in the temporary Storage-guide pin layer and a crystal ... storage = surface area; guide pin layer and the wafer seat layer; with the surface of the temporary storage base, in the uncovered area; placed in a cutting cover on the temporary storage base A wafer on the surface is a plurality of conductive elements adhered to the wafer holder, which are electrically conductive; a packaging gel is connected to the appropriate position of the 5HZ film and the guide pin layer to cover the wafer and the wafer holder layer. ; Among them, the electrical package, solder mask, and guide pin layer of the semiconductor package are removed by cutting, and after obtaining -i ', the temporary base is etched as in the scope of patent application = semiconductor package. The material of the temporary storage base is the structure of the steel housing, the conductor package, and the material of the welding cover in the second patent application scope includes the structure of the polycondensation + conductor package, and the edge material. The photosensitivity of the ultraviolet-type green paint is absolutely the same as the structure of the semiconductor package and the texture of the semiconductor package. The shell is a conductive material including nickel and gold. For example, the formation of the solder mask in item 1 and 10 of the patent application scope is based on the structure of the semiconductor package of polysilicon, and the manufacturing process makes the polysilicon Amine m = amine or UV-type green paint by light micro A __ usable external green paint is only configured in this temporary = Λ correction 525277 _Case No. 89124710_ Year Month Amendment_ Sixth, the scope of patent application Those who are part of the surface of the base. 6. The structure of the semiconductor package according to item 1 of the scope of patent application, wherein the formation of the lead layer and the wafer seat layer is formed by electroplating. 7. The structure of the semiconductor package according to item 1 of the scope of patent application, wherein the conductive element is a wire made of one of the conductive materials of gold, copper or aluminum. 8. The structure of the semiconductor package described in item 1 of the scope of the patent application, wherein the wafer base layer may also be a solder mask. 9. A method for manufacturing a semiconductor package without a pedestal, comprising the following steps: preparing a temporary storage base; forming a solder mask covering the surface area of the temporary storage base; forming a guide pin Layer and a wafer base layer, the guide pin layer and the wafer base layer are arranged in a part of the solder mask which is not covered by the temporary storage base surface; a wafer bottom surface is adhered to the top surface of the wafer base layer; A plurality of conductive elements are electrically connected at appropriate positions of the chip and the lead pin layer; the solder mask, the chip, the wafer base layer, the lead pin layer and the conductive element are covered with a packaging gel; and the semiconductor package is cut. After the cutting and forming process, the temporary storage base is removed by etching to obtain a `` baseless semiconductor package ''. 10. The method for manufacturing a semiconductor package according to item 9 of the scope of patent application, wherein the temporary storage base is made of copper. 11. The method for manufacturing a semiconductor package as described in item 9 of the scope of patent application, Page 14