TW525215B - Method of improving exipaxy wafer quality - Google Patents

Abstract

In the invention, inert gas is continuously introduced into the plasma chemical vapor phase deposition procedure of epitaxy layer deposition process. From the experimental results, defects generated in the conventional technique can be effectively reduced such that nearly perfect crystallized silicon exipaxy wafer is obtained.

Description

525215

FIELD OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor, and more particularly to a method for improving the quality of an epitaxial wafer. Background of the Invention: After decades of development, CVD has become the most important and main thin film deposition tool in semiconductor processes. For all thin films required for semiconductor components, whether it is conductors, semiconductors or dielectric materials, CVD can be borrowed. For the generation, the dielectric materials are Si02, Si3N4, PSG, and BPSG, the conductors are WS ix, W, and polycrystalline silicon, and the semiconductors are silicon: but the CVD used to make single-crystal thin films is usually `` Epitaxy ). Worm crystal refers to the thin film material that needs to be deposited according to the process of the component outside the substrate. The epitaxial film is a silicon substrate with high purity. The stupid stone common on some semiconductor components is grown on a uniform wafer crystal surface. Although the application status of two layers of pure Shixunshijing, polycrystalline silicon and epitaxial silicon films are different, they are deposited in a high temperature (600 ° C ~ 12 0 ° C) in a similar process reaction chamber. And get. The principle of epitaxy can be divided into:

(1) Liquid Phase Epitaxy (LPE) ° The crystal growth of LPE is to deposit a crystalline film by directly contacting a molten liquid material with a wafer on a substrate, which is particularly suitable for compound semiconductor devices, especially for development.

525215 V. Description of the invention (2) Optical element. (2) Vapor phase Epitaxy (VPE) 〇 The principle of VPE is to allow the raw material of stupid crystals to be transferred to the wafer surface in the form of gas or electro-polymerized particles. These particles are lost by the surface of the wafer Lattice adsorption (Adsorb), usually the wafer will provide energy to the particles in the form of heat, causing them to migrate to the lattice position and condense (Condensati ο η). At the same time, the particles and the atoms on the surface of the lattice are separated from the wafer surface by absorbing thermal energy, which is called Desorb. Therefore, the VpE procedure is actually the result of the dynamic equilibrium of the two functions of particle adsorption and dissociation.

I VPE can be divided into (a), Chemical Vapor Deposition (CVD) and (b) Physical Vapor Deposition (PVD) technologies according to the reaction mechanism. CVD is roughly applied to the growth of semiconductor crystal films and oxide layers. pv]) is mainly applicable to the deposition of connection lines. Gold (3) Molecular beam stupid crystals (Moiecuiar Beam Epitaxy, MBE).

f E 疋 The most popular epitaxial technology in recent years, whether it is I I I — v, im is the thin film characteristics of materials such as semiconductors, Si or SixGel-x, is the best of all stupid technologies. The principle of MBE is basically the same as that of high-temperature evaporation lint. 'Operating pressure is maintained at Ultra Hlgh Vacuum, „μ is about 10 to 10 t〇rr, so the wafer loading must be controlled by 1 to maintain its vacuum. 525215 V. Description of the invention (3) The epitaxial process can increase the flatness of the gate region of the device by continuous growth. The distribution of the starting material silicon has a very important help to the efficiency of the breakdown voltage of the gate oxide oxide. The low defect density requirement of the 2.5-micron device generation 'promotes the development of several wafer technologies alternately. The main crux of controlling defects lies in the polished wafers. During the crystal growth process, it is necessary to suppress the accumulation of insert-type defects and Growth of aggregated hole defects. When they intersect on the wafer surface, they converge into our common D-defects and cavity-related defects such as Crystal Origin (j pits, COPs). However, Xi In the epitaxial process of the know-how, at least a small amount of defects appear on the stupid wafer and cause a series of 1 changes. The most common type of epitaxial wafer defect is the structure Epitaxial defects (Structural epitaxy defects) and large area defects (Large area defects). Therefore to reduce structural defects and large area defects, bright epitaxy with the best cleanliness = Shi Xi wafers with round surface, only Commercial application value. It is called a clean stupid wafer surface. It must have: (1) significantly reduced recesses and crystal defects on the wafer surface; (2) no residual polishing products. The main application of stupid crystals is A very uniform crystal is formed on the wafer: it is structured so that the working efficiency of the semiconductor wafer is strong. In the traditional semiconductor process, this film is accumulated in a large batch furnace tube equipment.彳 Ran is "growth", but as semiconductor components become smaller and smaller, the circuit structure becomes more and more complex.

Page 7 525215 V. Description of the invention (4) Uniformity, process control, etc. are more important. Therefore, to solve the current epitaxial wafer process problem, we must move towards a problem-solving and more economical direction. By growing a thin film stupid layer on the wafer surface, and avoiding crystallization in the stupid wafer process, The reason is that the recess is on the surface of the wafer, and a more perfect gate oxide layer integrity (Gate ο X ideintegrity (G 〇 I)) and a reliable insulated gate (IG) component are produced earlier. Summary: The main purpose of the present invention is to provide a method for manufacturing a + conductor. Another object of the present invention is to provide a method for improving the quality of an epitaxial wafer. The method for improving the quality of an epitaxial wafer includes at least the following steps: providing a wafer in a reaction chamber and introducing a reaction gas into the epitaxial process, Pass an inert gas into the epitaxial process and form an epitaxial film on the wafer to obtain a low-defect stupid wafer. The reaction gas may be trichlorosilane and hydrogen. Wherein the inert gas is one of He, Ne, Ar, Kr, Xe, Rn or

Page 8 525215 V. Description of the invention (5) Composition of mixing. The flow ratio of the flow of the inert gas (Nob 1 e gas) to the flow of the reaction gas is 1% to 60%. The flow rate ratio between the Noble gas flow rate and the reaction gas flow rate is preferably 10% to 18 ° / °. In the plasma chemical vapor deposition process of the epitaxial layer deposition process, the present invention continuously introduces inert gas, and it is learned from the experimental results that the defects occurring in the epitaxial layer deposition process of the conventional technique can be effectively reduced, and nearly Perfect crystallization Detailed description of the invention: Detailed description: The present invention, in the process of plasma chemical vapor deposition of the epitaxial layer deposition process, 'exposes a method for improving the quality of stupid wafers' is described in detail below. Because the growth of stupid early-early-crystal films is extremely difficult, all conditions must meet epitaxial growth. Otherwise, if there are minor defects, a large area of epitaxy stacking fault will occur, that is, it cannot be formed. Comprehensive epitaxial silicon single crystal thin film, so the preparatory work before the epitaxial process must be very careful, whether it is cutting, polishing, cleaning leftover residues should be avoided.

Page 9 525215 V. Description of the invention (6) The cause of epitaxial defects that prevents the formation of epitaxial silicon single crystal thin films, and the defects of telecrystalline wafers can be classified into two types: stupid crystal defects and large area defects. . Related to the wafer substrate (S ubstrate), there are the substrate crystal structure direction (0 rientati ο η), crystal defects (Crysta 1 defect), surface contaminants (Surface contaminants) and surface damage (Surface damage); Related to the environment, there are pollution and cleanliness during the loading and unloading process, and the growth temperature is related to the epitaxial growth process.

(Growth temperature), growth rate (Growth rate), simultaneous etch (In si tu-etch) and reaction device integrity (Reactor integrity). 1 The invention belongs to the vapor phase epitaxy method. At a temperature lower than the melting point, a layer of single crystal silicon is grown on the __y day circle. The silicon can be doped with divalent or pentavalent impurities. Influence of dopant pattern (N or?) And concentration on the epitaxial growth process. The epitaxial crystal needs a silicon source and a dopant source. The silicon source used in the present invention is trichlorosilane (1 > 1 with 10 ^ 31131 ^ / shell TCS, S1HCI3). Trichlorosilane is a colorless smoky liquid; Hydrogen dopant is introduced as the dopant source, in order to reduce the risk of hydrogen dopant in the jade process, and hydrogen (¾) is added to dilute and store to participate in the process reaction. See Figure 1. Figure 1. Crystal reaction The device includes a reaction chamber 100, which is a schematic diagram of a cat's daily reaction device. Yiyi, temperature controller 102, gas input ^

525215 V. Description of the invention (7) 104, exhaust end 106 and wafer access device 108. The reaction chamber 100 is a space for storing wafers and provides a working chamber for stupid crystals to perform stupid deposition reaction. The temperature controller 102 is a device that can heat and control the temperature of the reaction chamber. The gas input terminal 104 does In order to input the reaction gas source, the exhaust end 106 can exhaust the reacted gas; the wafer access device 108 is used as a medium for the wafer to enter and exit the reaction chamber. After the wafer 110 is placed in the reaction chamber 100, the epitaxial deposition reaction is started. The heating is started with the temperature controller 100, the operating voltage is about 12 KV to 16KV, and the operating bios voltage is about 10 KV to 1000KV, and the temperature of the reaction gas is controlled between 1100 t: to 1250 t :, and the wafer substrate is heated, and the temperature of the wafer substrate is about 110. (3 to 13 0 ° C, the pressure in the reaction and chamber is about 1 t 0rr to 1000 torr, and trichlorosilane, hydrogen, and noble gas are continuously introduced from the gas input terminal 104. Gas flow, three gas silane is about 1 seem to 100 0 seem, hydrogen is about 1 sccm to 1000 sccm & inert gas is about 1 seem to 1 0 0 seem. Among them, argon (Ar ), The flow ratio of argon flow to the reaction gas flow of trichlorosilane and hydrogen is 丨 0%. In the epitaxial process, the particles of inert gas can bombard the wafer surface and take away the particles on the contaminated surface to achieve the cleaning effect. After the reaction is completed, a stupid wafer 110 can be obtained, and the improvement of the epitaxial quality obtained can be seen from FIG. 2, which is a graph showing the relationship between the number of epitaxial defects and the flow of the inert gas in the present invention, and the vertical axis is large-size particles. The number of Large Particle Defects (LPD). The horizontal axis is the ratio of the flow rate of the pure gas to the flow rate of the reaction gas. 8-inch epitaxial wafers

Page 11 525215 5. Description of the invention (8) As an example, at a passivation flow rate of 10%, most of the LPDs have disappeared. There are about 8 LPDs with a size of 1.2 microns, There is one LPD with a size of 0.9 micron, and after passing the passivation gas flow rate exceeding 10%, the LPD of all sizes has disappeared. In the present invention, a passivation gas is passed in during the stupid crystal deposition reaction process without affecting the epitaxial deposition rate. As shown in FIG. 3, FIG. 3 shows the relationship between the epitaxial deposition rate and the flow rate of the pure gas to the reaction gas. In the figure, the vertical axis is the deposition rate of the worm crystal layer, and the horizontal axis is the ratio of the inert gas flow rate to the reaction gas flow rate. When the flow rate ratio of the passivation gas is 10%, it is still maintained at a daily rate of 2,000 Å / minute from day to day> and the present invention shows that before the flow rate ratio of pure gas flow is 18% It does not cause island delays in process time. The invention has the advantages of (a) improving the quality of the epitaxial wafer, reducing the defects of the stupid crystal process, and meeting the quality requirements; (b) low cost, without having to spend too much cost and changing processes and equipment; (c) not Affects the epitaxial growth rate, 'can also meet the requirements of process time and increase production capacity. The present invention is explained in the preferred embodiment as above. It is not intended to limit the present invention, and those skilled in the art can make some changes and modifications without departing from the spirit of the present invention & The appended application & scope of profit and its equivalent are determined. Month-

525215 Brief description of the drawings Brief description of the drawings: Figure 1 is a simplified diagram of an epitaxial reaction device. FIG. 2 is a graph showing the relationship between the number of stupid crystal defects and the passivation gas flow in the present invention. Figure 3 is a graph showing the relationship between the deposition rate of stupid crystals and the flow rate ratio of pure gas flow in the present invention. Explanation of drawing number: reaction chamber 1 0 0 temperature controller 1 0 2 gas input end 104 exhaust end 1 0 6 wafer access device 1 0 8 stupid wafer 11 0

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Claims (1)

525215 6. Scope of patent application 1. A method for improving the quality of an epitaxial wafer, including at least the following steps: providing a wafer in a reaction chamber; introducing a reaction gas into the epitaxial process; introducing pure gas (Noble gas) in In the stupid process, and forming a stupid thin film on the wafer to obtain a low defect stupid wafer. 2. The method according to item 1 of the patent application range, wherein the reaction gas can be trigas silane (SiHCl3) plus hydrogen (H2). 3. If the method of the scope of patent application is applied, the inert gas (Noble gas is one of He, Ne, Ar, Kr, Xe, Rn or a mixture thereof). Method, wherein the ratio of the flow rate of the noble gas to the flow rate of the reaction gas is 1% to 60%. 5. The method according to item 1 of the patent application scope, wherein the noble gas flow rate and the reaction gas flow rate The obtained flow ratio is 10% to 18% in the preferred embodiment c Page 14