525032 A7 B7 經濟部中央標隼局員工消費合作社印製 五、發明説明（1 ) 琎明所鼷的持術領域 本發明偽有關載置著以薄膜電晶體（以下稱為TFT( Thin Film Transistor)為開關元件之主動矩陣型液晶顯 示装置及其製造方法者。 習知捋術 第17圖偽表示載置著具有習知低霄阻信號配線之TFT 型液晶顯示裝置的TFT之TFT陣列基片的製造步驟之截面圖 。於圖中，1為玻璃基Η等之透明絶綠性基Η、2為具有於 透明絶線性基板1上形成的闞電極之閛配線、3為共同配線 、5為閘配線2上形成的閘絶綠膜、6為介由閘絶線膜5而於 閘電極2上形成的半導體層、7為於半導體層6上形成的歐 姆式接觸層、8為像元電極、10、11為於歐姆式接觸層7上 形成的源極及汲極、12為保護膜。 其次說明載置著習知TFT之TFT基片的製造方法。首先 ，如第17圖（a)所示般，使於透明絶線性基H1之表面上形 成由AI或A1合金之比電阻值較小的金屬而成之單層膜後， 採用藉由照相製販法形成的光阻層作成電路布局圖案，形 成具閘霄極之閘配線2及共同配線3。其次如第17圖（b)所 示般，在連纊形成電漿CVD法形成閘絶線膜5之矽氮化膜， 及不定形矽膜經摻雜雜質的η +型不定形矽膜後，採用藉由 照相製販法形成的光阻，同時對不定形矽膜及n +型不定形 矽膜作成電路布局圖案，於閘配線2之上方位置上形成半 導醱層6及歐姆式接觸層7。 其次，如第17圖U)所示般，形成透明導霄糢[T0( (請先閱請背面之注意事項再填寫本頁) 裝. 訂 本紙張尺度適用中國國家標隼（CNS ) Α4規格（210 X 297公釐） 3 9 0 0 8 525032 A7 B7 五、發明説明（2 )525032 A7 B7 Printed by the Consumer Cooperatives of the Central Bureau of Standards of the Ministry of Economic Affairs. 5. Description of the Invention (1) Field of the Invention The present invention is related to the placement of thin film transistors (hereinafter referred to as TFT (Thin Film Transistor)). It is an active matrix liquid crystal display device of a switching element and a method for manufacturing the same. Fig. 17 shows a conventional TFT array substrate on which a TFT on which a TFT liquid crystal display device with a conventional low-resistance signal wiring is mounted is mounted. A cross-sectional view of the manufacturing steps. In the figure, 1 is a transparent green insulating substrate such as glass substrate, 2 is a wiring having a rhenium electrode formed on a transparent insulating substrate 1, 3 is a common wiring, and 5 is a gate. The gate insulation green film 6 formed on the wiring 2, 6 is a semiconductor layer formed on the gate electrode 2 via the gate insulation film 5, 7 is an ohmic contact layer formed on the semiconductor layer 6, 8 is a pixel electrode, 10 and 11 are source and drain electrodes formed on the ohmic contact layer 7, and 12 is a protective film. Next, a manufacturing method of a TFT substrate on which a conventional TFT is mounted will be described. First, as shown in FIG. 17 (a), As shown, AI or A1 is formed on the surface of the transparent insulating base H1. After a single-layer film made of metal with a low specific resistance value of gold, a photoresist layer formed by a photographic method is used to form a circuit layout pattern to form gate wiring 2 and common wiring 3 with gate poles. As shown in FIG. 17 (b), after the flail formation plasma CVD method is used to form the silicon nitride film of the gate insulating film 5 and the amorphous silicon film is doped with an impurity-doped η + type amorphous silicon film, the borrowed A photoresist formed by a photographic method, and at the same time, a circuit layout pattern is formed for the amorphous silicon film and the n + -type amorphous silicon film, and a semiconducting hafnium layer 6 and an ohmic contact layer 7 are formed above the gate wiring 2. , As shown in Figure 17 U), form a transparent guide mold [T0 ((Please read the precautions on the back before filling this page)). The size of the paper is applicable to China National Standard (CNS) Α4 specifications ( 210 X 297 mm) 3 9 0 0 8 525032 A7 B7 V. Description of the invention (2)
Indium Tin Oxide)膜後，採用由照相製販法形成的光阻 作成電路布局圖案，以形成像元電極8 。其次，於歐姆式 接觭層7上形成源極10及汲極11。因此，源極10及汲極11 傺具有為改善與n +型不定形矽膜間之歐姆式接觸特性而於 下層上由阻障金屬Cr或Ti等而成的膜，為達低電阻化由比 電阻值較小的A1或A1合金而成的膜構成的二層膜構造。藉 由使AI膜形成電路布局圖案而用的光阻之顯影液，A1膜溶 解於顯影液中，構成由A1膜及基底而成的像元電極8之ΙΤ0 膜在顯影液中引起電池反應，故為防止IT0膜受腐蝕，亦 有添加W等作為A1合金之情形。最後如第17圖（d)所示般， 使氮化矽成膜而形成保護膜12。 發明欲解泱的護頴 如上述般，於習知的TFT型液晶顯示裝置，為得低消 (請先閱讀背面之注意事項再填寫本頁) 經濟部中央標隼局員工消費合作杜印製 層的力金或洗周刻 ，外 ， 單阻強条射清埃蝕cr以形 之電等A1噴 之塵受 由金情 膜低 子使水 子及不M合之 金成刷 成純刷 埃膜對A1線 合構 用形由 用塵颶 ，之配 A1以採在藉採，金又屬號 或膜 ， ， ，行埃条 。金信 膜層軟此際進塵A1低等成 A1多柔因之可之之降此形 由之較 。阻 不面分 率有以 用膜 於痕光 惟表部 品含膜 採 颶 由傷的 ，膜 該良或 颶 在 金颶成 用的除 ，使 ·金 , 条 金生而 能去罩 象 膜的 置A1条 會案可全遮現»高 装有AI上圖有完為路金較 示上 ，面局 偽能成 短的度 顯層形表布洗未即成成硬 晶面情 膜路清 ，阻 生而之 液表之在電行果光 ，ΜΟ等 之於線 ，成進結的箸或膜 功或配時作波 。存存Ta金 電 ，號 洗膜音業殘殘 ·合 耗膜信清颶超作圍而Ti的 本紙張尺度適用中國國家標準（CNS ) A4現格（2丨0X297公缓） 4 3 9 0 0 8 525032 A7 B7 五、發明説明（4 ) 案缺陷部經予蝕刻後所欲去除的光阻電路布局圖案所構成 者。 經濟部智慧財產局員工消費合作社印製 液 透與線 形成片 控及之 ·， 成 相 形 ，及電 該 ：*, 配間 而基 成極層驟 而。料 而 成極制 , 有 層極曆 膜一形 電罩步 線狀材 案 構電控 中具 體電體 電第在 制遮之 配形之 圖 .所制及 樣片導一導導與：控於部 極的線 局 板控極 態基半第半明則括覆覆陷 電部配 。布 基成電 一一 ·，、 與 透片包 被被缺 制口極 者路 二形制 另第線極線 的基法 至予案 控開電 成電 第由控 之，配電配 接二方層未圖 或有制 構成 與 ·，此 法片極一極連第造罩刻局 極具控。所膜 板板覆 方基電 第電氣；製遮蝕 布 電上及 者案屬。基 基被 造二 制之制電片該成與路 制分極成圖金者一性成 製第控件控極基在形 ·，電 控部電形局使成第緣層 之 及及元及電一 徵，驟的 由一 制所布 為構由 絕罩 置片極體極 二第特後步線 於少控料路及所置明遮 裝基 電導電第的其線的配。係至成材電膜案裝透成 示一制半制與極 ·，配狀極驟，之構之阻羼圖示：形 顯第控成控由電料極 形電步狀間與刻光金 局顯有 ， 晶括 •，構 於及} 材電之 制之形 案由蝕 由由布 晶具後 液包 片同；；el晶 制線控 層之圖 係的係 係路 液板線 明置基 共極膜IX液控配 及罩層 局層性 層層電 明基配 發裝性 層電緣(P持及極極遮罩布罩擇罩罩阻發一極 本 示緣體 二 絕元挟極電電除遮路遮選遮遮光本第電 顯絕導第的像同電制制去 電 可 的 中制 晶明 半 及成 之共制 控控及 的 互 成 其控 IL---,-----------IT----- (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 6 (修正頁）39008 525032 A7 B7 五、發明説明 經濟部智慧財產局員工消費合作社印製 陷；配之成。顯有極一極連片控及覆驟 案上 構控同 缺層極層而料晶具電第電氣基於膜被步 圖子 所、共 案體電體膜材液係制之制電一除緣膜之 局端 片極層 圖導一導電晶該片控件控極第去絕緣部 布極 基電體 局半第半導液，棊及元及電·與··之絕陷 路電 二制導 布；、與明持中一線體極二則含間及缺 電制 第控半 路線極線透挟法第配導電第片包案膜案 的控 及 ·， 與 電配電配的時方該極半制與基法圖護圖 鄰除 片片； 的極一極接同造，電成控由二方局保局 相去 基基層 覆電第電連片製成制構於·，第造布為布 線與 一性體 被制之制氣基一構控同；膜；製路未路 配可。第緣導 層控件控電一另所、共極緣極該電匆電 極係者由絕半 罩及元及極第之片極層電絕電在的蝕之 電，行係明 ； 遮極體極電與置基電體二的元徵鄰及線 制驟進置透子 為電導電二則裝二制導第成像特相·，配 控步時裝：端 未制半制第片示第控半及形之其線驟極 或的同示有極 刻控成控與基顯及·，與線間成，配步電 極膜驟顯具電 触的構於，二 晶片片 ·，配之而料極的制 電護步晶係制 , 成同 ·，膜第液基基層極層膜材電分控 制保的液片控 狀形共極緣 ·，的一性體電體電晶制部及 控及膜的基及 形所層電絕極明第緣導一導導液控一極 於膜緣明一線 之驟體二的電發由絕半第半明持或之電 除緣絕發第配 線步導第成元本置明；、與透挾極膜制 去絕述本該極 配之半及形像 裝透子極線的同電護控。 之上 ，電 極部與線間之 示 ··端電配接共制保的者 間之 成制 (請先閲讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 7 (修正頁）39008 525032 A7 B7 五、發明説明（6 構成半導體元件之第一電極、第一電極配線及第二電極 經濟部智慧財產局員工消費合作社印製 膜 ·，在膜電短 顯 透與線所成料A1清者 該金 表極一 緣極除 緣的之 晶 ：·， 配 間而材 成子成 ，合 之電第 絕電去絕覆線 液有層極之膜晶形刷形 片A1膜制之 的元中 之被配 該 具體電 層電液 序用而 基或 層控件 成像其間未極 ，片導一體導持依與驟 二A1二及元 形之，案上電 中基半第導明挾：·，步 第成此極體 所成料圖膜制 法一 半透同 由驟之 與形 洗電導 間而材局緣控 方第線極與的共藉步膜 片序清斜半 之膜晶布絕或 造該配電線接片係的層 基依子控成 層電液路及極 製，極一配連基線膜二 一 •，刷的構 體導持 電膜電 一 片電第 極氣一 配層刻 第片 用成同 導明挟近護制 再基制之電電第極二蝕 括基，形共 半透時鄰保控 之二控件制極此電之 Μ 包性後所層 與的同之刻止 置第及元控電與制屬阻 置緣膜膜體 線接片線蝕防 裝與極體及二 則控金光裝絕層層導 配連基配 ，κ示 片電導 極第片 及的成 示明 二二半 極氣一極後， 顯基制半電與基極高形 顯透之刻與 電電第電分部 晶 一控成制由二 電較後 晶：屬蝕； 制極此制部陷 液第·，構控 ·，第制度面 液有金 Κ 層 控電與控一缺 的括片時 ·，膜.，控硬表 的具的阻體 及二則或之案 明包基同極緣極在及之 明係高光導 極第片 極膜圖 發 係性層 電絕電 徵金膜 發片 較成半 電與基 電護局。本 置緣體 二的元 特合層 本 基度形 ·， 制由二制保布者 裝絕導第成像其Α1二 一硬後線 控·，第控及路路 示明半及形之，或洗。 第及面配 訂-----—線HI (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) Α4規格（210Χ297公釐） 8 (修正頁）3900 8 525032 A7 B7 五、發明説明（7 ) 配連 極氣 i 霞 制極 控電 及二 極第 電與 制由 控 ·， ;膜 極緣 電絕 二的 第成 及形 線所 配間 極之 電層 一 體 第導 ·，半 極與 電線 基 一 第 此 與 則 片 基二 第 極 電 元 像 之 。 成料 而材 膜晶 電液 導持 明挾 透時 的同 接片 顯明 晶透 液 ： 該有 , 具 中片 法基 方 一 造第 製該 一 ， 再片 之基 置 二 裝第 示與 顯片 晶基 液一 的第 明括 發包 本置 裝 示 片 基 性 緣 絕 半及 與線 ; 配 層極 體電 導一 半第 線極 配電 極 一 電第 制之 控件 及元 極體 電導 制半 控成 ; 構 同 共 層 體 導 成之 形成 所而 間膜 層電 體導 導明 半透 與的 線接 配連 極氣 S 鬣 制極 控電 及 二 極第 電與 制 由 控及 極膜 電 緣 二 絕 第的 ·, 極 料電 材一 晶 第 液及 持極 挟電 同 二 共第 片 、 基極 一 電 第一 此第 與括 則包 Η 法 基方 二造 第製 , 該 極在 電徵 元特 像其 度之 硬膜 成屬 形金 上的。 膜高者 層較成 多度形 之硬而 金洗驟 合清步 Α1子之 或刷膜 Α1用層 為與多 層 ·，刻 面驟蝕 表步、 在之阻 : 膜光 由屬成 藉金形 係的後 線高面 配較表 液 的 明 發 本 n^i. I - ml - -1^- (I νϋϋ —^ϋ ml n (請先閱讀背面之注意事項再填寫本頁) 訂 經濟部智慧財產局員工消費合作社印製 有層 具體 係導 片半 基 ·’ 一 線 第配 第片 括基 包性 置緣 裝絕 示明 顯透 晶 ： 金 合 IX A 或 li A 由 於 該極硬 , 電 成 片制形 基控上 二及膜 第極層 及電多 片制的 基控成 一 ; 而 面半 表成 之構 膜同 屬共 金層 的體 高導 較半 度與 0 ; 此成 洗形 清所 子膜 刷層 用多 , 刻 後蝕 屬 Μ 金阻 的光 高 成 較形 度後 極 電1 第 極 電1 第 之 件 元 撞 導 之 層 體 導 半 與 線 配 極 電 制 控 及 極 ΙΓΤΤ 貿 dM 制及 控 ·， ; 膜 極緣 電絕 二 的 第成 及形 線所 配間 二 第 極 DpQT 元 。 像者 之片 成料 而材 膜 晶 電液 導持 明挟 透時 的同 接 Η 連基 氣一 電 第 極此 電與 二 則 第片 與基 本紙張尺度適用中國國家標準（CNS ) Α4規格（210X297公釐） 9 (修正頁）39008 線一 525032 A7 B7 五、發明説明（8 ) in.— - i I n I —i— fm fMMmt (請先閲讀背面之注意事項再填寫本頁) 本發明的液晶顯示裝置之製造方法中·其中硬度較高 的金屬係指具有由刷子清洗時不致於上逑金靥之表面上生 成傷痕等的硬度之金靥。 發明之奮餱態樣 管）fe態樣1 “線： 經濟部智慧財產局員工消費合作社印製 Μ下Μ圖面為準說明載置有本發明之一實施態樣的薄 膜電晶體（TFT)之液晶顯示裝置之製造方法。第1圖係表示 載置有本發明之實施態樣1的通道蝕刻型之TFT的液晶顯示 裝置之TFT陣列基片的製造步驟之截面圖。圖中，1為玻璃 基ϋ等透明絕緣性基ϋ、2為具有於透明絕緣性基片1上形 成的控制電極（本實施態樣為閘電極）之控制電極配線（本 實施態樣為閘配線）、3為與閘配線同時形成於透明絕緣性 基片1上的共同配線、4為於閘配線2及共同配線3上形成的 遮罩層、5為於光罩層4上形成的絕緣膜（本實施態樣為閘 絕緣膜）、6為介由閘絕緣膜5而於閘配線2上形成的半導體 層、7為於半導體層6上形成的歐姆式接觸層、8為像元電 極、9為金屬膜、10、11為具有藉由將金屬膜作成電路布 局圖案而於歐姆式接觸層7上形成的第一電極配線（本實施 態樣為源配線）之第一電極與第二電極（本實施態樣為源電 極及汲電極）、12為保護膜。 其次，說明由本實施態樣之液晶顯示裝置的TFT陣列 基片之製造方法。首先•如第1圖（a)所示般，於透明絕緣 性基片1之表面上利用濺鍍法等將含有Cii 0.2原子％的八1 10 (修正頁）39008 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 525032 A7 B7 五、發明説明（9 ) (以下記載成A 1 - 0 . 2 a t % C u )類比電阻值較小的金屬成膜約 200nm後，藉由照相製販法形成光阻，採用以磷酸、醋酸 及硝酸為主成分之蝕刻液進行電路布局圖案蝕刻，在形成 具有閘電極之閘配線2及共同配線3後去除光阻。此時，A1 -0.2at%Cu膜之蝕刻條採用以磷酸、醋酸及硝酸為主成分 之蝕刻液，惟經事先檢討磷酸、醋酸及硝酸之組成，藉由 將Al-0.2at%Cu膜之蝕刻端面形成傾斜形狀，可提高上層 上所形成的膜之被覆性。 其次，如第1圖（b)所示般，例如藉由濺鍍法形成Ο膜 約2 0 0 n in厚，用刷子清洗其表面後，塗布光阻，使光阻作 成電路布局圖案後成為閛配線2及共同配線3等之A1-0.2 at%Cu膜而成的電路布局圖案所被覆的形狀後，蝕刻去除 正露出的Cr膜，以形成光罩層4 。其後，去除光阻，於例 如以磷酸、醋酸及硝酸為主成分之蝕刻液内，浸漬必要的 時間至使200nm左右的A卜0.2at%Cu膜能受蝕刻，去除A1-0.2at % Cii膜而得的電路布局圖案間之短路部等的蝕刻殘 渣。 經濟部中央標準局員工消費合作社印製 在此，用第2圖及第3圖說明於蘭配線2等之配線上生 成的短路缺陷部欲予去除的過程。於閛配線或源配線等之 配線13間生成短路缺陷部14的情形（第2圖U)),首先如第 2圖（b)所示般，以被覆配線13之形狀形成遮罩靥4 ,其次 藉由將已形成遮單層4之基Η浸漬於可蝕刻配線1 3之蝕刻 液内，如第3圖所示般，蝕刻去除未為遮罩層4所被覆的短 路缺陷部14。 本紙張尺度適用中國國家標準（CNS ) Λ4規格（2!G .x :97彡f :) 3 9 0 0 8 (請先閱讀背面之注意事項再填寫本頁) 11 525032 A7 B7 五、發明説明（10 ) 且，遮罩層4,如第4圖所示般，作成僅於鄰近容易生 成短路缺陷之配線13電路布局圖案的部分具有開口部15之 形狀亦可。 其次，如第1圖（c)所示般，藉由霄漿CVD法等，依 予形成成為閘絶緣膜5之矽氮化膜約500nm ,非晶矽膜約 2 00nm,摻雜的，型非晶矽膜約50nm後，採用由照相製版 法而形成的光阻，同時將非晶矽膜及η +型非晶矽膜作成電 路布局圖案，於閜配線2之上方的位置上形成半導體層6及 歐姆式接觸層7。其次，如第1圖（d)所示般，利用濺鍍法 等形成透明導電膜ΙΤ0約100nm後，採用由照相製販法形成 的光阻作成電路布局圖案，形成像元電極8。 其次，如第1圖（e)所示般，由連缠於最下靥上形成構 成與歐姆式接觸層7之n +型非晶矽膜具有歐姆式接觸性良 好的Cr或Ti等高熔點金屬約lOOnm ,於中間層上形成比電 阻值較小的A卜0.2at%Cu等約300nm ,於最上層上形成硬 經濟部中夬標隼局員工消費合作社印製 高較高且可用刷子淸洗的維氏硬度130之Cr約50nm膜，形 成由此三靥膜而成之金屬膜9後，進行刷子清洗。其次， 如第1圖（f)所示般，採用由照相製販法所形成的蝕刻光阻 ,將金屬膜9作成電路布局圖案，形成源配線，及於歐姆 式接觸層7上分離成二之源電極10及汲霄極11。其次，利 用乾蝕刻法蝕刻源電極10及汲電極11欲予去除的部分之 η +型非晶矽膜（歐姆式接觸層9)形成通遒部後，去除光阻 。最後，如第1圖（g)所示般，形成氮化矽膜，於像元電極 8上以外的部分形成保護膜12。 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） 3 9 0 0 8 (請先閲讀背面之注意事項再填寫本頁) 12 525032 A7 B7 五、發明説明（η ) 使於如此形成的第一基片之TFT陣列基Η與其他透明 絶綠性基片上形成有遮光層，上塗層及對向電極之第二基 Η的對向基片之表面上形成定向膜並使對向，於其間植入 液晶以密封劑封入，同時藉由在對向的陣列基片及對向基 Η之外側上配置偏光板而構成液晶嵌板。 且，採用Α卜0.2at%Cu膜作為閘配線2之材料，惟若 為比電阻值小且不生成由水引起的腐蝕及小凸起之膜時， 採用A1膜或其他組成之A1合金膜（含有A190at%)亦可。 又，採用Cr膜作為遮罩層4 ,而若非為對A1合金膜之 蝕刻液所侵蝕時，亦可採用W膜等其他金屬膜。又，作為 蝕刻由A1合金膜引起的蝕刻殘渣之方法，亦可採用乾蝕法 以取代濕蝕刻法。 採用以上步驟製造液晶顯示裝置時，於採用A1条金屬 膜於閘配線2之情形經常發生的配線間之短路缺陷並未被 發現，又，即使在源配線方面，藉由進行刷子清洗可減少 電路布局圖案之缺陷。 經濟部中央標準局員工消費合作社印製 (請先閱讀背面之注意事項再填寫本頁) 若依本發明，為使信號配線成低霄阻化，卽使於採用 具有A1膜或A1合金膜而成之單層膜，或表面層上具有A1条 金屬膜之多層膜構成配線13(蘭配線2)的情形，藉由光罩 層4等被覆配線13可確實的蝕刻去除配線13間之短路缺陷 部14,或於配線13(源配線）之表面層上形成硬度較高的金 屬層並在刷子清洗後形成光阻，作成電路布局圖案，可防 止配線1 3間之短路，同時鞴由採用比電阻值較小的材料構 成信號配線，可使其電路布局圖案細線化，以高良品率製 本紙張尺度適用中國國家標準（CNS ) Λ4規格（210X 297公釐） ι 3 3 9 0 0 8 525032 A7 B7 五、發明説明（12 ) 造由高開口率化之低消耗電功的液晶顯示裝置。 奮_態樣2 第5圖傺表示載置有本發明之實施態樣2的通道保護膜 型之TFT的液晶顯示装置之TFT陣列基片的製造步驟之截面 圖。圖中，16為金颶膜、17為供形成金颶膜16用之光阻電 路布局圖案、18為通道保護膜、19為半導體層。且就與第 1圖相同部分附上相同圖號，而省略說明。 其次，說明本實施態樣之液晶顯示裝置的TFT陣列基 Η之製造方法，首先，如第5圖（a)所示般，於透明絶綈性 基板1之表面上藉由濺鍍法形成Al-0.2at%Cu類之比電阻 值較小的金屬膜約2 0 0 η ία厚後，利用照相製版法形成光阻 ,採用以磷酸、醋酸及硝酸為主成分之蝕刻液進行電路布 局圖案蝕刻、形成具有閙電極之閘配線2及共同配線3後去 除光阻。此時蝕刻Al-0.2at%Cii膜時採用以磷酸、醋酸及 硝酸為主成分之蝕刻液，惟經事先檢討磷酸、醋酸及硝酸 之組成，藉由將A卜0.2at%Cu膜之蝕刻端面形成傾斜形狀 ,可提高上層所形成的膜之被覆性。 經濟部中央標準局員工消費合作社印製 其次，如第5圖（b)所示般，例如藉由濺鍍法形成Cr膜 約200ηπι厚，用刷子清洗其表面後，塗布光阻，形成光阻 電路布局圖案17後成閘配線2及共同配線3等之Al-0.2at% Cu膜而成的電路布局圖案所被覆的形狀後，蝕刻去除正露 出的Cr膜，以形成由Cr膜等之金屬膜16及光阻電路布局圖 案1 7而成的遮罩層4 。其後，於例如以磷酸、醋酸及硝酸 為主成分之蝕刻液内，浸漬必要的時間至使2 0 0 n m左右的 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） 3 9 0 0 8 (請先閲讀背面之注意事項再填寫本頁) 14 經濟部中央標隼局員工消費合作社印製 525032 A7 B7 五、發明説明（13 ) A卜0.2at%Cu膜能受蝕刻，去除A卜0.2at%Cu膜而得的電 路布局圖案間之短路部等的蝕刻殘渣後，去除已構成遮罩 層4之光阻霄路布局圖案17。 其次，如第5圖（c)所示般，藉由電漿CVD法等，依 序形成成為閘絶緣膜5之矽氮化膜約500nm 、非晶矽膜約 ΙΟΟηη、通道保護膜18約2 5 0 nm後，採用由照相製版法而形 成的光阻，同時將非晶矽膜及η +型非晶矽膜作成電路布局 圖案，於閛配線2之上方的位置上形成通道保護膜18。其 次，將磷離子以例如加速電壓2 0 K e V植入非晶矽膜内，形 成η +型非晶矽層。其次，如第5圖（d )所示般，將非晶矽膜 及由植入磷離子而形成的n +型非晶矽層作成電路布局圖案 ，於表面上形成具有歐姆式接觸層之半導體靥19。其次， 如第5圖（e)所示般，利用濺鍍法等形成透明導電膜IT0約 lOOnn後，採用由照相製販法形成的光阻作成電路布局圖 案，形成像元電極8。 其次，如第5圖（f)所示般，由連缅於最下層上形成與 半導體層1 9間之歐姆式接觸性良好的C r或T i等約1 0 0 n id , 於中間層上形成比電阻值較小的A 1 - 0 . 2 a t % C u約3 0 0 n m , 於最上層上形成硬度較高且可用刷子清洗的Cr約50nin膜， 形成由此三層膜而成之金屬膜9後，進行刷子清洗。其次 ，如第5圖（g)所示般，採用由照相製販法所形成的蝕刻光 阻，將金屬膜9作成電路布局圖案，形成第一電極配線（本 實施態樣為源配線）及於半導體層19上分離成二之第一電 極及第二電極（本實施態樣為源霄極10及汲電極11)。其次 本紙張尺度適用中國國家標窣（CNS ) A4規格（210X 297公釐） 15 3 9 0 0 8 (請先閱讀背面之注意事項再填寫本頁) 訂 d 525032 A7 B7 經濟部中央樣隼局員工消費合作社印製 五、發明説明（14 ) » 利 用 乾 蝕 法 蝕 刻 源 電 極 10及 汲 電 極 11 欲 予 去 除 的 部 分 上 所 生 成 的 矽 化 鉻 層 及 Π + 型 非 晶 矽 層 後 9 去 除 光 阻 0 最 後 如 第 5 圖（h) 所 示 般 參 形 成 氮 化 矽 膜 9 於 像 元 電 極 8 上 以 外 的 部 分 形 成 保 護 膜 12 0 使 於 如 此 形 成 的 第 一 基 片 之 TFT 陣 列 基 片 與 其 他 透 明 絶 線 性 基 片 上 形 成 有 遮 光 層 上 塗 層 及 對 向 電 極 之 第 二 基 Η 的 對 向 基 片 之 表 面 上 形 成 定 向 膜 並 使 對 向 f 於 其 間 植 入 液 晶 以 密 封 劑 封 入 1 同 時 藉 由 在 對 向 的 陣 列 基 片 及 對 向 基 Η 之 外 側 上 配 置 偏 光 板 而 構 成 液 晶 嵌 板 0 且 9 採 用 A 1 -0 .2 at % C υ 膜 作 為 閘 配 線 2 之 材 料 9 惟 若 為 bb 霄 阻 值 小 且 不 生 成 由 水 引 起 的 腐 蝕 及 小 凸 起 之 膜 時 V 採 用 A 1 膜 或 其 他 組 成 之 A 1 合 金 膜 亦 可 0 又 1 採 用 Cr 膜 作 為 金 颶 膜 16 9 而 若 非 為 對 A 1 合 金 膜 之 蝕 刻 液 所 侵 蝕 時 9 亦 可 採 用 W 膜 等 其 他 金 屬 膜 0 又 9 作 為 蝕 刻 由 A 1 合 金 膜 引 起 的 蝕 刻 殘 渣 之 方 法 費 亦 可 採 用 乾 蝕 法 以 取 代 濕 蝕 刻 法 0 若 依 本 實 施 態 樣 t 於 載 置 有 通 道 保 護 膜 型 之 TFT 的 液 晶 顯 示 裝 置 可 得 與 實 施 態 樣 1 相 同 的 功 效 9 同 時 藉 由 遮 軍 層 4被覆閘配線2等 之 配 線 部 以 去 除 配 線 間 之 短 路 部 等 的 缺 陷 部 之 際 9 藉 由 將 遮 罩 層 4 作 成 使 Cr ‘膜 等 之 金 屬 膜 16 丨及 金 屬 膜 Η i成 電 路 布 局 圖 案 而 用 的 光 阻 電 路 布 局 圖 案 17 ，之 二 層 構 造 1 可 防 止 金 屬 層 16之 因 被 覆 不 良 引 起 的 配 線 之 腐 蝕 9 又 可 使 構 成 光 罩 層 4之金驅膜】 .6予以薄膜化c ) 育 m 態 樣 3 訂 I 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） 16 3 9 0 0 8 請 先 閱 讀 背 Sj 之 注 意 事 項 再 填 寫 本 頁 # 525032 A7 B7 五、發明説明（15 ) 實施態樣2像就於通道保護膜型之TFT,將閘配線2等 之配線部在蝕刻時的光罩靥4作成金屬膜16及光阻電路布 局圖案17之二層構造的情形予以説明，惟於通道蝕刻型之 TFT ,即使將閘配線等之配線部的蝕刻時之光罩層作成金 鼷膜及光阻電路布局圖案之二層構造時，亦可得與實施態 樣2相同的功效。 奮施熊樣4 第6圖及第7圖僳表示載置有本發明之實施態樣4的平 坦型之TFT的液晶顯示裝置之TFT陣列基片的製造步驟之截 面圖。圖中，20為非晶矽膜、21為通道、22為閘配線、23 為閘電極、2 4為源、汲領域、2 5為絶緣膜、2 6為接觸孔， 且與第5圖相同部分則附上相同圖號並省略說明。 經濟部中央橾準局員工消費合作社印製 其次，說明本實施態樣之液晶顯示裝置的TFT陣列基 Η之製造方法。首先如第6圖（a)所示般，藉由電漿CVD法 等於透明絶緣性基片1之表面上形成非晶矽膜20約ΙΟΟηιπ厚 。其次，如第6圖（b)所示般，照射雷射束使非晶矽膜20成 結晶化而得多晶矽。此時，雷射偽將例如脈衝寬幅1 5〜5 0 ns 之 ArF 或 XeCl激元雷射（excimer User)以 100 〜300mJ/ cm2強度照射。其後，採用由照相製販法形成的光阻作成 電路布局圖案，以形成通道21。其次，如第6圖（c)所示般 ，藉由使氧化矽或氮化矽或電漿之CVD法，當壓CVD法或濺 鍍法形成約200nr»厚膜，形成閘絶緣膜。 其次，如第6圖（d)所示般，错由濺鍍法形成A卜0.2at % C u類比電阻值較小的金驅膜約2 0 0 n m厚後，利用照相製 本紙張尺度適用中國國家標準（CNS ) A4規格（210X29?公釐） 3 9 0 0 8 (請先閱讀背面之注意事項再填寫本頁) 17 525032 A7 B7 五、發明説明（16 ) 販法形成光阻，採用以磷酸、醋酸及硝酸為主成分之蝕刻 液進行電路布局圖案蝕刻，在形成閘配線22後去除光阻。 此時蝕刻Al-0.2at%Cii膜時採用以磷酸、醋酸及硝酸為主 成分之蝕刻液，惟經事先檢討磷酸、醋酸及硝酸之組成， 藉由將Al-0.2at%Cu膜之蝕刻端面形成傾斜形狀，可提高 上層所形成的膜之被覆性。 其次，如第6圖（e)所示般，例如藉由濺鍍法形成Cr膜 約200nm厚，用刷子清洗其表面後，塗布光阻，被覆構成 閘配線22之Al-0.2at%Cii膜，同時在於通道21之上方形成 為形成由Cr膜而成的閘電極23而用的光阻電路布局圖案17 後，蝕刻去除正露出的〇膜，形成由Cr膜等之金屬膜16及 光阻電路布局圖案17而成之遮罩靥4及閘電極23。其後於 例如以磷酸、醋酸及硝酸為主成分之蝕刻液内，浸漬必要 的時間至使200nm左右的A卜0.2at%Cu膜能受蝕刻，去除 A卜0.2at% Cu膜而得的電路布局圖案間之短路部等的蝕刻 殘渣。 經濟部中央標準局員工消費合作社印製 其次，如第6圖（f)所示般，於去除光阻電路布局圖案 17之前，以例如加速電壓70KeV全面植入磷離子，於通道 21上形成成為源、汲領域24之η型半導體，在此，蝕刻構 成閘電極23之金屬膜16時，藉由設置2/im左右之邊蝕（ side etch),磷離子未予檀入光阻電路布局圖案17之下方 的通道21内，可形成偏置型電晶體，可減少失調電流。其 次，《由ECR霄漿CVD法等方式，在氫電漿中，使氫擴散 於多晶矽及閙絶線膜5中，使氫氣鍵結至未鍵結位置。其 本紙張尺度適用中國國家標準（CNS ) A4規格（210公釐 3 9 0 0 8 (請先閱讀背面之注意事項再填寫本頁) 18 525032 A 7 B7 五、發明説明（17 ) 次，如第6圖（g)所示般，藉由使氣化矽或氮化矽成電漿之 CVD法，常壓CVD法或濺鍍法予以成膜，形成絶緣膜25。其 後，在例如3501C退火，使構成源、汲領域24之非晶矽膜 活性化。其次，如第7圖（a)所示般，利用濺鍍法等形成透 明導電膜IT0約lOOnm後，採用由照相製販法形成的光阻作 成電路布局圖案，形成像元電極8。其次，如第7圖（b)所 示般，於源、汲領域24上之絶線膜25上形成接觸孔26。 其次，如第7圖（c)所示般，由連缅於最下層上形成與 源、汲領域24之η型半導體具有歐姆式接觸性良好的Cr或 T i等膜約1 0 0 n m ,於中間層上形成比電阻值較小的A 1 - 0 . 2 at%Cu等約300nm ,於最上層上形成硬度較高且可用刷子 經濟部中央標隼局負工消費合作社印^ (請先閲讀背面之注意亨項再填寫本頁) 清洗的Cr約50ηπι膜，形成三層膜後並用刷子清洗。其次， 採用由照相製販法所形成的蝕刻光阻使三層膜作成電路布 局圖案，介由第一電極配線（本實施態樣為源配線）及接觸 孔2 6 ,以形成與源、汲領域2 4霉氣連接的第一電極及第二 電極（本實施態樣為源電極10及汲電極11)。最後，如第 7圖（d)所示般，形成氮化矽膜，於像元電極8上以外的部 分形成保護膜1 2。 使於如此形成的第一基Η之TFT陣列基Η與其他透明 絶綠性基片上形成有遮光層、上塗層及對向電極之第二基 Η的對向基Η之表面上形成定向膜並使對向，於其間植入 液晶以密封劑封入，同時籍由在對向的陣列基片及對向基 Η之外側上配置偏光板而構成液晶嵌板。 且，採用Α卜0 . 2 a t % C u .模作為閘配線2之材料，惟若 本紙張尺度適用中國國家標準（CNS ) A4規格（210λ一’97公f 19 3 9 0 0 8 525032 A7 B7 五、發明説明（18 為比電阻值小且不生成由水引起的腐蝕及小凸起之膜時， 之 膜 金 合 I* A 對 為 非 〇 若 可而 亦， 膜 4 金層 合 罩 A1遮 之為 成作 組 他 其用 或採 膜， A1又 用 採 膜 Γ 為法 作蝕 , 乾 又用 〇 採 膜可 屬亦 金 ， 他法 其方 等之 膜渣 W 殘 用刻 採蝕 可的 亦起 , 弓 時膜 蝕金 侵 合 所A1 液由 刻刻 蝕蝕 4AKMK C 態 態 法施施 刻實實 蝕本與5 濕依得樣 代 若可萌 取 ，施 以 置奮 型 坦 平 有 置 載 在 裝 示 顯 晶 液 之 效 功 的 同 相 樣 態 施 實 之 明 發 本 有 置 載 示 表 偽 (請先閱讀背面之注意事項再填寫本頁) 晶 2 號 液 ，圖 之中同 T 圖相 TF。上 的画附 ί 面則 截分 的部 驟同 步相 造圖 製 5 之第 片與 基且 列 〇 陣線 Τ 配 TF用 i 的量 圖 8Γ置容 第裝肋 示輔 顯為 的 置 裝 示 顯 晶 液 之 樣 態 施 實 本 明 〇 說 明 · 說次 略其 省 並After the Indium Tin Oxide) film is used, a circuit layout pattern is formed using a photoresist formed by a photoresist method to form a pixel electrode 8. Next, a source electrode 10 and a drain electrode 11 are formed on the ohmic connection layer 7. Therefore, the source 10 and the drain 11 傺 have a film made of a barrier metal such as Cr or Ti on the lower layer in order to improve the ohmic contact characteristics with the n + -type amorphous silicon film. A two-layer film structure composed of a film made of A1 or A1 alloy having a small resistance value. By using a photoresist developing solution for forming an AI film to form a circuit layout pattern, the A1 film is dissolved in the developing solution, and the ITO film of the pixel electrode 8 composed of the A1 film and the substrate causes a battery reaction in the developing solution. Therefore, in order to prevent the IT0 film from being corroded, W may be added as the A1 alloy. Finally, as shown in FIG. 17 (d), a silicon nitride film is formed to form the protective film 12. The protection for the invention is as above. In the conventional TFT-type liquid crystal display device, in order to reduce the consumption (please read the precautions on the back before filling this page). Layers of gold or washing cycle, outside, single-resistance and strong strips to clear the eclipse, Cr, and the dust sprayed by A1, such as the shape of electricity, the water droplets and non-M alloys are made into pure brushes. The combination of the membrane and the A1 line is formed by using dust, and it is matched with A1 to be borrowed. Gold is a type or membrane. Jinxin The film is now softer and the dust A1 is lower than A1. The resistance factor is to use the film in the trace light, but the surface parts containing the film are damaged by the hurricane, and the film is good or the hurricane is used in the gold hurricane. In addition, the gold and gold can be removed to cover the film. A1 The case can be completely hidden »The high loading AI is shown above, and the road gold is shown on the display. The surface can be shortened to a short degree. The laminar surface can be washed and formed into a hard crystal surface. And the liquid meter in the electric line fruit light, ΜΟ is equal to the line, into the knot or film work or timing wave. Keeping Ta Jindian, No. washing film sound industry, residual and consumable film Xinqing hurricane as the surrounding area, and Ti's paper size is applicable to China National Standard (CNS) A4 (2 丨 0X297 public delay) 4 3 9 0 0 8 525032 A7 B7 V. Description of the invention (4) The photoresistor circuit layout pattern to be removed after the defective part is etched. Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs and the Consumer Cooperatives on the production of fluids and wires. Controlled, formed, and electricity should be: *, distribution and basic steps. The material is made into a polar system, a layered polar film, a shape of an electric cover, a step-shaped material, and a specific shape of the electric body in the electric control system. The produced and sample guide is guided by: The semi-second half of the semi-final base of the pole-board control state of the partial board covers the electrical distribution. The foundation method is one-to-one, and the basic method of forming the second line of the second pole line without the mouth pole is coated with a transparent film. The case is controlled by the case that the power is turned on and the power distribution is not connected to the second layer. The picture may have a structured structure and ·, this method is extremely controllable. The membrane board is covered by the square electric power; the electric shield; The base is made of two systems of electric film. This system and the road system are divided into two parts. The first control system is basically in shape. The electrical control department of the electrical control department makes the first edge layer and the unit and power. In one sign, the system is arranged by a system, and the second step of the second electrode is arranged on the material-controlling path and the exposed conductive base of the shield. The connection to the finished electrical film is shown as a one-half system and a pole. The shape of the pole is very short. The structure of the structure is shown in the figure: the shape of the first control is controlled by the electric pole. It is obvious that the crystal structure includes the structure of the material, the material, the material, the material, and the material, and the liquid is covered; The el crystal is made by the wire control layer. Common electrode membrane IX hydraulic control distribution and cover layer layer layer layer electrical BenQ distribution device layer edge (P holding and electrode mask cloth cover selection cover to prevent one pole display edge body two singular element In addition to blocking the road, blocking, blocking, blocking, blocking, blocking, blocking, etc., the image of this electric display is the same as the electric system. -------- IT ----- (Please read the precautions on the back before filling out this page) This paper size applies to China National Standard (CNS) A4 specification (210X297 mm) 6 (correction page) 39008 525032 A7 B7 V. Description of the invention 5. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs; it is matched. It has a significant pole-to-chip control and an on-board structure control. In the film cover step, the common body electric film material system is a system of electricity-elimination of the edge of the end of the sheet, a conductive crystal, the sheet control electrode, the first insulation layer, the base electrical body The semi-conducting semi-conducting fluid, the second and third-generation guide cloths of the Yuan and Electricity · and ·· Zhejiang Road; and the second half of the line with the control and the lack of electricity, the semi-conducting semi-conducting polar line penetration method The control and distribution of the first conductive first film package case, and the electric power distribution when the pole half system and the base map protection diagram adjacent to the slice; the pole one pole is made together, the electric control is controlled by the two parties The Bureau and the Security Bureau have made basic structures covered with electricity. The first fabric is made of wiring and the same structure is made of a gas-based substrate. The film is made of the same material. The edge conducting layer controls the electricity, and the common electrode is the same as the electrode. The electrode is composed of the half-shield and the element and the electrode layer, and the corrosion is in the line; Electricity and basic electric body two elements are adjacent to each other and the wire system is advanced. The penetrator is electrically conductive. The second device is equipped with a second guidance and imaging feature. It is equipped with a control step. Other steps Or the same display has extremely engraved control and basic display, and between the line, with the step of the electrode film suddenly shows the structure of the electric contact, two wafers, with the electrode of the protective step crystal The system, the same ..., the liquid-liquid base electrode layer of the membrane, the electrode layer of the liquid film control shape, the common electrode edge, the monolithic electro-electric crystal manufacturing part, and the base and shape of the control film The layer of the electric pole is connected to the first edge, the liquid is controlled, and the electric body that is polarized to the edge of the membrane is directly connected to the electric body. Ming ;, with the transparent electrode film system to eliminate the half of the polar match and the image installed through the sub-electrode line of the same electrical protection control. Above, the electrode part and the line between the terminal electrical connection co-production protection (Read the notes on the back before filling out this page) This paper size applies to Chinese National Standard (CNS) A4 (210X297 mm) 7 (correction page) 39008 525032 A7 B7 V. Description of the invention ( 6 The first electrode, the first electrode wiring, and the second electrode constituting the semiconductor element are printed by the consumer cooperative of employees of the Intellectual Property Bureau of the Ministry of Economic Affairs. The material made by the wire A1 is the crystal of the gold watch pole that is removed from the edge: ·, The combination is formed by the material, and the electric power is cut off. The wire liquid has a layered film. The element in the film A1 film is equipped with the specific electric layer electro-hydraulic sequence and the base or layer control is imaged in between. The chip guide is integrated with the second one and the element is in the form of the second element. Semi-guided 挟: ·, step-by-step into the material of this polar body, the method of making the film is half transparent, and the material is controlled by the step-by-step, and the material is controlled by the common line. The oblique half of the film crystal cloth or the layer of the power distribution line system is controlled by layers to form a layer of electro-hydraulic circuit and pole system, one pole is connected to the baseline film two one, and the brushed structure guides the electric film to one piece of electricity. The first layer of the polar gas and the first layer is used to form the second electrode of the electricity and electricity, which is the same as that of the semiconductor device. The second electrode is the base of the second electrode. The same layer as the first stop, the first control and the control resistance edge film membrane body wire connection line corrosion prevention equipment and polar body and two gold control equipment insulation layer guide After the first and second electrodes of the kappa chip show the two and a half halves of the gas and the first pole, the moment of the semi-basic system and the high shape of the base are transparent and the crystal of the first branch of the electricity department is controlled by the second electricity. Later crystals: belong to the eclipse; the system's traps are controlled by the system, the structure is controlled, the system liquid has gold κ layer control power and control, and the lack of brackets, film., Control of the hard watch The resistor body and the two OR cases show that the same base electrode is in contact with the polar electrode of the high-light-conducting electrode. The system is a layer of electrical insulation and the gold film is more semi-electrical and basic electrical protection. The basic shape of the element special layer of the marginal body II is made by the second system clother, and the A1 21 is hard-wired. The control and the road show that it is half-shaped. Or wash. The first and the second side of the binding ------line HI (Please read the precautions on the back before filling in this page) This paper size applies the Chinese National Standard (CNS) Α4 specifications (210 × 297 mm) 8 (correction page) 3900 8 525032 A7 B7 V. Description of the invention (7) Equipped with pole gas i Xia system pole control and two pole first control and control by ;; membrane electrode edge second and third line of the electrode The layer is integrated, the half-pole and the wire base are the first and the base are the second and second poles. When the material is formed and the material film crystal electro-hydraulic guide is bright and transparent, the same connecting piece shows the crystal transparent liquid: there is, the middle piece method is used to create the first one, and the second piece is placed to install the second display and display. The basic package of the chip crystal base liquid 1 is installed to display the semi-finished edge of the film and the wire; the layered electrode body conducts half the wire electrode and the electrode electrode system controls and the element electrode body conductivity control system ; The formation of the formation of the co-layer body and the electric conduction of the interstitial layer reveals the semi-transparent line connected with the pole gas S and the pole and the pole and the pole and the pole and the membrane edge Second, the first material, the first material of the electrode material and the second electrode of the same electrode, the first electrode of the base and the first rule, including the basic law of the second system, the electrode is in the electric levy Yuan special like its degree of dura mater formed on gold. The film height layer is more multi-layered, and the gold wash step is combined with the clear step A1, or the brush film A1 is used with multiple layers. The facet abruptly etches the surface steps. The resistance is: the film light is made of gold. The shape of the rear line of the high line with the surface liquid n ^ i. I-ml--1 ^-(I νϋϋ — ^ ϋ ml n (Please read the precautions on the back before filling this page) Order economy The Ministry of Intellectual Property Bureau ’s Consumer Cooperative has printed a layered specific system guide half-base. “The first line of the first line includes the base package. The inclusive edge mounting device is absolutely transparent. Acacia IX A or li A. Because of this extremely hard, electrical The first two layers of the film control and the first electrode layer of the film and the basic control of the multi-chip system are one; and the surface semi-formed film belongs to the same gold layer with a body conductivity of half a degree and 0; this shape is washed. There are many brush layers used in the Qingsuo sub-membrane. After the etching, the light intensity of the M metal resistance is relatively high. After the electrode is first, the first electrode is the first element, and the layer guide and the line electrode are controlled. The pole IΓΤΤ trades dM system and controls,; The second pole DpQT element of the second formation and the shape line of the membrane pole edge electric second. The film of the person who made the material and the material film crystal electro-hydraulic conductive connection is transparent and transparent. The base electrode, the first electrode, the second electrode, and the basic paper size are subject to the Chinese National Standard (CNS) Α4 specification ( 210X297 mm) 9 (Revised page) 39008 Line one 525032 A7 B7 V. Description of the invention (8) in. —-I I n I — i — fm fMMmt (Please read the notes on the back before filling this page) The present invention In the method of manufacturing a liquid crystal display device, a metal having a higher hardness refers to a metal having a hardness that does not cause scratches or the like on the surface of the upper surface of the metal surface when being cleaned by a brush. The state of the invention (the sample tube of the invention) fe state Sample 1 "Line: printed by the consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, the lower M figure is for illustration of a method for manufacturing a liquid crystal display device on which a thin film transistor (TFT) according to one embodiment of the present invention is mounted. The figure is a cross-sectional view showing the manufacturing steps of a TFT array substrate of a liquid crystal display device in which a channel-etched TFT of Embodiment 1 of the present invention is mounted. In the figure, 1 is a transparent insulating substrate such as glass substrate, 2 is a transparent insulating substrate Control electrode wiring (gate wiring in this embodiment) formed on the control electrode (gate wiring in this embodiment), 3 is a common wiring formed on the transparent insulating substrate 1 at the same time as the gate wiring, and 4 is A masking layer formed on the gate wiring 2 and the common wiring 3, 5 is an insulating film (a gate insulating film in this embodiment) formed on the photomask layer 4, and 6 is a gate wiring via the gate insulating film 5. The semiconductor layer formed on 2; 7 is an ohmic contact layer formed on semiconductor layer 6; 8 is a pixel electrode; 9 is a metal film; 10 and 11 are ohmic-type by forming a metal film into a circuit layout pattern; The first electrode and the second electrode (the source electrode and the drain electrode in this embodiment) of the first electrode wiring (the source wiring in this embodiment) formed on the contact layer 7, and 12 are protective films. Next, a method for manufacturing a TFT array substrate of a liquid crystal display device according to this embodiment will be described. Firstly, as shown in FIG. 1 (a), the surface of the transparent insulating substrate 1 is sputtered or the like containing Cii 0.2 atomic% 8 1 10 (revised page) 39008. This paper size applies Chinese national standards (CNS) A4 specification (210X297 mm) 525032 A7 B7 V. Description of the invention (9) (hereinafter described as A 1-0.2 at% C u) A metal with a small analog resistance value is formed into a film of about 200 nm. The photoresist method is used to form a photoresist, and an etching solution containing phosphoric acid, acetic acid, and nitric acid as main components is used to etch the circuit layout pattern. After the gate wiring 2 and the common wiring 3 having a gate electrode are formed, the photoresist is removed. At this time, the etching strip of A1 -0.2at% Cu film uses an etching solution mainly composed of phosphoric acid, acetic acid and nitric acid, but after reviewing the composition of phosphoric acid, acetic acid and nitric acid in advance, The etched end face is formed in an inclined shape, which can improve the coverage of the film formed on the upper layer. Next, as shown in FIG. 1 (b), for example, a 0-film is formed by sputtering to a thickness of about 200 n in. After cleaning the surface with a brush, a photoresist is applied to make the photoresist into a circuit layout pattern.形状 After the shape covered by the circuit layout pattern of the A1-0.2 at% Cu film of the wiring 2 and the common wiring 3, etc., the exposed Cr film is removed by etching to form a photomask layer 4. After that, the photoresist is removed, and an etching solution containing phosphoric acid, acetic acid, and nitric acid as the main component is immersed for a time necessary to allow the 200nm Ab 0.2at% Cu film to be etched, and A1-0.2at% Cii is removed. Etching residues such as short-circuited portions between circuit layout patterns obtained from the film. Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs Here, the process of removing short-circuit defects generated on the wiring of the LAN wiring 2 and the like will be described with reference to Figures 2 and 3. In the case where a short-circuit defect portion 14 is generated between wirings 13 such as 閛 wiring or source wiring (Fig. 2 U)), first, as shown in Fig. 2 (b), a mask 靥 4 is formed in the shape of a covered wiring 13. Next, by immersing the substrate on which the masking single layer 4 has been formed in the etching solution of the etchable wiring 13, as shown in FIG. 3, the short-circuit defect portion 14 not covered by the masking layer 4 is removed by etching. This paper size applies the Chinese National Standard (CNS) Λ4 specification (2! G.x: 97 彡 f :) 3 9 0 0 8 (Please read the precautions on the back before filling this page) 11 525032 A7 B7 V. Description of the invention (10) As shown in FIG. 4, the mask layer 4 may have a shape having an opening portion 15 only in a portion of the circuit layout pattern adjacent to the wiring 13 that is prone to short-circuit defects. Next, as shown in FIG. 1 (c), a silicon nitride film to be the gate insulating film 5 is formed approximately 500 nm, an amorphous silicon film is approximately 200 nm, and the doped type is formed by a slurry CVD method or the like. After the amorphous silicon film is about 50 nm, a photoresist formed by a photoengraving method is used. At the same time, the amorphous silicon film and the η + type amorphous silicon film are used to form a circuit layout pattern, and a semiconductor layer is formed on the position above the hafnium wiring 2 6 和 ohmic contact layer 7. Next, as shown in FIG. 1 (d), a transparent conductive film ITO is formed at a thickness of about 100 nm by a sputtering method or the like, and then a circuit layout pattern is formed by using a photoresist formed by a photo process to form a pixel electrode 8. Secondly, as shown in FIG. 1 (e), the n + -type amorphous silicon film formed by entanglement on the lowermost ridge and forming the ohmic contact layer 7 has a high melting point such as Cr or Ti, which has good ohmic contact. The metal is about 100 nm, and the specific resistance value is about 300 nm on the middle layer, such as A 0.2 0.2 %% Cu. On the top layer, the Ministry of Hard Economy, China Standards Bureau, Employee Consumer Cooperative Co., Ltd. prints high and can use brushes. After washing the Cr film having a Vickers hardness of 130 to about 50 nm, a metal film 9 formed of the three-layer film was formed, and then brush-washed. Next, as shown in FIG. 1 (f), an etching photoresist formed by a photographic method is used to form a metal film 9 into a circuit layout pattern, form source wiring, and separate it into two on the ohmic contact layer 7. Source electrode 10 and drain tube 11. Next, dry-etching is used to etch the η + -type amorphous silicon film (ohmic contact layer 9) of the source electrode 10 and the drain electrode 11 to be removed, and then the photoresist is removed. Finally, as shown in FIG. 1 (g), a silicon nitride film is formed, and a protective film 12 is formed on portions other than the pixel electrode 8. This paper size applies Chinese National Standard (CNS) A4 specification (210X 297 mm) 3 9 0 0 8 (Please read the precautions on the back before filling this page) 12 525032 A7 B7 V. Description of invention (η) A light-shielding layer is formed on the TFT array substrate of the first substrate and other transparent green insulating substrates, and an alignment film is formed on the surface of the opposing substrate of the second substrate of the counter electrode and the opposite electrode, and Oriented, a liquid crystal is implanted therebetween and sealed with a sealant. At the same time, a liquid crystal panel is formed by disposing a polarizing plate on the opposite side of the opposing array substrate and the opposing substrate. In addition, a 0.2 at% Cu film is used as the material of the gate wiring 2. However, if the film has a lower specific resistance value and does not generate corrosion and small bumps caused by water, an A1 film or an A1 alloy film of other composition is used. (Contains A190at%). In addition, a Cr film is used as the masking layer 4, and other metal films such as a W film may be used unless it is etched by the etching solution of the A1 alloy film. As a method for etching the etching residue caused by the A1 alloy film, a dry etching method may be used instead of the wet etching method. When the above steps are used to manufacture a liquid crystal display device, short circuit defects between wirings that often occur when A1 metal film is used in the gate wiring 2 are not found. Moreover, even in the source wiring, the circuit can be reduced by brush cleaning. Defects in layout patterns. Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs (please read the precautions on the back before filling this page). According to the present invention, in order to reduce the signal wiring resistance, it is necessary to use A1 film or A1 alloy film. In the case of a single layer film or a multilayer film with A1 metal film on the surface layer to form the wiring 13 (blue wiring 2), the short-circuit defects between the wirings 13 can be reliably removed by covering the wirings 13 such as the photomask layer 4 14 or a metal layer with higher hardness is formed on the surface layer of wiring 13 (source wiring) and a photoresist is formed after brush cleaning to form a circuit layout pattern, which can prevent a short circuit between wirings 1 and 3. The material with a smaller resistance value constitutes the signal wiring, which can make the circuit layout pattern thinner. The paper size is made with high yield. The paper size applies the Chinese National Standard (CNS) Λ4 specification (210X 297 mm) ι 3 3 9 0 0 8 525032 A7 B7 V. Description of the invention (12) A liquid crystal display device with low power consumption and high power consumption. Fen_Aspect 2 Fig. 5 (a) is a cross-sectional view showing a manufacturing step of a TFT array substrate of a liquid crystal display device in which a channel protective film type TFT according to an aspect 2 of the present invention is mounted. In the figure, 16 is a gold hurricane film, 17 is a photoresist circuit layout pattern for forming the gold hurricane film 16, 18 is a channel protection film, and 19 is a semiconductor layer. In addition, the same parts as those in FIG. 1 are attached with the same drawing numbers, and the description is omitted. Next, a method for manufacturing a TFT array substrate of a liquid crystal display device according to this embodiment will be described. First, as shown in FIG. 5 (a), Al is formed on the surface of the transparent insulating substrate 1 by a sputtering method. -0.2at% Cu-based metal film with a small specific resistance value of about 2 0 η ία thick, and then a photoresist is formed by a photoengraving method, and the circuit layout pattern is etched by using an etching solution mainly composed of phosphoric acid, acetic acid, and nitric acid. 2. After forming the gate wiring 2 and the common wiring 3 with a rubidium electrode, the photoresist is removed. At this time, an etching solution containing phosphoric acid, acetic acid, and nitric acid as the main component is used when etching the Al-0.2at% Cii film, but the composition of phosphoric acid, acetic acid, and nitric acid has been reviewed in advance. Forming an inclined shape can improve the covering property of the film formed on the upper layer. Printed by the Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs, as shown in Figure 5 (b). For example, a Cr film is formed by sputtering to a thickness of about 200 ηm. After cleaning the surface with a brush, a photoresist is applied to form a photoresist. After the circuit layout pattern 17 is formed into a shape covered by an Al-0.2at% Cu film of the gate wiring 2 and the common wiring 3, etc., the exposed Cr film is removed by etching to form a metal such as the Cr film. The mask layer 4 is formed by the film 16 and the photoresist circuit layout pattern 17. Thereafter, immersion in an etching solution containing, for example, phosphoric acid, acetic acid, and nitric acid, as necessary, so that the paper size of about 200 nm can be adapted to the Chinese National Standard (CNS) A4 specification (210X 297 mm) 3 9 0 0 8 (Please read the precautions on the back before filling this page) 14 Printed by the Consumers' Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 525032 A7 B7 V. Description of the invention (13) A 0.2at% Cu film can be etched, After removing etching residues such as short-circuited portions between the circuit layout patterns obtained by the 0.2 at% Cu film, the photoresist road layout pattern 17 that has formed the mask layer 4 is removed. Next, as shown in FIG. 5 (c), a silicon nitride film that becomes the gate insulating film 5 is formed by a plasma CVD method, etc., about 500 nm, an amorphous silicon film is about 100 ηη, and a channel protection film 18 is about 2 After 50 nm, a photoresist formed by a photoengraving method is used, and an amorphous silicon film and an η + -type amorphous silicon film are used to form a circuit layout pattern, and a channel protection film 18 is formed on a position above the hafnium wiring 2. Next, phosphorus ions are implanted into the amorphous silicon film at, for example, an acceleration voltage of 20 KeV to form an η + -type amorphous silicon layer. Next, as shown in FIG. 5 (d), an amorphous silicon film and an n + -type amorphous silicon layer formed by implanting phosphorus ions are used as a circuit layout pattern, and a semiconductor having an ohmic contact layer is formed on the surface.靥 19. Next, as shown in FIG. 5 (e), a transparent conductive film IT0 is formed by a sputtering method or the like for about 100 nn, and then a circuit layout pattern is formed by using a photoresist formed by a photographic method to form a pixel electrode 8. Secondly, as shown in FIG. 5 (f), Cr or Ti, which has a good ohmic contact with the semiconductor layer 19, is formed on the lowermost layer by about 10 0 n id in the middle layer. A 1-0. 2 at% Cu with a small specific resistance value is about 300 nm, and a Cr film with a hardness of about 50nin is formed on the uppermost layer and can be cleaned with a brush. This three-layer film is formed. After the metal film 9 is applied, brush cleaning is performed. Next, as shown in FIG. 5 (g), an etching photoresist formed by a photographic method is used to form the metal film 9 into a circuit layout pattern to form a first electrode wiring (source wiring in this embodiment), and A first electrode and a second electrode separated into two on the semiconductor layer 19 (a source electrode 10 and a drain electrode 11 in this embodiment). Secondly, this paper size applies to China National Standard (CNS) A4 (210X 297 mm) 15 3 9 0 0 8 (Please read the notes on the back before filling this page) Order 525032 A7 B7 Central Bureau of Economic Affairs, Ministry of Economic Affairs Printed by the employee consumer cooperative 5. Description of the invention (14) »After the dry etching method is used to etch the source electrode 10 and the drain electrode 11 to be removed, the chromium silicide layer and the Π + type amorphous silicon layer are removed. 9 The photoresist is removed. 0 Finally, as shown in FIG. 5 (h), a silicon nitride film is formed. 9 A protective film is formed on the pixel electrode 8 other than the pixel electrode. 12 0 The TFT array substrate formed on the first substrate thus formed is transparent to other substrates. An alignment film is formed on the surface of the opposing substrate on the insulating substrate with a light-shielding layer coating and a second substrate of the opposing electrode, and the opposing f is implanted with a liquid crystal and sealed with a sealant 1 at the same time. Opposite array substrate and opposite substrate A polarizing plate is arranged on the outer side to form a liquid crystal panel 0 and 9 A 1 -0.2 at 2 C υ film is used as the material of the gate wiring 2 9 However, if the resistance value of bb is small and it does not cause water corrosion and small For raised film V, A 1 film or A 1 alloy film of other composition can also be used. 0 and 1 Cr film is used as gold hurricane film. 16 9 can also be used if it is not eroded by etching solution of A 1 alloy film. W film and other metal films 0 and 9 As a method for etching the etching residue caused by the A 1 alloy film, a dry etching method may be used instead of the wet etching method. 0 According to this embodiment, a channel protection film type is placed The TFT liquid crystal display device can obtain the same effect as in the first embodiment. 9 At the same time, the wiring layer such as the gate wiring 2 is covered by the shielding layer 4 to remove the defective portion such as the short-circuit portion between the wirings. 9 Cover layer 4 is made of Cr The metal film 16 of the film and the metal film Η are used to form the circuit layout pattern of the photoresist circuit layout pattern 17, and the two-layer structure 1 can prevent the corrosion of the wiring caused by the poor coating of the metal layer 16 and the composition Gold flooding film for photomask layer 4] .6 for thin film c) Yum appearance 3 Order I This paper size applies Chinese National Standard (CNS) A4 specification (210X 297 mm) 16 3 9 0 0 8 Please read first Please fill in this page if you need to pay attention to Sj # 525032 A7 B7 V. Description of the invention (15) Implementation mode 2 The TFT is like a channel protection film type, and the wiring parts such as the gate wiring 2 are etched. 4 A case where the two-layer structure of the metal film 16 and the photoresist circuit layout pattern 17 is made will be described. However, in the case of a channel-etched TFT, even if the mask layer is etched when wiring portions such as a gate wiring are etched, a gold film and a photoresist are formed. When the two-layer structure of the circuit layout pattern is obtained, the same effect as that of the second aspect can be obtained. Figures 6 and 7 of Fenshi Bear Sample 4 are sectional views showing manufacturing steps of a TFT array substrate of a liquid crystal display device having a flat TFT according to a fourth embodiment of the present invention. In the figure, 20 is an amorphous silicon film, 21 is a channel, 22 is a gate wiring, 23 is a gate electrode, 24 is a source, a drain region, 25 is an insulating film, and 26 is a contact hole, which are the same as those in FIG. 5 Parts are attached with the same drawing numbers and descriptions are omitted. Printed by the Consumers' Cooperative of the Central Bureau of Standards, Ministry of Economic Affairs Next, the manufacturing method of the TFT array substrate of the liquid crystal display device of this embodiment will be described. First, as shown in FIG. 6 (a), an amorphous silicon film 20 is formed on the surface of the transparent insulating substrate 1 by a plasma CVD method to have a thickness of about 100 nm. Next, as shown in Fig. 6 (b), the laser beam is irradiated to crystallize the amorphous silicon film 20 into polycrystalline silicon. At this time, the laser pseudo-irradiates, for example, an ArF or XeCl excimer laser with a pulse width of 15 to 50 ns at an intensity of 100 to 300 mJ / cm2. Thereafter, a circuit layout pattern is formed using a photoresist formed by a photographic method to form the channel 21. Next, as shown in FIG. 6 (c), a thick film of about 200 nr »is formed by a CVD method of silicon oxide, silicon nitride, or plasma, and a pressure CVD method or a sputtering method to form a gate insulating film. Secondly, as shown in Fig. 6 (d), a gold flooding film with a small 0.2 A% Cu analogue resistance value was formed by sputtering to a thickness of about 200 nm, and the paper was produced using photographic paper. National Standard (CNS) A4 Specification (210X29? Mm) 3 9 0 0 8 (Please read the precautions on the back before filling out this page) 17 525032 A7 B7 V. Description of the Invention (16) The photoresist is formed by the law of trafficking. An etching solution containing phosphoric acid, acetic acid, and nitric acid as main components is used to etch the circuit layout pattern, and the photoresist is removed after the gate wiring 22 is formed. At this time, the etching solution containing phosphoric acid, acetic acid and nitric acid as the main component is used to etch the Al-0.2at% Cii film, but after reviewing the composition of phosphoric acid, acetic acid and nitric acid in advance, the etching end face of the Al-0.2at% Cu film Forming an inclined shape can improve the coverability of the film formed on the upper layer. Next, as shown in FIG. 6 (e), for example, a Cr film is formed to a thickness of about 200 nm by sputtering. After cleaning the surface with a brush, a photoresist is applied to cover the Al-0.2at% Cii film forming the gate wiring 22. At the same time, a photoresist circuit layout pattern 17 for forming a gate electrode 23 made of a Cr film on the square above the channel 21 is etched to remove the exposed 0 film to form a metal film 16 and photoresist made of a Cr film and the like. The mask 靥 4 and the gate electrode 23 formed by the circuit layout pattern 17. Then, in an etching solution containing phosphoric acid, acetic acid, and nitric acid as the main components, the circuit is obtained by immersing for a required time until the 200 nm Ab 0.2at% Cu film can be etched, and the Ab 0.2at% Cu film is removed. Etching residues such as short-circuited portions between layout patterns. Printed by the Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs. As shown in Figure 6 (f), before removing the photoresist circuit layout pattern 17, phosphorus ions are fully implanted at an acceleration voltage of 70 KeV, for example, and formed on the channel 21. The n-type semiconductor in the source and drain regions 24. Here, when the metal film 16 constituting the gate electrode 23 is etched, by setting a side etch of about 2 / im, phosphorus ions are not patterned into the photoresist circuit. A bias transistor can be formed in the channel 21 below 17 to reduce the offset current. Secondly, "The hydrogen plasma is used to diffuse hydrogen into the polycrystalline silicon and dysprosium insulating film 5 by means of the ECR CVD CVD method, so that hydrogen is bonded to the unbonded position. The size of this paper applies the Chinese National Standard (CNS) A4 specification (210 mm 3 9 0 0 8 (please read the precautions on the back before filling in this page) 18 525032 A 7 B7 5. Description of the invention (17) times, such as As shown in FIG. 6 (g), an insulating film 25 is formed by a CVD method, a normal pressure CVD method, or a sputtering method in which a vaporized silicon or silicon nitride is formed into a plasma. Thereafter, for example, at 3501C Annealing activates the amorphous silicon film constituting the source and drain regions 24. Secondly, as shown in FIG. 7 (a), a transparent conductive film IT0 is formed to a thickness of about 100 nm by a sputtering method or the like, and then formed by a photo process. The photoresist is used to form a circuit layout pattern to form the pixel electrode 8. Secondly, as shown in FIG. 7 (b), a contact hole 26 is formed on the insulating film 25 on the source and drain regions 24. Secondly, as shown in FIG. As shown in Fig. (C), a film of Cr or Ti with good ohmic contact is formed on the bottom layer of the n-type semiconductor with a source and drain region of about 100 nm, which is formed on the bottom layer. A 1-0. 2 at% Cu, etc., with a small specific resistance value, is about 300 nm, which forms a higher hardness on the uppermost layer and can be used by the Central Bureau of the Ministry of Economic Affairs. Industrial and consumer cooperative seal ^ (Please read the note on the back and fill in this page first) Clean the Cr film of about 50ηπι, form a three-layer film, and clean it with a brush. Second, use the etching photoresist formed by the photography method to make the three The layer film is used to form a circuit layout pattern, and the first electrode wiring (source wiring in this embodiment) and the contact hole 26 are formed to form a first electrode and a second electrode that are connected to the source and the draining area 24 (in this embodiment) The aspect is the source electrode 10 and the drain electrode 11). Finally, as shown in FIG. 7 (d), a silicon nitride film is formed, and a protective film 12 is formed on the portion other than the pixel electrode 8. This is so formed The first substrate of the TFT array substrate and other transparent green substrates are formed with a light-shielding layer, an overcoat layer, and a second substrate of the opposite electrode on the surface of the opposite substrate to form an alignment film and to face the opposite substrate. A liquid crystal panel is implanted with a liquid crystal to be sealed with a sealant, and a polarizing plate is arranged on the opposite array substrate and the opposite side of the opposite substrate to form a liquid crystal panel. Furthermore, Αb 0.2 at% Cu is used. .The mold is used as the material of the gate wiring 2, but if this paper size is applicable to China Home Standard (CNS) A4 specification (210λ-'97 male f 19 3 9 0 0 8 525032 A7 B7 V. Description of the invention (18 is when the specific resistance value is smaller and no corrosion caused by water and small convex film are generated, The film metallization I * A pair is non-zero. If possible, the film 4 gold lamination cover A1 can be used as a group for other purposes or filming. 〇Membrane mining can also be gold, and other methods of film slag W can be used for residual etching. The A1 solution of the gold-etching film invasion institute is etched and etched. If the real etched version and the 5 wet yide sample can be extracted, apply the Fen-type flat and have the same phase as the effect of the crystal display liquid. Please read the precautions on the back before filling in this page) Crystal No. 2 liquid, the picture is the same as the T picture phase TF. The above picture is attached with the cut-out part of the face, and the phase synchronization is made. The first piece of the picture and the base line 0 are equipped with the amount of i for TF. Figure 8 The state of the crystal liquid is practical and practical. Explanation · Slightly omitted
基 列 BF 1ST 般 " 示-0 所A1 a)成 /IV 形 上 第面 如表 先之 首 1 ο 法 方 造 之 片 圖 8 Η 基 性 綠 絶 明 透 於值 等阻 法電 鍍比 濺 由 0 %Gilead BF 1ST is like " shows -0 A1 a) into / IV form as the first in the table 1 ο made by the French method Figure 8 Η Basic green is absolutely transparent and transparent By 0%
類 U 經濟部中央標準局員工消費合作杜印製 , 局 配 阻布用 光路量 成電容 形行肋 法進輔 版液及 製刻 2 射蝕線 照 用 利成之 , 主 極 後為電 厚酸閜 a 硝有 on及具 30酸成 約醋形 膜 、在 屬酸 ， 金磷刻 的以蝕 小用案 較採圖 刻0 時 此 ο 阻 光 除 去 後 7 2 線 之配at r I 2 分閘 · 酸 磷 以 用 採 時 膜 醋 、 酸0 討 檢 先 I 經 一 液 刻0 之 分 成 主 為 酸 硝 及 酸 醋 每 對 由 膜 《 ? 的偽 ? 成， A1形27 將所線 由層配 緒 上用 , 高 量 成提容 組可肋 之 ，輔 酸狀 ， 硝形又 及斜 酸傾 覆 CU被 % 之 t 成 形 面 端 刻 蝕 之 膜 閜 與 成 作 元 ο 像 性 一 本紙張尺度適用中國國家標孪（CNS ) A4規格（21Gx M7公釐） 20 3 9 0 0 8 525032 A7 B7 五、發明説明（19 ) 配線2短路的構造，形成閛配線2對斷線之繁雜構造。 其次，如第8圖（b)所示般，例如藉由濺鍍法形成Cr膜 約20〇nffl厚用刷子清洗其表面後，塗布光阻，於形成光阻 電路布局圖案17使成能被覆由閘配線2及輔助容量用配線 27等之Al-0.2at%Cu膜而成的電路布局圖案之形狀後，蝕 刻去除正露出的Cr膜，形成由Cr膜等金屬膜16及光阻電路 布局圖案17而成的遮罩層4 。其後於例如以磷酸、醋酸及 硝酸為主成分之蝕刻液内，浸漬必要的時間至使200nm左 右的M-0.2at%Cu膜能受蝕刻，去除Al-0.2at%Cu膜而 得的電路布局圖案間之短路部等的蝕刻殘渣。其次，如第 8圖U)所示般，去除已構成遮罩層4之光阻電路布局圖案 17及金屬膜16。 以後的步驟傺與於賁施態樣1或實施態樣2之CVD法等 而得的閘絶緣膜形成以後之步驟相同，形成通道蝕刻型之 液晶顯示裝置或通道保護膜型之液晶顯示装置。 經濟部中央標隼局員工消費合作社印製 且，採用Al-0.2at%Cu膜作為閜配線2之材料，惟若 為比電阻值小且不生成由水引起的腐蝕及小凸起之膜時， 採用AI膜或其他組成之A1合金膜亦可。 又，採用Cr膜作為遮罩層4 ,而若非為對A1合金膜之 蝕刻液所侵蝕時，亦可採用W膜等其他金屬膜。又，作為 蝕刻由A 1合金膜引起的蝕刻殘渣之方法，亦可採用乾蝕法 以取代濕蝕法。 若依本實施態樣，可得與實施態樣2相同的功效，同 時轉由遮罩層4被覆閛配線2等之配線部以去除配線間之 本紙張尺度適用中國國家標隼（CNS ) A4規格（21GX29?公釐:) 3 9 0 0 8 (請先閲讀背面之注意事項再填寫本頁) 2 1 525032 A7 B7 五、發明説明（2〇 ) 短路部等的缺陷部後，因亦可去除構成遮罩層4之金屬膜 16,可防止由於金屬膜16而發生的短路缺陷。 奮施態樣6 第9圖係表示載置有本發明之實施態樣6的TFT之液晶 顯示裝置的TFT陣列基片之製造步驟的截面圖。圖中之圖 號傺與第8圖者相同，省略說明。 其次，説明本實施態樣之液晶顯示裝置的TFT陣列基 片之製造方法。首先如第9圖（a)所示般，藉由濺鍍法等於 透明絶緣性基H1之表面上形成Al-0.2at%Cu類比電阻值 較小的金颶膜約3 0 0 n m厚後，利用照射製販法形成光阻， 採用以磷酸、醋酸及硝酸為主成分之蝕刻液進行電路布局 圖案蝕刻，在形成具有閘電極之閘配線2及輔肋容量用配 線27後去除光阻。此時蝕刻Al-0.2at%Cu膜時採用以磷酸 、醋酸及硝酸為主成分之蝕刻液，惟經事先檢討磷酸、醋 酸及硝酸之組成，藕由將Al-0.2at% Cu膜之蝕刻端面形成 傾斜形狀，可提高上層所形成的膜之被覆性。 經濟部中央標苹局員工消費合作社印^ (請先閱讀背面之注意事項再填寫本頁) 又，輔肋容置用配線27,偽藉由對每一像元作成與閘 配線2短路的構造，形成閘配線2對斷線之繁雜構造。 其次，如第9圖（b)所示般，塗布光阻，於形成光阻電 路布局圖案17使成能被覆由閘配線2及輔助容量用配線27 等之A卜0.2at%Cu膜而成的電路布局圖案之形狀後，作為 遮罩層4 。其後於例如以磷酸、醋酸及硝酸為主成分之蝕 刻液内，浸漬必要的時間至使2 0 0 n m左右的A卜0 . 2 a t % C u 膜能受蝕刻，去除Al-0.2at%Cii膜而得的電路布局圖案間 本紙張尺度適用中國國家標準（（:>^)入4規格（210'297公缝） 〇 〇 。η Λ λ。 525032 A7 B7 五、發明説明（21 ) 之短路部等的蝕刻殘渣。其次，如第9圖（c)所示般，去除 已構成光罩層4之光阻電路布局圖案17。 以後的步驟僳與於實施態樣1或實施態樣2之CVD法等 而得的閘絶線膜形成以後之步驟相同，形成通道蝕刻型之 液晶顯示裝置或通道保護膜型之液晶顯示裝置。 且，採用Al-0.2at%Cu膜作為閛配線2之材料，惟若 為比電阻值小且不生成由水引起的腐蝕及小凸起之膜時， 採用A1膜或其他組成之A1合金膜亦可。 又，作為蝕刻由A1合金膜引起的蝕刻殘渣之方法，亦 可採用乾蝕法以取代濕蝕法。 若依本實施態樣，可得與實施態樣2相同的功效，同 時藉由遮罩層4被覆閘配線2等之配線部以去除配線間之 短路部等的缺陷部之際，由於使光罩層17作成光阻電路布 局圖案17,可使步驟簡略化。 奩施萌樣7 經濟部中央標隼局員工消費合作社印t (請先閱讀背面之注意事項再填寫本頁) 第10圖及第11圖偽表示載置有本發明之實施態樣7的 通道蝕刻型之TFT的輔肋容置通路閛方式之液晶顯示装置 的TFT陣列基Η之製造步驟的截面圖。圖中，28為閘端子 部、29為閘端子部28之接觸部分上形成的光阻電路布局圖 案、30為Al2〇3、31為端子、32為閘端子部28上之接觸部 分上形成的接觸孔、33為電氣連接閛端子部28及绱子31之 端子連接配線。且與第1圖相同部分則附上相同圖號並省 略說明。 其次，說明本實施態樣之铺肋容量通路閜方式的液晶 本紙張尺度適用中國國家標箪（CNS ) Λ4規洛（210 X 297公釐 23 3 9 0 0 8 525032 A7 B7 五、發明説明（22 ) 顯示裝置之TPT陣列基Η的製造方法。首先如第10圖（a) 所示般，藉由濺鍍法等於透明絶緣性基片1之表面上形成 Al-0.2at%Cu類比電阻值較小的金颶膜約300nm厚後，利 用照相製販法形成光阻，採用以磷酸、醋酸及硝酸為主成 分之独刻液進行電路布局圖案蝕刻，在形成具有蘭電極之 閘配線2及閘端子部2 8後去除光阻。此時蝕刻A卜0 . 2 a t % Cu膜時採用以磷酸、醋酸及硝酸為主成分之蝕刻液，惟經 事先檢討礎酸、醋酸及硝酸之組成，藉由將A 1-0 . 2 a t % C u 膜之蝕刻端面形成傾斜形狀，可提高上層所形成的膜之被 覆性。 經濟部中央標隼局員工消費合作杜印製 其次，如第10圖（b)所示般，例如藉由濺鍍法形成Ο 膜約lOOnm厚，用刷子清洗其表面後，塗布光阻，於形成 光阻電路布局圖案1 7使成能被覆由閘配線2等之A 1 - 0 . 2 a t % Cu膜而成的電路布局圖案之形狀後，蝕刻去除正露出的 Cr膜，形成由Cr膜等金屬膜16及光阻電路布局圖案17而成 的遮罩層14。其後於例如以磷酸、醋酸及硝酸為主成分之 蝕刻液内，浸漬必要的時間至使2 0 0 n m左右的A卜0 . 2 a t % Cii膜能受蝕刻，去除A卜0.2at%Cii膜而得的電路布局圖案 間之短路部等的蝕刻殘渣。其次，如第10圖（c)所示般， 去除已構成遮罩靥4之光阻電路布局圖案17及金屬膜16。 其次，如第1 0圖（d )所示般，於與閘端子部2 8之上層 的接觸部分上形成光阻電路布局圖案29後，為防止閘配線 2之腐蝕或與信號配線間之層間短路，將未為閘配線2及閘 端子部28之光阻所被覆的部分之A卜0.2at % Cu膜予以陽極 本紙張尺度適用中國國家標蕈（CNS ) A4現格（210 χ:297公釐） 3 9 0 0 8 (請先閱讀背面之注意事項再填寫本頁) 24 525032 A7 B7 五、發明説明（23 ) 氣化，於其表面上形成例如約ΙΟΟπϊπ厚之AI2O3膜30。此時 ，閘端子部28上之接觸部分因未為光阻電路布局圖案29所 被覆，故未受陽極氧化。其次，如第10圖（e)所示般，去 除閘端子部上之光阻電路布局圖案29。 其次，如第10圖（f)所示般，藉由電漿CVD法等，依序 形成成為閘絶緣膜5之矽氮化膜約5 0 0 n in ,非晶矽膜約2 0 0 nm,摻雜的η +型非晶矽膜約5〇nm後，採用由照相製版法而 形成的光阻，同時將非晶矽膜及η +型非晶矽膜作成電路布 局圖案，於閘配線2之上方的位置上形成半導體層6及歐姆 式接觸靥7。其次，如第11圖（a)所示般，利用濺鍍法等形 成透明導電膜ΙΤ0約100 n m後，採用由照相製販法形成的光 阻作成電路布局圖案，形成像元電極8及端子31。其次， 如第11圖（b)所示般，去除成為閘端子部28上之接觸部分 的矽氮化膜（閘絶緣膜5 ),形成接觸孔3 2。 經濟部中央標隼局員工消费合作社印製 其次，如第11圖U)所示般，由連缅於最下層上形成 構成與歐姆式接觸層7之型非晶矽膜具有歐姆式接觸性 良好的C r或T i ,等約1 0 0 n in ,於中間層上形成比®阻值較小 的Al-0.2at%Cu等約300ηπι ,於最上層上形成硬度較高且 可用刷子清洗的Cr約50nm膜，形成由此三靥膜而成之金屬 膜9後，進行刷子清洗。其次，如第11圖（d)所示般，採用 由照相製販法所形成的蝕刻光阻，將金颶膜9作成電路布 局圖案，形成電氣連接箸於歐姆式接觸層7上分離成二之 具有源配線的源電極1 0及汲電極1 1 ,與閙端子部1 8及端子 3 1之端子連接配線3 3。其次，利用乾蝕法蝕刻源電極1 0及 本紙張尺度適用中國國家標準（CNS ) A4規格(公釐） 3 9 0 0 8 (請先閲讀背面之注意事項再填寫本頁) 2 5 525032 A7 B7 五、發明説明（24 ) 汲電極11欲予去除的部分之n +型非晶矽膜（歐姆式接觸層 9)形成通道部後，去除光阻。最後，如第11圖（e)所示般 ,形成氮化矽膜，於像元電極8及端子31上以外的部分形 成保護膜1 2。 使於如此形成的第一基Η之TFT陣列基Η與其他透明 絶緣性基片上形成有遮光層、上塗層及對向電極之第二基 Η的對向基Η之表面上形成定向膜並使對向，對其間植入 液晶以密封劑封入，同時藉由在對向的陣列基片及對向基 Η之外側上配置偏光板而構成液晶嵌板。 且，採用Al-0,2at%Cu膜作為控制電極配線（本實施 態樣為閘配線2 ),惟若為比電阻值小且不生成由水引起的 腐蝕及小凸起之膜時，採用A1膜或其他組成之A1合金膜亦 可。 又，採用Cr膜作為遮罩層4 ,而若非為對A1合金膜之 蝕刻液所侵蝕時，亦可採用W膜等其他金屬膜。又，作為 蝕刻由A 1合金膜引起的蝕刻殘渣之方法，亦可採用乾蝕法 以取代濕蝕法。 經濟部中央標準局員工消費合作社印製 (請先閱讀背面之注意事項再填寫本頁) 又，雖然形成金颶膜16及光阻電路布局圖案17作為遮 罩層4,然而亦可僅以光阻電路布局圖案17構成遮罩層4。 若侬本實施態樣，卽使Μ由使構成閘配線2之A卜0.2 at % Cii膜陽極氣化並於表面上形成Al2〇 3,而具有防止A卜 0 . 2 a t % C U膜之腐蝕或閘配線2與其他信號配線間之層間短 路的構造之液晶顯示装置，亦可得與實施態樣5或實施形 態6相同的功效。 本紙張尺度適用中國國家標隼（CNS ) A4規格（210X 29。公廣） 〇 ft ο π λ λ 〇 525032 A7 B7 五、發明説明（25 ) 奮施熊樣8 第12圖及第13圖偽表示載置有本發明之實施態樣8的 通道蝕刻型之TFT的輔助容量通路閘方式之液晶顯示裝置 的TFT陣列基Η之製造步驟的截面圖。圖中，3 4為藉由去 除閘絶線膜5而形成的溝槽部。且與第10圖及第11圖相同 部分則附上相同圖號並省略說明。 其次，說明本實施態樣之輔助容量通路閘方式的液晶 顯示裝置之TFT陣列基片的製造方法。首先如第12圖（a) 所示般，藉由濺鍍法等於透明絶緣性基片1之表面上形成 A 1 - 0 . 2 a t % C u類比霄阻值較小的金颶膜約3 0 0 n m厚後，利 用照相製販法形成光阻，採用以磷酸、醋酸及硝酸為主成 分之蝕刻液進行電路布局圖案蝕刻，在形成具有閘電極之 閘配線2及閘端子部2 8後去除光阻。此時蝕刻A 1 - 0 . 2 at %U-type printed by employees of the Central Bureau of Standards of the Ministry of Economic Affairs. The local distribution resistance cloth uses the optical path to form a capacitive row rib method to enter the auxiliary plate solution and the engraving. Acid 閜 a has on and has a 30-acid vinegar-shaped film, which belongs to the acid, gold and phosphorus engraved with a small use case compared to when the picture is engraved with 0. ο 7 light line after the removal of the line at r I 2 points The gate and acid phosphorus are divided into vinegar and acid 0 when they are collected, and they are divided into 0 and 1 by a liquid. The main components are acid nitrate and acid vinegar. Each pair is formed by the pseudo of the film, A1 27. Used in combination, high-capacity lifting capacity group can be ribbed, co-acid-like, nitrate-shaped, and oblique-acid-overturned CU.% Of the film etched by the end of the forming surface. Applicable to China National Standard (CNS) A4 specification (21Gx M7 mm) 20 3 9 0 0 8 525032 A7 B7 V. Description of the invention (19) The structure of wiring 2 is short-circuited, forming a complicated structure of 2 pairs of broken wires. Next, as shown in FIG. 8 (b), for example, a Cr film is formed by a sputtering method to have a thickness of about 200 nm. After cleaning the surface with a brush, a photoresist is applied, and a photoresist circuit layout pattern 17 is formed to enable coating. After the shape of the circuit layout pattern formed by the Al-0.2at% Cu film of the gate wiring 2 and the auxiliary capacity wiring 27, etc., the exposed Cr film is etched away to form a metal film 16 such as the Cr film and a photoresist circuit layout The mask layer 4 formed by the pattern 17. Then, in an etching solution containing phosphoric acid, acetic acid, and nitric acid as the main components, the circuit is obtained by immersing the M-0.2at% Cu film at about 200 nm for etching and removing the Al-0.2at% Cu film. Etching residues such as short-circuited portions between layout patterns. Next, as shown in FIG. 8 (U), the photoresist circuit layout pattern 17 and the metal film 16 which have constituted the mask layer 4 are removed. The subsequent steps are the same as those after the gate insulating film formed by applying the CVD method of the aspect 1 or the aspect 2 to form a channel etching type liquid crystal display device or a channel protection film type liquid crystal display device. Printed by the Consumers' Cooperative of the Central Bureau of Standards, Ministry of Economic Affairs, and using Al-0.2at% Cu film as the material for 閜 wiring 2, but if it is smaller than the resistance value and does not generate corrosion and small raised film caused by water It is also possible to use AI film or A1 alloy film of other composition. In addition, a Cr film is used as the masking layer 4, and other metal films such as a W film may be used unless it is etched by the etching solution of the A1 alloy film. As a method for etching the etching residue caused by the Al alloy film, a dry etching method may be used instead of the wet etching method. According to this implementation mode, the same effect as implementation mode 2 can be obtained, and at the same time, the wiring layer such as wiring 2 is covered by the shielding layer 4 to remove the paper size of the wiring room. The national paper standard (CNS) A4 is applicable. Specifications (21GX29? Mm :) 3 9 0 0 8 (Please read the precautions on the back before filling out this page) 2 1 525032 A7 B7 V. Description of the invention (2) The defective parts such as the short-circuit part can also be used. The removal of the metal film 16 constituting the mask layer 4 can prevent short-circuit defects due to the metal film 16. Fenshi Aspect 6 FIG. 9 is a cross-sectional view showing the manufacturing steps of a TFT array substrate of a liquid crystal display device on which a TFT according to Embodiment 6 of the present invention is mounted. The number 傺 in the figure is the same as that in FIG. 8 and its explanation is omitted. Next, a method for manufacturing a TFT array substrate of a liquid crystal display device according to this embodiment will be described. First, as shown in FIG. 9 (a), a gold hurricane film having a small Al-0.2at% Cu analog resistance value is formed on the surface of the transparent insulating substrate H1 by sputtering to a thickness of about 300 nm. The photoresist is formed by the irradiation manufacturing method, and the circuit layout pattern is etched using an etching solution containing phosphoric acid, acetic acid, and nitric acid as main components. The photoresist is removed after the gate wiring 2 having the gate electrode and the auxiliary rib capacity wiring 27 are formed. At this time, the etching solution containing phosphoric acid, acetic acid and nitric acid as the main component is used when etching the Al-0.2at% Cu film, but after reviewing the composition of phosphoric acid, acetic acid and nitric acid in advance, the etching end surface of the Al-0.2at% Cu film is used. Forming an inclined shape can improve the coverability of the film formed on the upper layer. Printed by the Consumers' Cooperatives of the Central Bureau of Standards of the Ministry of Economic Affairs ^ (Please read the precautions on the back before filling out this page) Also, the auxiliary rib accommodation wiring 27 is constructed by making a short circuit with the gate wiring 2 for each pixel. , Forming a complicated structure of the disconnection of the gate wiring 2 pairs. Next, as shown in FIG. 9 (b), a photoresist is applied, and a photoresist circuit layout pattern 17 is formed so that it can be covered with a 0.2at% Cu film made of gate wiring 2 and auxiliary capacity wiring 27, etc. The shape of the circuit layout pattern is used as a mask layer 4. Then, in an etching solution containing, for example, phosphoric acid, acetic acid, and nitric acid as the main component, immersion is necessary for an A. 0.2 at% Cu film at about 200 nm to be etched to remove Al-0.2at%. Circuit layout pattern obtained from Cii film This paper scale applies Chinese national standard ((: > ^) into 4 specifications (210'297 cm) 〇〇.η Λ λ. 525032 A7 B7 V. Description of the invention (21) The etching residue of the short-circuit part and the like. Next, as shown in FIG. 9 (c), the photoresist circuit layout pattern 17 which has formed the photomask layer 4 is removed. The subsequent steps are different from the implementation mode 1 or implementation mode. The steps following the formation of the gate insulation film obtained by the CVD method and the like are the same, and a channel etching type liquid crystal display device or a channel protection film type liquid crystal display device is formed. Moreover, an Al-0.2at% Cu film is used as the hafnium wiring 2 As the material, if it is a film with a smaller specific resistance value and no corrosion or small bumps caused by water, an A1 film or an A1 alloy film of other composition may be used. Also, as an etching by an A1 alloy film For the method of residue, dry etching method can also be used instead of wet etching method. In this way, the same effect as that of Embodiment 2 can be obtained, and at the same time, the wiring portion such as the gate wiring 2 is covered by the mask layer 4 to remove the defective portion such as the short circuit portion between the wirings. The resistance circuit layout pattern 17 can simplify the steps. 步骤 施 萌 样 7 Printed by the Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs (please read the precautions on the back before filling this page) Figure 10 and Figure 11 are false representations A cross-sectional view of a manufacturing step of a TFT array substrate of a liquid crystal display device in which a channel-etched TFT of a channel etching type TFT of Embodiment 7 of the present invention is mounted. In the figure, 28 is a gate terminal portion, 29 It is a photoresist circuit layout pattern formed on the contact portion of the gate terminal portion 28. 30 is Al203, 31 is a terminal, 32 is a contact hole formed on the contact portion of the gate terminal portion 28, and 33 is an electrical connection. The terminal portion Terminal connection wiring of 28 and 绱 子 31. The same parts as in Fig. 1 are attached with the same figure numbers and descriptions are omitted. Next, the LCD that explains the ribbed capacity path 閜 method of this embodiment is used.箪 （CNS） Λ4 gauge (210 X 2 97 mm 23 3 9 0 0 525032 A7 B7 V. Description of the invention (22) Manufacturing method of TPT array substrate for display device. First, as shown in Fig. 10 (a), it is equal to transparent insulation by sputtering method A gold hurricane film with a relatively low Al-0.2at% Cu analogue resistance was formed on the surface of the substrate 1 with a thickness of about 300 nm, and then a photoresist was formed by a photographic method, using a unique etching solution containing phosphoric acid, acetic acid, and nitric acid as main components. The circuit layout pattern is etched, and the photoresist is removed after the gate wiring 2 and the gate terminal portion 28 having the blue electrode are formed. At this time, the etching solution of A. 0.2 at% Cu film is used with phosphoric acid, acetic acid and nitric acid as the main components. However, the composition of basic acid, acetic acid and nitric acid has been reviewed in advance, and A 1-0. 2 at The etched end face of the% Cu film is inclined to improve the coverage of the film formed on the upper layer. Consumption cooperation by employees of the Central Bureau of Standards, Ministry of Economic Affairs, followed by printing, as shown in Figure 10 (b). For example, a 0 film is formed by sputtering to a thickness of about 100 nm. After cleaning the surface with a brush, apply photoresist. The photoresist circuit layout pattern 17 is formed so as to cover the shape of the circuit layout pattern formed by the A 1-0. 2 at% Cu film of the gate wiring 2 and the like, and then the Cr film that is being exposed is removed by etching to form a Cr film A mask layer 14 formed of the metal film 16 and the photoresist circuit layout pattern 17 is formed. Then, in an etching solution containing, for example, phosphoric acid, acetic acid, and nitric acid as the main component, immersion is necessary for an A. 0.2 at% Cii film of about 200 nm to be etched, and A. 0.2 at% Cii is removed. Etching residues such as short-circuited portions between circuit layout patterns obtained from the film. Next, as shown in FIG. 10 (c), the photoresist circuit layout pattern 17 and the metal film 16 that have formed the mask 靥 4 are removed. Next, as shown in FIG. 10 (d), after the photoresist circuit layout pattern 29 is formed on the contact portion with the upper layer of the gate terminal portion 28, in order to prevent corrosion of the gate wiring 2 or interlayers with the signal wiring Short-circuit, the anode of 0.2A% Cu film that is not covered by the photoresistor of the gate wiring 2 and the gate terminal portion 28 is used as the anode. This paper is applicable to China National Standard (CNS) A4 standard (210 x 297) (Centi) 3 9 0 0 8 (Please read the notes on the back before filling out this page) 24 525032 A7 B7 V. Description of the invention (23) Vaporize, forming an AI2O3 film 30 with a thickness of, for example, about 100πϊπ on the surface. At this time, since the contact portion on the gate terminal portion 28 is not covered by the photoresist circuit layout pattern 29, it is not anodized. Next, as shown in Fig. 10 (e), the photoresist circuit layout pattern 29 on the gate terminal portion is removed. Next, as shown in FIG. 10 (f), a silicon nitride film to be the gate insulating film 5 is formed by a plasma CVD method and the like in order of about 500 n in, and the amorphous silicon film is about 200 nm. After the doped η + -type amorphous silicon film is about 50 nm, a photoresist formed by a photoengraving method is used. At the same time, the amorphous silicon film and the η + -type amorphous silicon film are used to form a circuit layout pattern for the gate wiring. A semiconductor layer 6 and an ohmic contact 7 are formed at a position above 2. Next, as shown in FIG. 11 (a), a transparent conductive film ITO is formed at about 100 nm by a sputtering method or the like, and then a circuit layout pattern is formed by using a photoresist formed by a photo process to form the pixel electrode 8 and the terminal 31. . Next, as shown in Fig. 11 (b), the silicon nitride film (gate insulating film 5) which becomes a contact portion on the gate terminal portion 28 is removed to form a contact hole 32. Printed by the Consumer Cooperatives of the Central Bureau of Standards of the Ministry of Economic Affairs. As shown in Figure 11 U), the type of amorphous silicon film that is formed on the lowermost layer to form the ohmic contact layer 7 has good ohmic contact. C r or T i, such as about 100 n in, on the intermediate layer to form Al-0.2at% Cu, which has a lower resistance than ®, such as about 300 ηπ, on the upper layer to form a higher hardness and can be cleaned with a brush A Cr film having a thickness of about 50 nm was used to form a metal film 9 made of the three-layer film, and then brush-washed. Secondly, as shown in FIG. 11 (d), the photo-resist formed by the photofabrication method is used to form the gold hurricane film 9 into a circuit layout pattern, and an electrical connection is formed on the ohmic contact layer 7 to be separated into two. The source electrode 10 and the drain electrode 11 having the source wiring are connected to the terminals 33 of the 閙 terminal portion 18 and the terminal 31 by the wiring 33. Secondly, dry etching method is used to etch the source electrode 10 and this paper size applies Chinese National Standard (CNS) A4 specifications (mm) 3 9 0 0 8 (Please read the precautions on the back before filling this page) 2 5 525032 A7 B7 V. Description of the invention (24) After the channel portion is formed on the n + -type amorphous silicon film (ohmic contact layer 9) of the portion to be removed of the drain electrode 11, the photoresist is removed. Finally, as shown in FIG. 11 (e), a silicon nitride film is formed, and a protective film 12 is formed on the pixel electrode 8 and the portion other than the terminal 31. An alignment film is formed on the surface of the TFT array substrate having the first substrate thus formed and the transparent substrate having the light-shielding layer, the overcoat layer, and the second substrate of the counter electrode formed on the other transparent insulating substrate. A liquid crystal panel is formed by placing a liquid crystal therebetween with a sealant, and placing a polarizing plate on the opposite side of the array substrate and the opposite substrate. In addition, an Al-0, 2at% Cu film is used as the control electrode wiring (gate wiring 2 in this embodiment), but if it is a film with a smaller specific resistance value and no corrosion and small protrusions caused by water, A1 film or A1 alloy film of other composition is also possible. In addition, a Cr film is used as the masking layer 4, and other metal films such as a W film may be used unless it is etched by the etching solution of the A1 alloy film. As a method for etching the etching residue caused by the Al alloy film, a dry etching method may be used instead of the wet etching method. Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs (please read the precautions on the back before filling this page). Although the golden hurricane film 16 and photoresist circuit layout pattern 17 are formed as the mask layer 4, it can also be printed with light only. The resistive circuit layout pattern 17 constitutes the mask layer 4. In this embodiment of the lens, the anode M is formed by vaporizing the anode of 0.2 at% Cii film constituting the gate wiring 2 and forming Al203 on the surface, thereby preventing corrosion of the film at 0.2 at% CU. A liquid crystal display device having a structure of an interlayer short circuit between the gate wiring 2 and other signal wiring can also obtain the same effect as that of the fifth embodiment or the sixth embodiment. This paper size applies to China National Standards (CNS) A4 (210X 29. Public) 〇ft ο π λ λ 〇525032 A7 B7 V. Description of the invention (25) Fenshi bear-like 8 Figures 12 and 13 are false A cross-sectional view showing a manufacturing process of a TFT array substrate of a liquid crystal display device of an auxiliary capacity via gate method in which a channel-etched TFT of Embodiment 8 of the present invention is mounted. In the figure, reference numeral 34 is a groove portion formed by removing the gate insulating film 5. In addition, the same parts as those in Figs. 10 and 11 are given the same reference numerals and descriptions are omitted. Next, a method for manufacturing a TFT array substrate of a liquid crystal display device of the auxiliary capacity path gate type according to this embodiment will be described. Firstly, as shown in FIG. 12 (a), the surface of the transparent insulating substrate 1 by sputtering is equivalent to the formation of A 1-0. 2 at% C u. After 0 0 nm thickness, a photoresist was formed by a photo-processing method, and a circuit layout pattern was etched using an etching solution containing phosphoric acid, acetic acid, and nitric acid as main components. The gate wiring 2 and the gate terminal portion 28 having the gate electrode were removed and formed. Photoresist. Etch A 1-0. 2 at%
Cu膜時採用以磷酸、醋酸及硝酸為主成分之蝕刻液，惟經 事先檢討磷酸、醋酸及硝酸之組成，藉由將Al-0.2at%Cu 膜之蝕刻端面形成傾斜形狀，可提高上層所形成的膜之被 覆性。 經濟部中央標隼局員工消费合作社印製 (請先閱讀背面之注意事項再填寫本頁) 其次，如第1 2圖（b )所示般，於分割與閘端子部2 8之 上層接觸的部分及相鄰的閘配線二間之位置上形成光阻電 路布局圖案2 9後，為防止蘭配線2之腐蝕或與信號配線間 之層間短路，使閘配線2及閘端子部2 8之未為光阻所被覆 的部分之A卜0.2at%Cu膜陽極氣化，於其表面上形成Al2〇3 膜例如約1 0 0 η m厚。此時間端子部2 8上之接觸部分因為光 阻電路布局圖案29所被覆，故未受陽極氣化。又，即使於 本紙張尺度適用中國國家標準（CNS ) A4規格（297公釐） 27 3 9 0 0 8 525032 A7 B7 五、發明説明（26 ) 像元内之相鄰的閘配線2間存在著A卜0.2at%Cii膜之蝕刻 殘渣等的情形，於分割閘配線2間之位置上為光阻電路布 局圖案29所被覆，而未受陽極氣化故，可在其後步驟去除 此蝕刻殘渣。其次，如第12圖（c)所示般，去除光阻電路 布局圖案29。 其次，如第12圖（d)所示般，藉由電漿CVD法等，依 序形成成為閛絶線膜5之矽氮化膜約5 0 0 n m 、非晶矽膜約 200nm、摻雜的n +型非晶矽膜約50nm後，採用由照相製版 法而形成的光阻，同時將非晶矽膜及η +型非晶矽膜作成電 路布局圖案，於閘配線2之上方的位置上形成半導體層6及 歐姆式接觸層7。其次，如第12圖（e)所示般，利用濺鍍法 等形成透明導霄膜IT0約ΙΟΟηιη後，採用由照相製版法形成 的光阻作成電路布局圖案，形成像元電極8及端子31。其 次，如第12圖（f)所示般，去除以光阻電路布局圖案2 9被 覆的蘭端子部2 8上之接觸部分，及相鄰的閘配線2間上之 矽氮化膜（閘絶絲膜5),以形成接觸孔32及溝槽部34。 經濟部中央標隼局員工消費合作社印货 (請先閱讀背面之注意事項再填寫本頁) 其次，如第13圖U)所示般，由連绩於最下層上形成 構成與歐姆式接觸層7之n+型非晶矽膜具有歐姆式接觸性 良好的C r或T i等約1 0 0 η m ,於中間層上形成比電阻值較小 的A卜0.2at%Cu等約300nm ,於最上層上形成硬度較高且 可用刷子清洗的C「約50nm膜，形成由此三層膜而成之金屬 膜9後，進行刷子清洗。其次，如第1 3圖（b )所示般，採用 由照相製販法所形成的蝕刻光阻，將金屬膜9作成電路布 局圖案，形成電氣連接著於歐姆式接觸層7上分離成二之 本紙張尺度適用中國國家標準（CNS ) A4規烙（210X2(厂公釐） 28 3 9 0 0 8 525032 A7 B7 經濟部中央樣隼局員工消費合作社印製 五、發明説明（27 ) 1 I 具 有 源 配 線 的 源 電 極 10及 汲 電 極 11 9 與 閘 端 子 部 18及 端 子 1 1 I 31之端 子 連 接 配 線 33 〇 其 次 $ 利 用 乾 蝕 法 蝕 刻 源 電 極 10及 1 1 I 汲 電 極 11欲予去除的部分 之 η + 型 非 晶 矽 膜 ( 歐 姆 式 接 m 層 ^-S 請 1 I 9 )形成通 道 部 後 $ 剝 離 光 阻 0 最 後 1 如 第 1 3圖 (c ) 所 示 般 先 閱 讀 1 I $ 形 成 氮 化 矽 膜 $ 於 像 元 電 極 8、 端子3 1 及 溝 槽 部3 1上以 背 I& 之 1 1 I 外 的 部 分 形 成 保 護 膜 12 0 在此溝槽部34 僳 相 當 於 設 於 第 注 意 事 1 1 I 4圖所示的容易生成短路缺陷之部分上的開口部1 由以上的步驟，成為閙配線2間之短路的原 5〇 因 之 蝕 刻 項 再 填 寫 本 頁 '—· 1 1 I 殘 渣 生 成 的 領 域 t 係 由 於 形 成 溝 槽 部 34而呈 表 面 露 出 的 狀 1 1 I 態 费 又 > 閛 配 線 2等之其他信號配線由於為閘絶綠膜5或保 1 1 I 護 膜 12所被 覆 著 » 在 此 狀 態 於 例 如 以 磷 酸 醋 酸 及 硝 酸 為 1 1 主 成 分 之 蝕 刻 液 内 9 浸 漬 必 要 的 時 間 至 使 2 0 0 η m左右的A 1 - 訂 1 0 . 2a t， ^ C li膜能受蝕刻， 去除A 1 - 0 . 2 a t % C U 膜 而 得 的 電 路 1 1 布 局 圖 案 間 之 短 路 部 等 的 独 刻 殘 渣 0 此 時 f 於 使 為 將 保 護 1 I 膜 12作 成 電 路 布 局 圖 案 而 形 成 的 光 阻 殘 存 之 狀 態 下 由 防 ά 1 I 止 信 號 配 線 之 腐 独 的 觀 點 以 進 行 去 除 独 刻 殘 渣 一 事 較 宜 〇 使 於 如 此 形 成 的 第 一 基 Η 之 TFT 陣 列 基 Η 與 其 他 透 明 I 1 1 绝 m 性 基 片 上 形 成 有 遮 光 靥 Λ 上 塗 層 及 對 向 電 極 之 第 二 基 1 1 Η 的 對 向 基 Η 之 表 面 上 形 成 定 向 膜 並 使 對 向 9 於 其 間 植 入 1 1 液 晶 以 密 封 劑 封 入 9 同 時 Μ 由 在 對 向 的 陣 列 基 片 及 對 向 基 1 I Η 之 外 側 上 配 置 偏 光 板 而 構 成 液 晶 嵌 板 0 1 I 且 9 採 用 A 1 [-0 . ί ! a t C 1 丨膜 作 為 配 線 2 之 材 料 1 惟 若 為 1 1 I 比 電 阻 值 小 且 不 生 成 由 水 引 起 的 腐 蝕 及 小 凸 起 之 m 時 % 採 1 1 I 用 A 1膜 或 其 他 組 成 之 A 1 丨合 金 膜 亦 可 0 1 1 本紙張尺度適用中國國家標隼(:CNS ) A4規格（210、：97公慶） 2 9 3 9 0 0 525032 A7 B7 五、發明説明（28 ) 若依本實施態樣，在不形成保護控制電極配線（本實 施態樣為閘配線2)之遮罩層下，可得與實施態樣7相同的 功效。 奮渝熊樣9 第14圖像表示載置有本發明之實施態樣9的TFT之液晶 顯示装置的TFT基片之製造步驟的截面圖。圖中，35為金 靥膜。且與第1圖相同部分則附上相同圖號並省略說明。 其次，説明本實施態樣之液晶顯示裝置的TFT陣列基 片之製造方法。首先如第14圖U)所示般，藉由濺鍍法於 透明絶緣性基片1之表面上連缠形成由下層係以Al-0.2at % C ii類之比電阻值較小的金颶約3 0 0 η πι厚，上層像以例如 Mo類硬度較Α1為高的金屬膜，由此二層膜而成的金屬膜35 後，進行刷子清洗。其次，如第14圖（b)所示般，藉由照 相製販法形成光阻，採用以磷酸、醋酸及硝酸為主成分之 (請先閱讀背面之注意事項再填寫本頁) 經濟部中央標隼局員工消費合作社印製 極刻颶 硝組高形刻使 電蝕金 及之 提面独 即 閘時刻 酸 酸度端 - , 有同蝕 醋硝速 刻又氣 具可次 。 、及 刻蝕 。氧 成由一 U 酸酸蝕之性有 形藉可 W 磷醋之膜覆含 ,時 ，S 以 、膜CU被内 膜此膜 U 用酸CU% 之體 C 。颶 採礎％ a 膜氣 t 2 (J % 阻 金 2 俗 討 C0 . 的 匆 at光種線時檢 2-0成蝕 2 除二配膜先-0A1形使 -0去之閛CU事Ai使所 ， A1後35之 ％ 惟較由層法 及 3 膜極at，度藉上蝕 膜線颶電 2 液速 ，高乾 Mopie金閛-0刻刻置提用 刻 1 成有A1蝕蝕蝕可採 蝕#構具刻之之側 ，， 鑛2¾成成蝕分膜膜狀時 連 線形形 ，成MOMO形35 液配颶 ，又主使加斜膜 刻閛金35為 ，增傾屬 蝕之的膜 酸成 ，成金 本紙張尺度適用中國國家標隼（CNS ) Λ4規格（210:097公釐） 3 0 3 9 0 0 8 525032 A7 B7 五、發明説明（29 ) 邊氣化光阻邊蝕刻金饜膜35,亦可使A卜0,2at % Cu膜之蝕 刻端面形成傾斜形狀。 又，如第14圖（c)所示般，於金屬膜35之蝕刻及光阻 去除後，亦可去除Mo膜，又，藉由採用硬度較A1為高且高 熔點金屬材料形成金颶膜35之上層膜，於A 1-0.2at%Cii膜 上進行陽極氣化處理亦可予去除。結果，藉由減少由於閘 配線2等之配線間之高度差，可提高上層所形成的膜之被 覆性。再者，藉由去除構成閘配線2等的金屬膜35之上層 膜，可去除正附著於上層膜上的塵埃等。 以後的步驟，偽與於實施態樣1或實施態樣2之藉由電 漿CVD法等的閘絶緣膜形成以後的步驟相同，形成通道蝕 刻型之液晶顯示裝置或通道保護膜型之液晶顯示装置。 且，採用A卜0 . 2 a t % C u膜作為閛配線2之材料，惟若 為比電阻值小且不生成油水引起的腐蝕及小凸起之膜時， 採用Α1膜或其他組成之Α1合金膜亦可。 經濟部中央標隼局Μ工消费合作社印製 (請先閱讀背面之注意事項再填寫本頁) 若依本實施態樣，於閛配線2之表面上形成硬度較高 的金屬層，籍由在刷子清洗後形成光阻作成電路布局圖案 ，可得與實施態樣1相同的功效。 奮偷熊槺1 0 第15圖俗表示載置有本發明之實施態樣10的TFT之液 晶顯示装置的TFT基Η之製造步驟的截面圖。圖中之圖號 與第9圖者相同，省略說明。 其次，説明本實施態樣之液晶顯示装置的T F Τ陣列基 Η之製造方法。首先如第15圖（a)所示般，籍由濺鍍法於 本紙張尺度適用中國國家標车（CNS ) A4说格（2丨0,<:297公廣） 3 1 3 9 0 0 8 525032 A7 B7 五、發明説明（3〇 ) 透明絶緣性基HI之表面上形成Cr或Ta等金颶約400ηπι厚 後，由照相製販法形成光阻，採用含有硝酸之蝕刻液進行 電路布局圖案蝕刻，在形成具有閘電極之閘配線2及共同 配線3後去除光阻。此時在蝕刻Cr或Ta膜時偽採用含有硝 酸之蝕刻液，惟搴先檢討硝酸之組成，藉由將Cr膜或Ta膜 之蝕刻端面形成傾斜形狀，可提高上層所形成的膜之被覆 性。 其次，如第15圖（b)所示般，塗布光阻，形成光阻電 路布局圖案17成為閘配線2及共同配線3等所被覆的形狀後 ，於對構成閘配線2等之C r膜或T a膜等的金颶膜之蝕刻液 内，浸漬必要的時間至使400ηπι左右之上述金屬膜能受蝕 刻，去除金颶膜而引起的電路布局圖案間之短路等的蝕刻 殘渣。其次，如第15圖（c)所示般，去除已構成遮罩膜4之 光阻電路布局圖案17。 以後的步驟，像與於實施態樣1或實施態樣2之藉由電 漿CVD法等的閛絶緣膜形成以後的步驟相同，形成通道蝕 刻型之液晶頴示装置或通道保護膜型之液晶顯示装置。 經濟部中央標準局員工消費合作社印製 若依本實施態樣，即使於閘配線2由Cr膜等所形成的 情形，藉由可確實的蝕刻去除信號配線間之短路缺陷部， 可防止信號配線間之短路，可以高良品率製出可靠性高的 液晶顯示裝置。 奮旃熊樣1 1 第16圖偽表示載置有本發明之實施態樣11的TFT之液 晶顯示裝置的TFT基Η之製造步驟的截面圖。圖中之圖號 本紙張尺度適用中國國家標隼（CNS ) Α4規格（210,<297公t ) 3 9 0 0 8 (請先閱讀背面之注意事項再填寫本頁) 32 525032 A7 B7 五、發明説明（31 ) 與第1 0圖者相同，省略說明。 (請先閱讀背面之注意事項再填寫本頁) 其次，説明本實施態樣之液晶顯示裝置的TFT陣列基 K之製造方法。首先如第16圖（a)所示般，藉由濺鍍法於 透明絶緣性基片1之表面上形成Cr或Ta等金颶約400nm厚 ,由照相製版法形成光阻，採用含硝酸之蝕刻液進行電路 布局圖案蝕刻，在形成具有閘電極之閘配線2及共同配線 3後去除光阻，此時在蝕刻Cr或Ta膜時係採用含有硝酸之 蝕刻液，惟事先檢討硝酸之組成，藉由將Cr或Ta膜之蝕刻 端面形成傾斜形狀，可提高上層所形成的膜之被覆性。 其次，如第16圖（b)所示般，藉由電漿CVD法等，依序 形成成為閘絶緣膜5之矽氮化膜約5 0 0 n m、非晶矽膜約2 0 0 rim、摻雜的n +型非晶矽膜約50ηιπ後，採用由照相製販法而 形成的光阻，同時將非晶矽膜及η +型非晶矽膜作成電路布 局圖案，於閘配線2之上方的位置上形成半導體層6及歐姆 式接觸層7。其次，如第16圖（c)所示般，利用濺鍍法等形 成透明導電膜IT0約ΙΟΟηπι後，採用由照相製販法形成的光 ο 8 極 S 元 像 成 形 案 圖 局 布 路 電 成 作 阻 經濟部十央標準局Μ工消費合作社印製 圖 6 1 如 , 膜 次化 其氮 矽 的 膜 線 絶 閘 線線 配 配 awn aw 於的 刻鄰 蝕相 , 割 般分 示能 所至 成 形 所 間 成 形 以 間 為 上 部 子 ， 端膜 閘化 於氮 與 矽 偽的 , 用 驟而 步 孔 刻觸 蝕接 之之 膜部 化觸 氮接 矽的 此間 C 層 4 34上 部與 槽成 溝形 進 時 同 圖 6 11 第 如 〇 次 刻其 蝕 行 成 形 上 層 下 最 於 纊 1 由 般 示 所 性 觸 接 式 姆 歐 有 具 膜 矽 晶 非 型 ♦ Π 之 7 層 觸 接 式 姆 歐 與 成 構 本紙張尺度適用中國國家標率（CNS ) Α4規格（2iGx：：97公釐） 33 3 9 0 0 8 525032 A7 B7 五、發明説明（32 ) 良好的C r或T i等約1 0 0 n m ,於中間層上形成比電阻值較小 的Al-0.2at%Cu等約300nm ,於最上層上形成硬度較高且 可用刷子清洗的Cr約50ηπι膜，形成由此三層膜而成之金屬 膜9後，進行刷子清洗。其次，如第1 6圖（f )所示般，採用 由照相製販法所形成的蝕刻光阻，將金屬膜9作成電路布 局圖案，形成源配線及歐姆式接觸層7上已分離成二之源 電極1 0及汲電極1 1。其次，利用乾蝕法蝕刻源電極1 0及汲 電極11欲予去除的部分之n +型非晶矽膜（歐姆式接觸層9) 形成通道部後，去除光阻。最後，如第16圖（g)所示般， 形成氮化矽膜，於像元電極8及溝槽部34上以外的部分形 成保護膜12。在此溝槽部34像相當於設於第4圖所示的容 易生成短路缺陷之部分上的開口部15。 使於如此形成的第一基Μ之TFT陣列基Η與其他透明 絶緣性基片上形成有遮光層、上塗層及對向電極之第二基 Η的對向基Η之表面上形成定向膜並使對向，於其間植入 液晶以密封劑封入，同時藉由在對向的陣列基片及對向基 Η之外側上配置偏光板而構成液晶嵌板。 經濟部中央標準局員工消費合作社印製 (請先閱讀背面之注意事項再填寫本頁) 若依本贲施態樣，在不形成保護控制電極配線（本實 施態樣為閘配線2)下，可得與實施態樣7相同的功效。 發明功效 若依本發明，為使信號配線成低電阻化，即使採用A 1 膜或A1合金膜而成之單層膜，或於表面層上採用具有A1条 金屬膜之多層膜而構成蘭配線等之信號配線的情形，Μ由 金屬膜或非金颶膜或金颶膜及非金屬膜之多層膜而成的遮 本紙張尺度適用中國國家標隼（CNS ) Α4現格（21〇 χ 297公釐） 3 4 3 9 0 0 8 525032 A7 B7 五、發明説明（33 ) 罩層被覆其表面，由確實的蝕刻去除信號配線間之短路缺 陷 缺 〇 路陷 短缺 除路 去短 由的 藉起 , 引 又層 〇 罩 路遮 短於 之由 間止 線防 配可 號， 信層 止罩 防遮 可除 , 去 部後 陷部 絶在短 的可之 成 ，間 形刻線 所蝕配 上予號 層並信 上出止 之露防 間部 ， 線路下 配短目 號陷數 信缺驟 除之步 去間之 的線等 分配成 部號形 由信層 藉使罩 ,, 遮 又等加 層增 綠不 層 0 金 的 高 較 度 硬 成 形 上 層 面 表 之 線 配 號 信 於 由 〇 藉 陷 又 缺 路 號成 信 構 止可 防料 可材 , 的 案小 圖較 局 值 布阻 路電 } b 成用 S έ- 阻因 光 ， 成果 形結 後 〇 洗路 清短 子之 刷間 在線 , 配 率 品 良 高 以 〇 可置 , 裝 化示 線顯 細晶 案液 圖的 局功 布電 路耗 電消 其低 使之 可化 故率 , □ 線開 配高 號出 信製 明 説 蜇 簡 之 式 圖 之 置 装 示 顯 晶 液 的 1Χ 樣 態 施 實 之 明 發 本 示 表 為 圖 1Χ 第 圖 之 用 而 用 作 的 1Χ 樣 態 施 實 之 明 發 本 〇 明 _ 說 面供 截為 的圖 驟 2 步第 造 製 (請先閱讀背面之注意事項再填寫本頁) 經濟部中央標孳局員工消费合作社印製 圖 之 用 而 用 作 的 r = --* 樣 態 施 實 之 明 發 本 明 說 供 為 圖 3 第 圖 之 用 而 用 作 的 11 AW 榜 態 施 實 之 明 發 本 明 說 供 為 圖 4 第 之 置 装 示 顯 晶 液 的 2 樣 態 施 實 之 明 發 本 示 表 為 圖 5 第 圖 面 截 的 驟 步 造 製 樣 態 施 實 之 明 發 本 示 表 為 圖 6 第 之 置 装 示 顯 晶 液 本紙張尺度適用中國國家標準（CNS ) Λ4規格（210X29·7公t ) 35 3 9 0 0 8 525032 A7 B7 五、發明説明（34 經濟部中央標隼局員工消費合作社印製 之之 之之之 之之之 之之的 置置 置置置 置置置 置置驟 裝裝 裝裝裝 装裝装 装装步 示 示 示 示 示 示 示 示 示 示 造 顯顯 顯顯顯 顯顯顯 顯顯製 晶 晶 晶 晶 晶 晶 晶 晶 晶晶之 液液 液液液 液液液 液液置 的的 的的的 的的的 的的装 ο 1 一卩 4567788911-习 樣樣 樣樣樣 樣樣樣 樣樣顯 態態 態態態 態態態 態態晶 施施 施施施 施施施 施施液 實實 實實實 實實實 實實種 之之 之之之 之之之 之之此 明明 明明明 明明明 明明的 發發 發發發 發發發 發發用 。本。本。本。本。本。本。本。本。本。本 c 習 圖示圖示圖示圖示圖示圖示圖示圖示圖示圖示圖示 面表面表面表面表面表面表面表面表面表面表面表 截為截為截為截為截為截為截為截為截為截為截為I 的圖的圖的圖的圖的圖的圖的圖的圖的圖的圖的圖 明 驟7驟8驟9驟10驟11驟12驟1驟1驟1驟1驟1 。説 步第步第步第步第步第步第步第步第步第步第步第圖之 造造 造造 造造 造造 造造 造面號 製 製製製 製製製 製製製 製截圃 (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） 36 3 9 0 0 8 525032 A7 B7 五、發明説明（35 ) 1 基Η 線 配 蘭 2 線 配 同 共 3 層 罩 遮 4 膜 緣 絶 閘 5 層 體 導 半 6 層 觸 接 式 姆 歐 7 極 元 像 8 9 0 12 3 11 1X 11 1i 膜極極膜 颶 電電護 線 金源汲保配 部 陷 缺 路 短 (請先閲讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作社印製 5 6 7 8 9 11 1 1 1 部 Π 開 案 圖 局 布 路 膜霣 屬阻 金光 膜 護 保 道 通 層 髖 導 半 膜 矽 晶 非 道 通 11 2 線 配 閙 域 領 汲 、 源 本紙張尺度適用中國國家標革（CNS ) A4規格（210,< 297公釐） 37 3 9 0 0 8 525032 A7 B7 五、發明説明（36 25 絶線膜 67890123 22223333 孔 觸 接 線 配 用 置 容 肋 輔 案 圖 局 布 部路 子電 端阻 閘光 子 端 3 孔 觸 接 線 配 接 I 遵 子 端 (請先閱讀背面之注意事項再填寫本頁) 5 3 部膜 槽颶 溝金 經濟部中央標隼局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS ) Μ規格（210X 297公釐） 38 3 9 0 0 8An etching solution containing phosphoric acid, acetic acid, and nitric acid as the main component is used for the Cu film. However, after reviewing the composition of phosphoric acid, acetic acid, and nitric acid in advance, the etched end surface of the Al-0.2at% Cu film can be formed into an inclined shape, which can improve the upper layer. Coverability of the formed film. Printed by the Employees' Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs (please read the precautions on the back before filling out this page) Secondly, as shown in Figure 12 (b), the contact with the upper layer of the brake terminal section 28 is divided. After the photoresist circuit layout pattern 29 is formed on the part and the position between two adjacent gate wirings, in order to prevent the corrosion of the blue wiring 2 or the short circuit between the signal wirings, the gate wirings 2 and the gate terminal portions 2 and 8 A 0.2at% Cu film is anode-vaporized for the photoresist-covered portion, and an Al203 film is formed on the surface, for example, about 100 nm thick. At this time, the contact portion on the terminal portion 28 is not covered by anode vaporization because it is covered by the photoresist circuit layout pattern 29. In addition, even if the Chinese national standard (CNS) A4 specification (297 mm) is applied to this paper size, 27 3 9 0 0 8 525032 A7 B7 V. Description of the invention (26) There are two adjacent gate wirings in the pixel. A. In the case of etching residues of 0.2at% Cii film, etc., the photoresist circuit layout pattern 29 is covered at the position between the split gate wirings 2 without being vaporized by the anode. Therefore, this etching residue can be removed in a subsequent step. . Next, as shown in Fig. 12 (c), the photoresist circuit layout pattern 29 is removed. Next, as shown in FIG. 12 (d), by a plasma CVD method or the like, a silicon nitride film that becomes the insulating film 5 is about 500 nm, an amorphous silicon film is about 200 nm, and a doping is sequentially formed. After the n + type amorphous silicon film is about 50 nm, a photoresist formed by a photoengraving method is used, and the amorphous silicon film and the η + type amorphous silicon film are used to form a circuit layout pattern at a position above the gate wiring 2 A semiconductor layer 6 and an ohmic contact layer 7 are formed thereon. Next, as shown in FIG. 12 (e), after forming a transparent conductive film IT0 by sputtering method or the like, the circuit layout pattern is formed by using a photoresist formed by a photoengraving method to form the pixel electrode 8 and the terminal 31. . Next, as shown in FIG. 12 (f), the contact portion on the blue terminal portion 28 covered with the photoresist circuit layout pattern 29 and the silicon nitride film (gate on the adjacent gate wiring 2) are removed. The insulation film 5) is used to form the contact hole 32 and the groove portion 34. Employees of the Central Bureau of Standards, Ministry of Economic Affairs, print the goods at the consumer cooperative (please read the precautions on the back before filling out this page) Secondly, as shown in Figure 13 U), a continuous contact layer is formed on the bottom layer to form an ohmic contact layer The 7+ n + type amorphous silicon film has a good ohmic contact such as C r or T i of about 100 η m, and forms a relatively low specific resistance A on the intermediate layer, such as 0.2 at% Cu and about 300 nm. On the uppermost layer, a film "C" of about 50 nm, which is relatively hard and can be cleaned with a brush, is formed after forming the metal film 9 formed by the three layers of films, followed by brush cleaning. Second, as shown in Fig. 13 (b), Using the photoresist formed by the photofabrication method, the metal film 9 is used as a circuit layout pattern to form an electrical connection connected to the ohmic contact layer 7 and separated into two paper sizes. Applicable to China National Standard (CNS) A4 regulations ( 210X2 (factory millimeter) 28 3 9 0 0 8 525032 A7 B7 Printed by the Consumer Cooperative of the Central Bureau of Samples of the Ministry of Economic Affairs 5. Description of the invention (27) 1 I Source electrode 10 and drain electrode 11 9 with gate wiring and gate terminal Portion 18 and terminal 1 1 I 31 Connection wiring 33 〇 Secondly, a dry etching method is used to etch the source electrode 10 and 1 1 I drain electrode 11 to remove the η + -type amorphous silicon film (ohmic layer m-layer ^ -S please 1 I 9) to form a channel The rear part is peeled off the photoresist 0 and the last one is read as shown in Figure 13 (c). 1 I $ The silicon nitride film is formed on the pixel electrode 8, the terminal 3 1 and the groove part 31. I & 1 1 A protective film is formed outside the I 12 0 The groove portion 34 僳 is equivalent to the opening portion 1 on the portion prone to short-circuit defects shown in the figure 1 1 I 4 from the above steps Please fill in this page as the original etching factor of the short circuit between the two wirings. “— 1 1 I The area where the residue is generated t is exposed because of the formation of the groove portion 34 1 1 I > 信号 Wiring 2 and other signal wirings are covered with green insulation film 5 or 1 1 I protective film 12 »In this state, for example, phosphoric acid, acetic acid and nitric acid are used as the main components of 1 1 9 immersion time in the etching solution is necessary to make A 1-about 10 0 2 m t, ^ C li film can be etched, remove A 1-0. 2 at% CU film circuit 1 1 Single-cut residues such as short-circuited portions between layout patterns 0 At this time, f is protected from photo-resistance in the state where the photoresist formed by protecting the 1 I film 12 as a circuit layout pattern is left alone It is more appropriate to remove the singulated residues. A light-shielding layer Λ is formed on the first substrate TFT array substrate thus formed and other transparent I 1 1 insulating substrates. An alignment film is formed on the surface of the opposite substrate of the second substrate 1 1 并使 and the opposite substrate 9 is implanted therebetween. 1 1 The liquid crystal is sealed with a sealant 9 at the same time. M is formed by the opposite array substrate and the opposite substrate 1 I.偏 A polarizing plate is arranged on the outer side to form a liquid crystal panel 0 1 I and 9 uses A 1 [-0. ! at C 1 丨 The film is used as the material of the wiring 2 1 But if it is 1 1 I The specific resistance value is small and the corrosion caused by water and small bumps are not generated.% Adopt 1 1 I Use A 1 film or other components A 1 丨 alloy film can also be used 0 1 1 This paper size is applicable to Chinese national standard (: CNS) A4 specifications (210 ,: 97 public holidays) 2 9 3 9 0 0 525032 A7 B7 V. Description of the invention (28) Ruo Yi In the present embodiment, the same effect as that in the embodiment 7 can be obtained without forming a mask layer for protecting the control electrode wiring (the gate wiring 2 in the embodiment). Fenyu Bear-like 9 The 14th image is a cross-sectional view showing the manufacturing steps of a TFT substrate of a liquid crystal display device on which the TFT of Embodiment 9 of the present invention is mounted. In the figure, 35 is a gold film. In addition, the same parts as those in FIG. 1 are given the same reference numerals and descriptions are omitted. Next, a method for manufacturing a TFT array substrate of a liquid crystal display device according to this embodiment will be described. First, as shown in FIG. 14 U), a gold hurricane having a small specific resistance value of Al-0.2at% C ii is formed from the lower layer by continuous sputtering on the surface of the transparent insulating substrate 1 by sputtering. About 3 0 0 η π thick, the upper layer image is, for example, a metal film having a higher Mo hardness than A1, and the metal film 35 formed from the two-layer film is washed by a brush. Secondly, as shown in Figure 14 (b), a photoresist is formed by a photographic method, using phosphoric acid, acetic acid, and nitric acid as the main components (please read the precautions on the back before filling this page). The bureau ’s consumer cooperative printed high-profile engraving of the hurricane nitrate group to make the electro-etched gold and its surface appear to be the acidity and acidity of the gate at the moment of the gate. , And etching. Oxygen is etched by a U acid and is tangible. It is covered with a film of phosphoric acid. At that time, S is coated with CU and the film is coated with CU% of acid C. Hurricane mining% a film gas t 2 (J% resistance to gold 2 popularly discussed C0. Time at the light seed line inspection 2-0 into the corrosion 2 in addition to the first two films with a 0A1 shape to make the 0 go CU thing Ai As a result, 35% after A1, but compared with the layer method and 3 membrane poles at, using the etch film line hurricane 2 liquid speed, high-dry Mopie gold 閛 -0 engraving lift etch 1 into A1 etch Etching can be etched # The side of the structure is carved, and the mine 2¾ is formed into an etched and divided film, which is connected to the MOMO shape. The liquid 35 is mixed with hurricane, and the oblique film is engraved with gold 35 to increase the tilt. It is a film of acid that is etched, and the paper size of gold is applicable to the Chinese National Standard (CNS) Λ4 specification (210: 097 mm) 3 0 3 9 0 0 8 525032 A7 B7 V. Description of the invention (29) Edge gasification light The edge-etching of the Au film 35 can also make the etched end face of the A, 0.2at% Cu film into an inclined shape. Also, as shown in FIG. 14 (c), after the metal film 35 is etched and the photoresist is removed The Mo film can also be removed. Furthermore, by using a metal material with higher hardness than A1 and a high melting point metal material to form the upper layer of the gold hurricane film 35, the anode gasification treatment on the A 1-0.2at% Cii film can also be removed. . As a result, by reducing The height difference between wirings such as wire 2 can improve the coverability of the film formed on the upper layer. Furthermore, by removing the upper film of the metal film 35 constituting the gate wiring 2 and the like, the dust that is adhering to the upper film can be removed. The subsequent steps are the same as those after the formation of the gate insulating film by plasma CVD method or the like in implementation mode 1 or implementation mode 2, forming a channel etching type liquid crystal display device or a channel protection film type. Liquid crystal display device. Moreover, A. 2 at% Cu film is used as the material of the 閛 wiring 2. However, if it is a film having a lower specific resistance and no corrosion caused by oil and water and small protrusions, an A1 film or Other compositions of A1 alloy film are also available. Printed by the Ministry of Economic Affairs, Central Bureau of Standards, M Industrial Consumer Cooperative (please read the precautions on the back, and then fill out this page). According to this embodiment, the hardness will be formed on the surface of the wiring 2 The higher metal layer can form the circuit layout pattern by forming a photoresist after brush cleaning, and can obtain the same effect as that of the embodiment 1. The figure 15 shows that the embodiment of the present invention is mounted. Sample 10 TFT liquid crystal display device A cross-sectional view of the manufacturing steps of the TFT substrate. The figure numbers in the figure are the same as those in FIG. 9 and the description is omitted. Next, the manufacturing method of the TF array substrate of the liquid crystal display device of this embodiment will be described. As shown in figure (a), the Chinese National Standard Car (CNS) A4 standard (2 丨 0, <: 297 public broadcasting) is applied to this paper scale by the sputtering method. 3 1 3 9 0 0 8 525032 A7 B7 V. Description of the invention (30) After the formation of a gold hurricane such as Cr or Ta on the surface of the transparent insulating base HI is about 400 ηm thick, a photoresist is formed by a photo-making method, and an etching solution containing nitric acid is used to etch the circuit layout pattern. The photoresist is removed after the gate wiring 2 and the common wiring 3 having the gate electrode. At this time, an etching solution containing nitric acid is pseudo-used when etching the Cr or Ta film, but the composition of the nitric acid is first reviewed. By forming the etched end surface of the Cr or Ta film into an inclined shape, the coverage of the film formed by the upper layer can be improved . Next, as shown in FIG. 15 (b), a photoresist is applied to form a photoresist circuit layout pattern 17 to be covered with the gate wiring 2 and the common wiring 3, and then the Cr film constituting the gate wiring 2 and the like is formed. In the etching solution of gold hurricane film such as Ta film, etc., it is necessary to immerse the above-mentioned metal film of about 400 ηm to be etched to remove etching residues such as short circuit between circuit layout patterns caused by gold hurricane film. Next, as shown in Fig. 15 (c), the photoresist circuit layout pattern 17 which has been used to form the mask film 4 is removed. The subsequent steps are the same as those after the formation of the rhenium insulating film by the plasma CVD method in Embodiment 1 or Embodiment 2, forming a channel etching type liquid crystal display device or a channel protection film type liquid crystal. Display device. If printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs according to this implementation, even in the case where the gate wiring 2 is formed by a Cr film, etc., the short-circuit defect portion between the signal wiring can be removed by reliable etching, which can prevent the signal wiring. A short circuit in between can produce a highly reliable liquid crystal display device with a high yield. Furious bear-like 1 1 FIG. 16 is a cross-sectional view schematically showing a manufacturing process of a TFT substrate of a liquid crystal display device on which a TFT according to an embodiment 11 of the present invention is mounted. The drawing number in the picture is applicable to China National Standard (CNS) Α4 size (210, < 297 g t) 3 9 0 0 8 (Please read the precautions on the back before filling this page) 32 525032 A7 B7 5 The invention description (31) is the same as that in FIG. 10, and the description is omitted. (Please read the precautions on the back before filling this page.) Next, the manufacturing method of the TFT array substrate K of the liquid crystal display device of this embodiment will be described. First, as shown in FIG. 16 (a), a gold layer such as Cr or Ta is formed on the surface of the transparent insulating substrate 1 by a sputtering method to a thickness of about 400 nm, and a photoresist is formed by a photoengraving method. The etching solution is used to etch the circuit layout pattern, and the photoresist is removed after the gate wiring 2 and the common wiring 3 having the gate electrode are formed. At this time, an etching solution containing nitric acid is used when etching the Cr or Ta film, but the composition of nitric acid is reviewed in advance. By forming the etched end surface of the Cr or Ta film into an inclined shape, the coverability of the film formed on the upper layer can be improved. Next, as shown in FIG. 16 (b), by a plasma CVD method or the like, a silicon nitride film that becomes the gate insulating film 5 is about 500 nm, an amorphous silicon film is about 200 rim, After the doped n + -type amorphous silicon film is about 50 ηπ, a photoresist formed by a photographic method is used, and the amorphous silicon film and the η + -type amorphous silicon film are used to form a circuit layout pattern above the gate wiring 2 A semiconductor layer 6 and an ohmic contact layer 7 are formed at the positions. Next, as shown in FIG. 16 (c), a transparent conductive film IT0 is formed by a sputtering method or the like for about 100 nm, and then the light is formed by a photo-processing method. The 8-pole S-element image forming scheme is a circuit layout. For example, the membrane line of the film and its nitrogen silicon barrier film line with the etch aw phase adjacent to the etch aw phase, the separation can be shown to form The interlayer is formed with the interlayer as the upper part, and the end film is gated with nitrogen and silicon. The film is etched with a step-by-step hole to contact the nitrogen-contacted silicon. The C layer 4 34 has an upper groove and a groove. The time is the same as in Fig. 6. 11 The etching is performed at the 0th time. The upper layer is lower than the upper layer. It is shown by the general contact type. The MU has a film silicon crystal type. The paper size of the paper is applicable to China National Standards (CNS) A4 specifications (2iGx :: 97 mm) 33 3 9 0 0 8 525032 A7 B7 V. Description of the invention (32) Good C r or T i etc. about 1 0 0 nm to form Al-0.2a with lower specific resistance on the intermediate layer t% Cu, etc., is about 300 nm, and a Cr film with a hardness of about 50 ηm, which is relatively hard and can be cleaned by a brush, is formed on the uppermost layer. After the metal film 9 formed of the three-layer film is formed, brush cleaning is performed. Secondly, as shown in FIG. 16 (f), the metal film 9 is formed into a circuit layout pattern by using an etching photoresist formed by a photographic method to form a source wiring and an ohmic contact layer 7 which has been separated into two parts. Source electrode 10 and drain electrode 1 1. Next, a dry etching method is used to etch the n + -type amorphous silicon film (ohmic contact layer 9) of the source electrode 10 and the drain electrode 11 to be removed, and then the photoresist is removed. Finally, as shown in FIG. 16 (g), a silicon nitride film is formed, and a protective film 12 is formed on the pixel electrode 8 and the portion other than the trench portion 34. Here, the groove portion 34 corresponds to the opening portion 15 provided in a portion where short-circuit defects are easily generated as shown in FIG. An alignment film is formed on the surface of the TFT array substrate of the first substrate M and other transparent insulating substrates on which the light-shielding layer, the overcoat layer, and the second substrate of the counter electrode are formed. The liquid crystal panel is formed by placing the liquid crystal in the opposite direction, sealing it with a sealant, and arranging a polarizing plate on the outside of the opposite array substrate and the opposite substrate. Printed by the Consumers' Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs (please read the precautions on the back before filling this page). If this is the case, the protective control electrode wiring will not be formed (the gate wiring 2 in this embodiment), The same effect as that of Embodiment 7 can be obtained. EFFECT OF THE INVENTION According to the present invention, in order to reduce the resistance of signal wiring, even if it is a single-layer film made of A 1 film or A1 alloy film, or a multi-layer film with A1 metal film is used on the surface layer to form a blue wiring In the case of signal wiring, etc., M is made of a metal film or a non-gold film or a multi-layer film of a gold film and a non-metal film. The standard of the paper is applicable to China National Standard (CNS) A4 (21〇χ 297). (Mm) 3 4 3 9 0 0 8 525032 A7 B7 V. Description of the invention (33) The cover layer covers the surface, and the short-circuit defects between the signal wiring are removed by the exact etching. , The lead layer is shorter than the cover line, which can be numbered by the stop line. The cover stop of the letter layer can be removed, and the recessed part must be short, and the line is etched by the line. The number of layers is exposed, and the top and bottom of the letter are exposed, and the short line number is assigned to the line below the line. The number of lines that are absent from the step is to be divided into line numbers. The letter layer uses the cover to cover, etc. Adding layers to increase greenness but not 0 layers of gold The letter of the letter was constructed by 〇 borrowing and lacking the road number. The small picture of the case can prevent material and materials. The road map is more resistant than the local value.} B The use of S-blocking light, after the results are formed, the road is washed. The short brushes are online, the high rate of the product can be set to 0, and the local power distribution circuit of the display line showing the fine crystal solution is reduced by the power consumption to make it possible to reduce the failure rate. The letter-out system clearly states that the simplified version of the figure is equipped with a 1X display of crystal liquid. The display is shown in Figure 1X. The display is used as a 1 × display of the actual implementation. 〇 明 _ The second step of making the cut out is as follows (please read the precautions on the back before filling this page). The central government bureau of the Ministry of Economic Affairs prints drawings for the consumer cooperatives r =- -* Appearance of Shi Shiming Ming Ben said to be used for the purpose of Figure 3 and Figure 11 AW Bang Shi Shih Ming Ming Fa Benming said to be used for the display of crystal liquid 2 in Figure 4 Shi Shiming issued this chart as shown in Figure 5 This step is made in a step-by-step manner. The display is shown in Figure 6. The display is installed with crystal display liquid. The paper size is applicable to the Chinese National Standard (CNS) Λ4 specification (210X29 · 7 male t) 35 3 9 0 0 8 525032 A7 B7 V. Description of the invention (34 Printed by the Consumer Cooperatives of the Central Bureau of Standards of the Ministry of Economic Affairs. Show show show show show show show show show show show show show show show show show show show show show show show show show show show show show show show ο 1 卩 4567788911-XiYiYiYiYiYiYiYiYiYiYiXingXingXingXingXingXingXingXingXingXingXingXingXingXingXingXingXing Of this, this is clearly and clearly issued. this. this. this. this. this. this. this. this. this. This illustration is shown on the surface of the surface. The surface is the surface. The surface is the surface. The surface is the surface. The surface is the surface. The figure is the figure of the figure of the figure of the figure of the figure of the figure of the figure of I 1 step 1 step 1. Said step by step by step by step by step by step by step by step by step by step by step by step by step by step by step by step Garden (please read the notes on the back before filling this page) This paper size is applicable to Chinese National Standard (CNS) A4 size (210X 297 mm) 36 3 9 0 0 8 525032 A7 B7 V. Description of invention (35) 1 base配 Line with blue 2 lines with a total of 3 layers of cover 4 Membrane edge barrier 5 Layer body guide 6 Layers of contact type Mou 7 Polar element image 8 9 0 12 3 11 1X 11 1i Jinyuan Jibao Distribution Department is short of roads (please read the notes on the back before filling this page) Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 5 6 7 8 9 11 1 1 1 Membrane is a gold barrier film, protective layer, hip, semi-membrane, silicon, non-canal, 11 2 wire, and field source. The paper size is applicable to China National Standard Leather (CNS) A4 specification (210, < 297 mm). ) 37 3 9 0 0 8 525032 A7 B7 V. Description of the invention (36 25 insulation film 67890123 22223333 holes Auxiliary plans for contact wiring with supporting ribs, layout of the circuit board, electrical terminal block, photon terminal, 3 hole contact wiring, I compliance terminal (please read the precautions on the back, and then fill out this page) The paper standard printed by the Employees' Cooperatives of the Central Bureau of Standards and Finance of the Ministry of Economic Affairs applies the Chinese National Standard (CNS) M specifications (210X 297 mm) 38 3 9 0 0 8