CN102914927B - Array substrate and method for manufacturing same - Google Patents

Array substrate and method for manufacturing same Download PDF

Info

Publication number
CN102914927B
CN102914927B CN201210417724.7A CN201210417724A CN102914927B CN 102914927 B CN102914927 B CN 102914927B CN 201210417724 A CN201210417724 A CN 201210417724A CN 102914927 B CN102914927 B CN 102914927B
Authority
CN
China
Prior art keywords
maintenance
derby
data line
passivation layer
gate insulator
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201210417724.7A
Other languages
Chinese (zh)
Other versions
CN102914927A (en
Inventor
张弥
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by BOE Technology Group Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to CN201210417724.7A priority Critical patent/CN102914927B/en
Publication of CN102914927A publication Critical patent/CN102914927A/en
Application granted granted Critical
Publication of CN102914927B publication Critical patent/CN102914927B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Abstract

An embodiment of the invention provides an array substrate and a method for manufacturing the same. The array substrate comprises a substrate, grid scanning lines, grid insulating layers, data lines, maintenance metal blocks, passivation layers and connecting electrodes, wherein the grid scanning lines are positioned on the substrate, the grid insulating layers are positioned on the grid scanning lines and the substrate, the data lines are positioned on the grid insulating layers, the maintenance metal blocks are positioned on the grid insulating layers and are electrically connected with the data lines, the passivation layers are positioned on the grid insulating layers and the maintenance metal blocks and are provided with passivation layer via holes or grooves, the connecting electrodes are used for being electrically connected with maintenance metal lines used for maintenance, and are connected with the maintenance metal blocks by the passivation layer via holes or grooves, and sufficiently large contact areas are provided by the connecting electrodes for being connected with the maintenance metal lines. When the data lines are broken, the maintenance metal lines are directly deposited on the connecting electrodes of the maintenance metal blocks, as the sufficiently large contact areas are provided by the connecting electrodes, contact areas among the maintenance metal lines and connecting electrodes of maintenance points are enlarged, and the maintenance success rate is increased.

Description

A kind of method of array base palte and manufacturing array substrate
Technical field
The present invention relates to liquid crystal panel manufacturing technology, refer to a kind of method of array base palte and manufacturing array substrate especially.
Background technology
Thin Film Transistor (TFT) array base palte (TFT-LCD) is low in energy consumption, low cost of manufacture and radiationless, by array base palte and color membrane substrates, box is formed, in prior art, as shown in Figure 1, array base palte comprises: controlling grid scan line 1 and data line 5 vertical with it, adjacent controlling grid scan line 1 and data line 5 define pixel region, each pixel region includes a TFT switch, the public electrode 11 of pixel electrode 10 and part, gate insulator 4, semiconductor active layer 3, the grid 2 of TFT switch, source electrode 6 and drain electrode 7, passivation layer 8 covers on each device above-mentioned, and above drain electrode 7, form passivation layer via hole or groove 9, pixel electrode 10 is connected with the drain electrode 7 of TFT switch by passivation layer via hole or groove 9, for reducing the light leak in pixel after box, the both sides being parallel to data line in pixel form shield bars 12.TFT-LCD can lower the induced leakage current in raceway groove, and shield bars 12 adopts the material identical with grid 2, in same photo-mask process (Mask), complete making; Wherein, memory capacitance 13 can be formed between the part of pixel electrode 10 and controlling grid scan line 1.
When fracture occurs data line 5, as shown in Figure 2, need to punch on data line 5, deposition maintenance metal wire 16, is reconnected data line 5 by maintenance metal wire 16.
There are the following problems for prior art: when fracture occurs data line 5, as shown in Figures 2 and 3, need on data line 5, beat connecting hole 17 and deposition maintenance metal wire 16, by maintenance metal wire 16, data line 5 is reconnected, but connecting hole 17 is little with the contact area of maintenance metal wire 16, easily causes keeping in repair unsuccessfully.
Summary of the invention
The technical problem to be solved in the present invention is to provide a kind of method of array base palte and manufacturing array substrate, beat connecting hole on the data line for solving in prior art and deposit maintenance metal wire in the process reconnecting data line, because the contact area between connecting hole and maintenance metal wire is too small, easily cause keeping in repair failed defect.
The embodiment of the present invention provides a kind of array base palte, comprising: substrate; Controlling grid scan line, is positioned on described substrate; Gate insulator, is positioned on described controlling grid scan line and substrate; Data line, is positioned on described gate insulator; Maintenance derby, is positioned on described gate insulator, is electrically connected with described data line; Passivation layer, is positioned on described gate insulator and maintenance derby, and has passivation layer via hole or groove; Connecting electrode, described connecting electrode is connected with described maintenance derby by described passivation layer via hole or groove, is electrically connected with between the maintenance metal wire of maintenance for providing enough large contact area.
In described array base palte, described data line and maintenance derby adopt same material.
In described array base palte, the material of connecting electrode is tin indium oxide, indium zinc oxide or aluminum zinc oxide.
In described array base palte, also comprise: shield bars, be positioned on described substrate, be parallel to described data line.
In described array base palte, maintenance derby comprises organic material bead, and this organic material bead contains conductive silver glue.
A method for manufacturing array substrate, comprising: on substrate, deposit the first metallic film, and forms controlling grid scan line on described first metallic film; Deposit gate insulator, described gate insulator is positioned on described controlling grid scan line and substrate; Deposit second metallic film, described second metallic film is formed data line and maintenance derby; Deposit passivation layer, described passivation layer is positioned on described gate insulator, and has passivation layer via hole or groove; Arrange the connecting electrode be connected with described maintenance derby through described passivation layer via hole or groove, described connecting electrode is electrically connected with between maintenance metal wire for providing enough large contact area.
In described method, also comprise: by photoetching process and chemical etching technology, while described first metallic film forms described controlling grid scan line, form the grid of described controlling grid scan line, and public electrode and shield bars; The process of deposit gate insulator also comprises: deposit one thin film transistor (TFT); And, by photoetching process and chemical etching technology, described grid is formed with the raceway groove above active layer and described grid.
The beneficial effect of technique scheme of the present invention is as follows: maintenance derby 15 is electrically connected with data line 5, when there is fracture in data line 5, maintenance metal wire 16 is deposited directly on the connecting electrode 14 of maintenance derby 15, because connecting electrode 14 provides enough large contact area, thus the contact area between maintenance metal wire 16 and the connecting electrode 14 of maintenace point is increased, which ensure that maintenance metal wire 16 can be enough large with the contact area of maintenance derby 15, data line 5 after keeping in repair is worked well, improves repairable rate.
Accompanying drawing explanation
Fig. 1 represents the structural representation of prior art TFT-LCD array substrate;
Fig. 2 represents prior art repair data line schematic diagram;
Fig. 3 represents the cross-sectional schematic in prior art repair data line C-C cross section;
Fig. 4 represents the structural representation of a kind of array base palte of the embodiment of the present invention;
Fig. 5 represents that maintenance metal wire is deposited on the schematic diagram one on the connecting electrode of maintenance derby by the embodiment of the present invention;
Fig. 6 represents that maintenance metal wire is deposited on the schematic diagram two on the connecting electrode of maintenance derby by the embodiment of the present invention;
Fig. 7 represents the method flow schematic diagram of embodiment of the present invention manufacturing array substrate;
Controlling grid scan line 1
Grid 2
Semiconductor active layer 3
Gate insulator 4
Data line 5
Source electrode 6
Drain electrode 7
Passivation layer 8
Passivation layer via hole or groove 9
Pixel electrode 10
Public electrode 11
Shield bars 12
Memory capacitance 13
Connecting electrode 14
Maintenance derby 15
Maintenance metal wire 16
Connecting hole 17.
Embodiment
For making the technical problem to be solved in the present invention, technical scheme and advantage clearly, be described in detail below in conjunction with the accompanying drawings and the specific embodiments.
As shown in Figure 4, the single pixel vertical view of amorphous silicon film transistor (TFT) structure, adopts the bottom grating structure of back of the body raceway groove corrosion; The array base palte of TFT-LCD there are one group of controlling grid scan line 1 and public electrode 11 parallel with it, and vertical with controlling grid scan line 1 one group of data line 5 and shield bars 12; Adjacent controlling grid scan line 1 and data line 5 have intersected to form pixel region, comprise in a pixel region: TFT switching device, pixel electrode 10 and a public electrode 11; Wherein, TFT switching device is made up of grid 2, source electrode 6, drain electrode 7, gate insulator 4 and semiconductor active layer 3, and pixel electrode 10 is connected with drain electrode 7 by passivation layer via hole or groove 9.
The embodiment of the present invention provides a kind of array base palte, as shown in Figure 4, comprising:
Substrate;
Controlling grid scan line 1, is positioned on described substrate;
Gate insulator 4, is positioned on described controlling grid scan line 1, grid and substrate;
Data line 5, is positioned on described gate insulator 4;
Maintenance derby 15, is positioned on described gate insulator 4, is electrically connected with described data line 5;
Passivation layer 8, is positioned on described gate insulator 4 and maintenance derby 15, and has passivation layer via hole or groove 9;
For realizing with between the maintenance metal wire 16 of maintenance the connecting electrode 14 that be electrically connected, being connected with described maintenance derby 15 by passivation layer via hole or groove 9, being electrically connected with between the maintenance metal wire 16 keeped in repair for providing enough large contact area.
The technical scheme provided is provided, maintenance derby 15 is electrically connected with data line 5, when there is fracture in data line 5, maintenance metal wire 16 is deposited directly on the connecting electrode 14 of maintenance derby 15, because connecting electrode 14 provides enough large contact area, thus the contact area between maintenance metal wire 16 and the connecting electrode 14 of maintenace point is increased, which ensure that maintenance metal wire 16 can be enough large with the contact area of maintenance derby 15, data line 5 after keeping in repair is worked well, improves repairable rate.
In TFT-LCD array substrate, public electrode 11, is positioned on described controlling grid scan line 1 and gate insulator 4, and parallel with described controlling grid scan line 1;
In a preferred embodiment, data line 5 and maintenance derby 15 adopt same material.
In a preferred embodiment, the material of connecting electrode 14 is tin indium oxide, indium zinc oxide or aluminum zinc oxide.
The material of pixel electrode 10 is tin indium oxide, indium zinc oxide or aluminum zinc oxide; Connecting electrode 14 is identical with the material that pixel electrode 10 adopts, in same plated film, mask lithography and chemical etching technology, complete making.
In a preferred embodiment, shield bars 12, is positioned on array base palte, is parallel to data line 5.
Shield bars 12 completes in the process forming controlling grid scan line 1, or completes in the process forming data line 5, and shield bars 12 should be parallel to data line 5.The individual layer that public electrode 11 and shield bars 12 are aluminium, chromium, tungsten, tantalum, titanium, one of molybdenum and aluminium nickel or combination in any are formed or lamination layer structure.
In TFT-LCD array substrate, thin film transistor (TFT), is positioned at the intersection of controlling grid scan line 1 and data line 5, this thin film transistor (TFT) is coated with passivation layer 8, the drain electrode 7 of described thin film transistor (TFT) is formed with described passivation layer via hole or groove 9; Source electrode 6 and the described data line 5 of described thin film transistor (TFT) are electrically connected;
Pixel electrode 10, is positioned on described passivation layer 8, and is connected with the drain electrode 7 of described thin film transistor (TFT) by the described passivation layer via hole in the drain electrode of described thin film transistor (TFT) or groove 9.
In array base palte, there is several passivation layer via hole or groove 9, the effect of each passivation layer via hole or groove 9 is not quite similar.Wherein, the passivation layer via hole in the drain electrode of thin film transistor (TFT) or groove 9, for being connected with the drain electrode 7 of thin film transistor (TFT); At least two passivation layer via hole in close data line 5 position or groove 9 are then for providing interface channel for the direct connection between connecting electrode 14 and maintenance derby 15.
In a preferred embodiment, the source electrode 6 of controlling grid scan line 1, data line 5, thin film transistor (TFT) and drain electrode 7, and described maintenance derby 15 be aluminium, chromium, tungsten, tantalum, titanium, the individual layer of one of molybdenum and aluminium nickel or combination in any formation or lamination layer structure.Data line 5 is identical with the material that maintenance derby 15 adopts, and completes in same plated film, mask lithography and chemical etching technology.
Each embodiment of thering is provided is provided, as shown in Figure 4, on the array base palte of the TFT-LCD manufactured, there is one group of controlling grid scan line 1 and the public electrode 11 parallel with controlling grid scan line 1, and vertical with controlling grid scan line 1 one group of data line 5 and shield bars 12.
Adjacent controlling grid scan line 1 and data line 5 have intersected to form pixel region, and a pixel region includes TFT switching device-thin film transistor (TFT), pixel electrode 10 and a public electrode 11, gate insulator 4, semiconductor active layer 3; Thin film transistor (TFT) is made up of grid 2, source electrode 6 and drain electrode 7, and pixel electrode 10 is connected with drain electrode 7 by passivation layer via hole or groove 9.
Based on above-mentioned array base-plate structure, add maintenance derby 15, and maintenance derby 15 is electrically connected with data line 5 in data line 5 side, maintenance derby 15 adopts the metal material identical with data line 5.
As shown in Figure 5, use in data line 5 side the metal identical with data line 5 to make and keep in repair derby 15, and be electrically connected with data line 5.When there is fracture in data line 5, in the process of mantenance data line 5, maintenance metal wire 16 is deposited directly on the connecting electrode 14 of maintenance derby 15, because maintenance derby 15 comprises organic material bead, this organic material bead contains conductive silver glue, adopts laser to be smashed by bead, conductive silver glue is connected with the maintenance metal wire 16 on color membrane substrates, to increase maintenance metal wire 16 and the contact area of data line 5, improve maintenance rate.
Wherein, connecting electrode 14 has conducting function, cover maintenance derby 15 on be in order to protect maintenance derby 15 on passivation layer via hole or groove 9.When adopting laser to be smashed by the organic material bead including conductive silver glue, just by connecting electrode 14, maintenance derby 15 and maintenance metal wire 16 are linked together.Conductive silver glue is a kind of adhesive solidifying or have certain electric conductivity after drying, usually with matrix resin and conductive filler-conducting particles for principal ingredient, by the bonding effect of matrix resin, conducting particles is combined together to form conductive path, the conduction realized by gluing material connects.
In above-described embodiment, the source electrode 6 of controlling grid scan line 1, data line 5, thin film transistor (TFT) and drain electrode 7, public electrode 11, maintenance derby 15 and shield bars 12 material can be one of metal or alloy or the combination in any such as aluminium, chromium, tungsten, tantalum, titanium, molybdenum and aluminium nickel, and structure can be individual layer or lamination layer structure.Controlling grid scan line 1, public electrode 11 and shield bars 12 complete making in same plated film, mask lithography and chemical etching technology, and adopt identical material; Data line 5 and maintenance derby 15 adopt same material, complete in same plated film, mask lithography and chemical etching technology; Gate insulator 4 adopts the material such as silicon nitride or aluminium oxide, and pixel electrode 10 and connecting electrode 14 adopt the materials such as tin indium oxide, indium zinc oxide or aluminum zinc oxide.
As shown in Figure 6, TFT-LCD array substrate obviously can have various modifications and variations, specifically can by increasing or reduce exposure frequency and selecting different materials or combination of materials to manufacture TFT-LCD of the present invention.
The embodiment of the present invention provides a kind of method of manufacturing array substrate, as shown in Figure 7, comprising:
Step 701, substrate deposits the first metallic film, and forms controlling grid scan line 1 on described first metallic film;
Step 702, deposit gate insulator 4, described gate insulator 4 is positioned on described controlling grid scan line 1 and substrate;
Step 703, deposit second metallic film, described second metallic film is formed data line and maintenance derby 15;
Step 704, deposit passivation layer 8, described passivation layer 8 is positioned on described gate insulator 4, and has passivation layer via hole or groove 9;
Step 705, arranges the connecting electrode 14 be connected with described maintenance derby 15 through described passivation layer via hole or groove 9, and described connecting electrode 14 provides enough large contact area to be electrically connected with between maintenance metal wire 16.
In a preferred embodiment, also comprise: by photoetching process and chemical etching technology, the first metallic film is formed controlling grid scan line 1, grid 2, public electrode 11 and shield bars 12; Grid 2 is parts of controlling grid scan line 1, provides cut-in voltage for opening thin film transistor (TFT);
The process of deposit gate insulator 4 also comprises: deposition film transistor; And, by photoetching process and chemical etching technology, described grid 2 forms the raceway groove above semiconductor active layer 3 and described grid 2.
Described second metallic film forms data line 5 also comprise: by photoetching process and chemical etching technology formed on described second metallic film described data line 5, thin film transistor (TFT) source electrode 6 and drain electrode 7, wherein, part source electrode 6 and part drain electrode 7 are overlapped on described semiconductor active layer 3.
By photoetching process and chemical etching technology, the drain electrode 7 of thin film transistor (TFT) forms described passivation layer via hole or groove 9, be connected with pixel electrode 10 by this passivation layer via hole or groove 9.
The technology that Application Example provides manufactures TFT-LCD, and manufacture process comprises:
Step 801, array base palte deposits the first metallic film, forms controlling grid scan line 1, grid 2, public electrode 11 and shield bars 12 by photoetching process and chemical etching technology;
Step 802, consecutive deposition gate insulator 4 and amorphous silicon membrane on the array base palte of completing steps 801, by photoetching process and chemical etching technology formed on grid 2 semiconductor active layer 3 and above raceway groove.
Step 803, deposit second metallic film on the array base palte of completing steps 802, forms data line 5, source electrode 6, drain electrode 7 by photoetching process and chemical etching technology, and wherein part source electrode 6 and part drain electrode 7 are overlapped on semiconductor active layer 3; Thin film transistor (TFT) is formed after making source electrode 6 and drain electrode 7 complete.
Step 804, deposit passivation layer 8 on the array base palte of completing steps 803, forms the passivation layer via hole or groove 9 and connecting hole 17 that are positioned at drain electrode 7 by photoetching process and chemical etching technology; Drain voltage is delivered on pixel electrode 10 by passivation layer via hole or groove 9.
Step 805, the array base palte of completing steps 804 deposits the layer for etching pixel electrode 10, by photoetching process and chemical etching technology, form pixel electrode 10, connecting electrode 14 and maintenance derby 15, and pixel electrode 10 and drain electrode 7 are linked together.Wherein, keep in repair derby 15 to be connected with data line 5 formation integrative-structure.
Compared with the existing technology, the array base palte completed is provided with maintenance derby 15 in data line 5 side, and maintenance derby 15 is connected with data line 5.The organic material bead of maintenance derby 15 containing conductive silver glue, is smashed bead by laser, and conductive silver glue is connected with maintenance metal wire 16, to increase maintenance metal wire 16 and the contact area of data line 5, improves repairable rate.
TFT-LCD of the present invention by method manufacture below, can also comprise:
Step 901, uses magnetically controlled sputter method, array base palte is prepared a layer thickness and exists extremely metallic film as grid metallic film.
The material of grid metallic film adopts the metals such as molybdenum, aluminium, alumel, molybdenum and tungsten alloy, chromium or copper usually, also can use the unitized construction of above-mentioned different materials film.By gate mask version by exposure technology and chemical etching process, the certain area of array base palte forms controlling grid scan line 1, public electrode 11 and shield bars 12.
Step 902, utilizes chemical vapor deposition method consecutive deposition on array base palte arrive gate insulator 4, and arrive amorphous silicon membrane-semiconductor active layer 3; The material normally silicon nitride of gate insulator 4, also can use monox and silicon oxynitride etc.
After exposing with the mask of semiconductor active layer 3, dry etching is carried out to amorphous silicon, form silicon isolated island, and the gate insulator 4 between grid metal and amorphous silicon plays the effect stopping etching.
Step 903, adopts and prepares the similar method of controlling grid scan line 1, and the thickness that deposit one deck is similar to grid metallic film on array base palte exists arrive the second metallic film.
By forming data line 5, source electrode 6, drain electrode 7 and maintenance derby 15 in certain area on the second metallic film of the mask of source-drain electrode; Wherein, data line 5, source electrode 6, drain electrode 7 and shield bars 12 have identical thickness, because adopt identical etching technics, so have the same metal wire angle of gradient after etching, source electrode 6 and drain electrode 7 contact with the two ends of semiconductor active layer 3 respectively, form thin film transistor (TFT).
Step 904, adopts and prepares gate insulator 4 and the similar method of semiconductor active layer 3, whole array base palte deposits a layer thickness arrive passivation layer 8, material normally silicon nitride or the silicon dioxide of passivation layer 8.Now controlling grid scan line 1, public electrode 11 and shield bars 12 are coated with gate insulator 4 and passivation layer 8 above, and data line 5 and maintenance derby 15 are coated with the passivation layer 8 of same thickness above; By the mask of passivation layer 8, utilize the passivation layer via hole of exposure and etching technics formation drain electrode 7 part or groove 9 and connecting hole 17.
Step 905, adopts and prepares gate insulator 4 and the similar method of semiconductor active layer 3, whole glass substrate deposits one deck pixel electrode layer;
Use the mask of transparency electrode, by identical processing step, final formation pixel electrode 10, connecting electrode 14, maintenance derby 15 and memory capacitance 13, conventional transparency electrode is ITO or IZO, and thickness exists extremely between.
In the process making TFT-LCD, also can by increasing or reduce exposure frequency and selecting different materials or combination of materials to realize corresponding step, therefore, the structure of TFT-LCD obviously can have various modifications and variations.
Make in the TFT-LCD formed, maintenance derby 15 is positioned at same layer with data line 5, maintenance derby 15 and data line 5 are connected to form one structure, data line 5, public electrode 11 and shield bars 12 complete in same plated film, mask lithography are with chemical etching technology, and have employed identical material.The source electrode 6 of controlling grid scan line 11, data line 5, thin film transistor (TFT) and drain electrode 7, public electrode 11 or shield bars 12 be aluminium, chromium, tungsten, tantalum, titanium, the individual layer of one of molybdenum and aluminium nickel or combination in any formation or lamination layer structure, the material of gate insulator 4 is silicon nitride, silicon dioxide or aluminium oxide etc., and the material of pixel electrode 10 and connecting electrode 14 is tin indium oxide, indium zinc oxide or aluminum zinc oxide etc.
Compared with prior art, make by using the metal identical with data line 5 in data line 5 side and keep in repair derby 15, maintenance derby 15 is connected with data line 5.When keeping in repair the data line 5 of fracture, do not need drilling technology, but maintenance metal wire 16 is deposited directly on the connecting electrode 14 of maintenance derby 15, due to maintenance derby 15 comprising organic material bead, organic material bead contains conductive silver glue, being smashed by bead by laser makes conductive silver glue be connected with maintenance metal wire 16, to increase maintenance metal wire 16 and the contact area of data line 5, improves repairable rate.
The TFT-LCD made by technology adopting the embodiment of the present invention to provide obviously can carry out various forms of accommodation, as long as increase maintenance metal in data line 5 side, and maintenance metal is connected with data line 5.
The above is the preferred embodiment of the present invention; it should be pointed out that for those skilled in the art, under the prerequisite not departing from principle of the present invention; can also make some improvements and modifications, these improvements and modifications also should be considered as protection scope of the present invention.

Claims (6)

1. an array base palte, is characterized in that, comprising:
Substrate;
Controlling grid scan line, is positioned on described substrate;
Gate insulator, is positioned on described controlling grid scan line and substrate;
Data line, is positioned on described gate insulator;
Maintenance derby, is positioned on described gate insulator, is electrically connected with described data line, and maintenance derby comprises organic material bead, and this organic material bead contains conductive silver glue;
Passivation layer, is positioned on described gate insulator and maintenance derby, and has passivation layer via hole or groove;
Connecting electrode, described connecting electrode is connected with described maintenance derby by described passivation layer via hole or groove, is electrically connected with between the maintenance metal wire of maintenance for providing enough large contact area.
2. array base palte according to claim 1, is characterized in that,
Described data line and maintenance derby adopt same material.
3. array base palte according to claim 1, is characterized in that,
The material of described connecting electrode comprises tin indium oxide, indium zinc oxide or aluminum zinc oxide.
4. array base palte according to claim 1, is characterized in that, also comprises:
Shield bars, is positioned on described substrate, is parallel to described data line.
5. a method for manufacturing array substrate, is characterized in that, comprising:
Substrate deposits the first metallic film, and form controlling grid scan line on described first metallic film;
Deposit gate insulator, described gate insulator is positioned on described controlling grid scan line and substrate;
Deposit second metallic film, described second metallic film is formed data line and maintenance derby, and maintenance derby comprises organic material bead, and this organic material bead contains conductive silver glue;
Deposit passivation layer, described passivation layer is positioned on described gate insulator, and has passivation layer via hole or groove;
Arrange the connecting electrode be connected with described maintenance derby through described passivation layer via hole or groove, described connecting electrode is electrically connected with between maintenance metal wire for providing enough large contact area.
6. method according to claim 5, is characterized in that, also comprises:
By photoetching process and chemical etching technology, while described first metallic film forms described controlling grid scan line, form the grid of described controlling grid scan line, and public electrode and shield bars;
The process of deposit gate insulator also comprises: deposition film transistor; And, by photoetching process and chemical etching technology, described grid is formed with the raceway groove above active layer and described grid.
CN201210417724.7A 2012-10-26 2012-10-26 Array substrate and method for manufacturing same Active CN102914927B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201210417724.7A CN102914927B (en) 2012-10-26 2012-10-26 Array substrate and method for manufacturing same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201210417724.7A CN102914927B (en) 2012-10-26 2012-10-26 Array substrate and method for manufacturing same

Publications (2)

Publication Number Publication Date
CN102914927A CN102914927A (en) 2013-02-06
CN102914927B true CN102914927B (en) 2015-06-24

Family

ID=47613348

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201210417724.7A Active CN102914927B (en) 2012-10-26 2012-10-26 Array substrate and method for manufacturing same

Country Status (1)

Country Link
CN (1) CN102914927B (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107068918A (en) * 2017-05-12 2017-08-18 京东方科技集团股份有限公司 A kind of preparation method of oled panel
CN108538853B (en) * 2018-03-29 2019-12-31 武汉华星光电技术有限公司 Display device and array substrate thereof
CN112631003B (en) * 2020-12-30 2022-11-29 成都中电熊猫显示科技有限公司 Array substrate and broken line repairing method of array substrate

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0772183A2 (en) * 1995-11-01 1997-05-07 Samsung Electronics Co., Ltd. Matrix-type display capable of being repaired by pixel unit and a repair method therefor
US5684547A (en) * 1994-08-05 1997-11-04 Samsung Electronics Co., Ltd. Liquid crystal display panel and method for fabricating the same
CN101561598A (en) * 2008-04-14 2009-10-21 北京京东方光电科技有限公司 Array basal plate of liquid crystal display as well as manufacturing method and maintaining method thereof

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100382456B1 (en) * 2000-05-01 2003-05-01 엘지.필립스 엘시디 주식회사 method for forming Repair pattern of liquid crystal display

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5684547A (en) * 1994-08-05 1997-11-04 Samsung Electronics Co., Ltd. Liquid crystal display panel and method for fabricating the same
EP0772183A2 (en) * 1995-11-01 1997-05-07 Samsung Electronics Co., Ltd. Matrix-type display capable of being repaired by pixel unit and a repair method therefor
CN101561598A (en) * 2008-04-14 2009-10-21 北京京东方光电科技有限公司 Array basal plate of liquid crystal display as well as manufacturing method and maintaining method thereof

Also Published As

Publication number Publication date
CN102914927A (en) 2013-02-06

Similar Documents

Publication Publication Date Title
CN104217994B (en) A kind of thin-film transistor array base-plate and preparation method thereof, display device
CN101431093B (en) Organic light emitting device and method of fabricating the same
CN105452949B (en) The manufacturing method of semiconductor device, display device and semiconductor device
CN106409845A (en) Switch element, the preparation method of the switch element, array substrate and display apparatus
CN101561604B (en) TFT-LCD array substrate structure and manufacturing method thereof
CN104795434A (en) OLED pixel unit, transparent display device, manufacturing method and display equipment
CN109326609A (en) A kind of array substrate and preparation method thereof
CN101387800B (en) TFT LCD structure and method for manufacturing same
KR20080093709A (en) Thin film transistor substrate and manufacturing method thereof
CN103219389A (en) Thin film transistor and manufacturing method thereof and array substrate and display device
US20210202464A1 (en) Electrostatic Discharge Unit, Array Substrate and Display Panel
CN1987624A (en) TFT LCD array base board structure and its producing method
CN103489826A (en) Array substrate, manufacturing method and display device
TW201013279A (en) Liquid crystal display and method of manufacturing the same
CN102832254B (en) A kind of array base palte and manufacture method, display floater
CN102088025A (en) Thin film transistor substrate and method of manufacturing the same
CN106876479A (en) Thin film transistor (TFT) and preparation method thereof, array base palte and preparation method thereof, display panel
CN103765597A (en) TFT (Thin Film Transistor), manufacturing method thereof, array substrate, display device and barrier layer
CN102969311B (en) Array substrate and manufacturing method thereof, and display device
CN108807547A (en) Thin film transistor (TFT) and preparation method thereof, array substrate and preparation method thereof
WO2017195699A1 (en) Active matrix substrate, method for producing same, and display device
TW200841104A (en) Array substrate and method for manufacturing the same
CN102914927B (en) Array substrate and method for manufacturing same
CN103915451A (en) Array substrate, manufacturing method thereof and display device
CN202126557U (en) Array substrate

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant