522651522651
、發明説明（ 又月係屬於％子電路肖運轉之方法，及更特別者係屬 ' 於相同之兒路及方法上之一種延遲鎖定迴路及延遲 鎖定方法。 種l遲鎖《迴路τ能被使用I提供一與參考時脈有關 一具有預先決定之相信之時脈信號。儘管由延遲鎖定迴路 所供給《時脈信號按有關之參考時脈而被偏移，其相位將 輕參考相位為+。由延遲鎖定迴路產生之信號在此將歸屬 於如一先行之時脈信號。 袖一般言，一先行之時脈信號可使用於具有相對之高度整 口 < 一積體電路（〗c)上，例如一具有邏輯合併之記憶體 (MML)，一 Ram滙流排DRAM (RDRAM)，及一雙資料率 同步dram (DDR)。參考時脈信號由一輸入栓輸入並被分 配至全部之設備。在參考時脈信號到達一位置距離輸入栓 為相對較遠之時，可能與接近輸入栓一位置之參考時脈信 號來比較已被延遲。由於延遲之差別，使得〗C之每一部位 維持同步甚為困難。 因之，1C内可能包括有延遲鎖定迴路。該延遲鎖定迴路 一般置於接近於接收一參考時脈信號之一輸入栓處。延遲 鎖定迴路接收參考時脈信號，並產生一先行之時脈信號。 先行之時脈信號在頻率長度上與參考時脈信號相似。無論 為何，先行之時脈信號較有關之參考時脈信號被提前一相 位相當於由接近之位置至較遠之有關接收之參考時脈信號 4- 本纸張尺度適用中國國家標準(CNS) A4規格(210X297公釐)2. Description of the invention (The month belongs to the method of the% sub-circuit operation, and more specifically belongs to a delay lock loop and a delay lock method on the same path and method. A delay lock "loop τ can be Use I to provide a clock signal with a pre-determined belief in relation to the reference clock. Although the clock signal is shifted by the relevant reference clock provided by the delay-locked loop, its phase will be lighter with a reference phase of + The signal generated by the delay-locked loop will be attributed here as a prior clock signal. In general, a prior clock signal can be used on a whole circuit with a relative height < an integrated circuit (〖c) For example, a memory with logical combination (MML), a Ram bus DRAM (RDRAM), and a dual data rate synchronous dram (DDR). The reference clock signal is input by an input pin and distributed to all devices. When the reference clock signal reaches a position that is relatively far away from the input pin, it may be delayed compared with the reference clock signal near a position of the input pin. Due to the difference in delay, each of C It is very difficult to maintain synchronization of parts. Therefore, a delay lock loop may be included in 1C. The delay lock loop is generally placed near an input pin that receives a reference clock signal. The delay lock loop receives the reference clock signal, and An antecedent clock signal is generated. The antecedent clock signal is similar in frequency to the reference clock signal. In any case, the antecedent clock signal is advanced by a phase from the relevant reference clock signal by a phase equivalent to Remote reference clock signal related to reception 4- This paper size applies to China National Standard (CNS) A4 specification (210X297 mm)
522651 A7 ___ B7_ ___ 五、發明説明（2~~) ' 之較入栓位置所延遲之時間。使用之參考時脈信號為接近 於輸入栓之參考時脈信號，及被傳送至電路之先行之參考 時脈信號距離輸入栓為遠。在此一方式中，一成同步之時 脈信號可在I C之每一部位都可接收得到，及同步化之信號 即便在很高之速度下亦能使1C與參考時脈信號同步運轉。 圖1為慣常之延遲鎖定迴路之圖解方塊圖。慣常之延遲 鎖定迴路10包括一輸入緩衝器12，一可變延遲電路14， 一相位感測泵1 6及一延遲補償電路1 8。輸入緩衝器1 2將 一外加之時脈信號ECLK1予以緩衝來送出一參考時脈信號 RCLK1 。 延遲鎖定迴路依照可變延遲電路1 4來控制延遲之時間使 回饋時脈信號FCLK1之相位與參考之時脈rcLKI之相位相 符。其他之延遲鎖定迴路說明於美國專利5,614,855 ; 5,642,082，及 5,875,219 中。 慣常之延遲鎖定迴路之可變延遲電路包括η個延遲端 子，此處η指一預先決定之數目。由延遲端子之預先決定 之數目來限定一可變之延遲範圍，此可限制運轉之顏率。 此即，當被輸入之頻率較運轉頻率之區域為低時，可變延 遲卷路之相位偏移將不再增加’使得一較外部检信號為早 在回饋信號方面之信號產生搖擺。且當被輸入之頻率較運 轉之頻率為高時，可變延遲電路的相位偏移將不再降低， 使得較外部輸入信號為遲之信號在回饋信號之方向可能產 生搖擺。因此，I C運轉之頻率必須由延遲鎖定迴路加以限 制。 5- 522651 A7 B7522651 A7 ___ B7_ ___ 5. Description of the invention (2 ~~) 'The delay time compared with the position of the bolt. The reference clock signal used is the reference clock signal that is close to the input pin, and the previous reference clock signal that is transmitted to the circuit is far from the input pin. In this way, a synchronized clock signal can be received at every part of the IC, and the synchronized signal enables 1C to run synchronously with the reference clock signal even at very high speeds. Figure 1 is a diagrammatic block diagram of a conventional delay lock loop. The conventional delay lock loop 10 includes an input buffer 12, a variable delay circuit 14, a phase sensing pump 16 and a delay compensation circuit 18. The input buffer 12 buffers an additional clock signal ECLK1 to send a reference clock signal RCLK1. The delay lock loop controls the delay time according to the variable delay circuit 14 so that the phase of the feedback clock signal FCLK1 matches the phase of the reference clock rcLKI. Other delay locked loops are described in US Patents 5,614,855; 5,642,082, and 5,875,219. The variable delay circuit of the conventional delay-locked loop includes n delay terminals, where n refers to a predetermined number. A variable delay range is defined by a predetermined number of delay terminals, which can limit the rate of operation. That is, when the inputted frequency is lower than the operating frequency, the phase offset of the variable delay coil will not increase any more, so that a signal earlier than the external detection signal will sway. And when the input frequency is higher than the operating frequency, the phase offset of the variable delay circuit will no longer decrease, so that signals that are later than the external input signal may sway in the direction of the feedback signal. Therefore, the frequency of I C operation must be limited by the delay lock loop. 5- 522651 A7 B7
五、發明説明（3 發明搞要_ 此為本發明之目的乃提供-具有増加運轉頻率區域之延 遲鎖定迴路及方法。 本發明之另一目的為提供將回饋時脈信號之相位虫使用 於延遲鎖定迴路之參考時脈信號相位能匹配之一延遲鎖定 迴路及方法。 / 這些及其他目的按照本發明’由提供之延遲鎖定迴路產 生一先行之時脈信號且為接收之參考時脈㈣利步。延 遲鎖足迴路可包含-相位感測系感測關於先行時脈之回鎮 信號相對於參考時脈信號之間之相位差，依相位差方向送 出控制信號來控制電塵位準…可變延遲電路按照由相位 感測泵供給之控制信號之電壓位準來延遲參考時脈信號。 一相位偏移器將參考時脈信號之相位與由可變延遲電路延 f之-被延遲之時脈信號之相位加以比較來產生先行之時 =。：：延遲之時脈信號與有關之參考時脈信號之相 相位值為多8"，依參考之相位值來偏移被 脈::：1古仏號來產生先行之時脈信號。及當被延遲之時 關，參考時脈信號之相位差較參考之相位值為 V時’產生為我偏移之相位。 按=發明之另-方面’產生與—參考時脈 先行之時脈«之延遲較迴路，可包括—相位咸㈣咸 :】於；=脈之回饋信就相對於參考時脈信號：間之： :差’及…控制信號按相位差之方向來控制一電壓位 準。一可變延遲電路包括多個延遲端子按照來自相位感測 522651V. Description of the invention (3 Summary of the invention_ The purpose of the present invention is to provide a delay locked loop and method with an increased operating frequency region. Another object of the present invention is to provide a phase worm that feeds back clock signals to the delay One of the delay lock loops and methods whose phase of the reference clock signal of the lock loop can match. / These and other purposes according to the present invention 'produce a prior clock signal from the provided delay lock loop and receive the reference clock at a glance. The delay lockup circuit can include-the phase sensing system senses the phase difference between the clockwise signal relative to the reference clock signal and sends a control signal according to the phase difference direction to control the electric dust level ... variable The delay circuit delays the reference clock signal according to the voltage level of the control signal supplied by the phase sensing pump. A phase shifter compares the phase of the reference clock signal with the delay clock f delayed by the variable delay circuit. The phase of the signal is compared to generate the leading time =. :: The phase value of the delayed clock signal and the related reference clock signal is 8 ", according to the reference The phase value is used to offset the pulse ::: 1 ancient clock to generate the leading clock signal. And when the time is delayed, the phase difference of the reference clock signal is V when the phase value of the reference is V. The phase of shifting. According to = another aspect of the invention, the delay of the reference clock that precedes the clock «can be longer than the loop, which can include-the phase is salty:] in; the pulse of the pulse is relative to the reference clock Signal: Interval:: Difference 'and ... The control signal controls a voltage level according to the direction of the phase difference. A variable delay circuit includes multiple delay terminals according to the phase sensing 522651
栗送出之控制信號延遲參考時脈信號相符合之電壓位準來 產生先行之時脈信號。被起動之可變延遲電路之延遲端子 數目’最好按參考時脈信號之一頻率來決定。 延遲鎖定方法按照發明可使用一延遲鎖定迴路，該延遲 鎖定迴路產生與一參考時脈信號同步之先行之時脈信號。 使用一延遲鎖定迴路之延遲鎖定方法產生與一參考時脈信 號同步之一先行之時脈信號包括之步騾為a)延遲參考時脈 信號來產生一被延遲之時脈信號；b)感測被延遲之時脈信 號與有關之參考時脈信號之相位差；c)決定此相位差是^ 較一預先決定之參考之相位值為多；d)當相位差較參考之 相位值為多時偏移被波延遲之時脈信號來產生先行之時脈 信號；及e)在步驟a)控制參考時脈信號中延遲之量。 按照方法之另一方面，延遲鎖定方法用於一可變延遲 路來產生與接收到之參考時脈信號同步之先行之時脈 號，及參考時脈信號如同多個之延遲端子，可包含^感 關於先行時脈之回饋信號相對於參考時脈信號之間之 差；b)當相位差較疋為多時反轉回饋信號之相位；對 位差之宽度反應控制可變延遲電路之一被起動之延遲端 =數目’及d )依相位差之方法冑改變延遲時間將參考時; k號延遲來產生先行之時脈信號。 按照本發明之延遲鎖定迴路及延遲較方法，運轉心 :區域能予以增加。且，多餘之時並不需使用於將先行: 時脈信號1CLK2同料參考時脈信號RCLK2。The control signal sent by the pump is delayed with reference to the voltage level corresponding to the clock signal to generate the previous clock signal. The number of delay terminals of the activated variable delay circuit is preferably determined by a frequency of a reference clock signal. The delay lock method according to the invention may use a delay lock loop which generates a preceding clock signal synchronized with a reference clock signal. A delay-locking method using a delay-locked loop to generate a preceding clock signal in synchronization with a reference clock signal includes the following steps: a) delaying the reference clock signal to generate a delayed clock signal; b) sensing The phase difference between the delayed clock signal and the related reference clock signal; c) determines that the phase difference is ^ more than the phase value of a predetermined reference; d) when the phase difference is more than the reference phase value The delayed clock signal is shifted to generate a preceding clock signal; and e) in step a) controlling the amount of delay in the reference clock signal. According to another aspect of the method, the delay lock method is used for a variable delay circuit to generate a preceding clock number synchronized with the received reference clock signal, and the reference clock signal is like multiple delay terminals, which may include ^ Sense the difference between the feedback signal of the prior clock and the reference clock signal; b) reverse the phase of the feedback signal when the phase difference is larger; one of the variable delay circuits that controls the width of the difference Starting delay terminal = number 'and d) According to the method of phase difference, changing the delay time will refer to the time; the k-th delay will generate the leading clock signal. According to the delay lock loop and delay comparison method of the present invention, the operating center area can be increased. Moreover, when it is unnecessary, it is not necessary to use it in advance: the clock signal 1CLK2 is the same as the reference clock signal RCLK2.
裝 線 522651 五、發明説明（5 , 圖面重點說明 圖1為一慣常之延遲鎖定迴路方塊圖； 圖2為按照本發明之一具體實施例之一延遲鎖定迴路方 塊圖； 圖3為圖2之一可變延遲電路之圖解方塊圖； 圖4為圖2之一相位反轉控制器之電路圖； 圖5A為圖4當一被延遲之時脈信號DCLK2與有關之一參 考時脈信號RCLK2之相位差為；r或較小時之主端子之時間 圖及5B為圖4當一被延遲之時脈信號DCLK2與有關之一參 考時脈信號RCLK2之相位差為；r或較大時之主端子之時間 圖； 圖6為示出圖2之一延遲控制器一方塊圖； 圖7為圖6之一偏移控制器之電路圖； 圖8為按照圖7之主端子時間圖；及 圖9為圖2之一相位偏移器之電路圖。 所選具體實施例之詳細說明 本發明併用以下參考之圖面充份說明之，其中並示出發 明所選之具體實施例。所提供之這些具體實施例將徹底及 π全的予以揭示及將全部發明之範圍對精於此一技藝之士 加以表達，此發明無論如何有可能被具體實施成許多不同 之形式及闡述於此應不能被解釋為發明之限制全部中參考 之編號為元件代號。 參見圖2 , —延遲鎖定迴路2〇包括一輸入緩衝器21，一 可變延遲電路22，一相位偏移器23，一延遲補償電路 -8- 522651 A7 B7 五、發明説明（6 ) 2 4，一延遲控制器2 5，一相位反轉控制器2 7，及一相位 感測泵2 6。 輸入緩衝器2 1對一外部時脈信號ECLK2緩衝送出一參考 時脈信號RCLK2。 可變延遲電路22接收參考時脈信號RCLK2產生可產生一 先行時脈信號之被延遲之時脈信號。可變延遲電路2 2包括 有多個延遲端子，被延遲之時脈信號RCLK2為由延遲端將 參考時脈信號RCLK2延遲之一信號。最好，可變延遲電路 22被起動之延遲端子之數目受由來自延遲控制器25之記 數信號群Q C輸出所控制。 相位偏移器2 3接收被延遲之時脈信號DCLK2，及提供一 先行之時脈信號ICLK2。先行之時脈信號ICLK2及被延遲 之時脈信號DCLK2間之相位關係由被延遲之時脈信號 DCLK2與有關之參考時脈信號RCLK2間之相位差來決定。 此即，當被延遲之時脈信號DCLK2與有關之參考時脈信號 RCLK2之相位差較一預先決定之相位值為多時，被延遲之 時脈信號DCLK2之相位依參考之相位值而偏移產生一先行 之時脈信號ICLK2。當被延遲之時脈信號DCLK2與有關之 參考時脈信號RCLK2之相位差較參考之相位值為少時，產 生之先行之時脈信號ICLK2具有如被延遲之時脈信號 DCLK2相同之相位。 最好，參考之相位值為7Γ，以便當被延遲之時脈信號 DCLK2與有關之參考時脈信號RCLK2之相位差為7Γ或較多 時，先行之時脈信號ICLK2為一反轉之被延遲之時脈信號 -9 · 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐) 522651 A7 B7 五、發明説明（7 ) DCLK2之信號。當被延遲之信號DCLK2與有關之參考時 脈信號RCLK2之相位差為7Γ或較少時，先行之時脈信號 ICLK2為一不反轉之被延遲之時脈信號DCLK2之信號。 延遲補償電路24為用於對相位偏移器23補償之電路， 即，由延遲鎖定迴路2 0之一輸出點距至該先行之時脈信號 ICLK2處被使用之一點傳送延遲時間之補償。如果發生之 延遲時間為當參考時脈信號RCLK2到達相位感測泵2 6 時，延遲補償電路2 4對此延遲時間做補償。 如果延遲鎖定迴路20中未包括延遲補償電路24，接近 延遲鎖定迴路2 0之輸出點之一點及所屬之距離輸出點較遠 之一點間由於傳送延遲時間產生一不對稱。無論如何，如 果即使延遲補償電路2 4並未包括於延遲鎖定迴路内，按照 本發明此一效果乃可達成。並且，延遲補償電路24之一輸 出信號可為提供至相位感測泵2 6之一回饋信號FCLK2。 相位感測泵2 6感測參考時脈信號RCLK2與回饋信號 FCLR2間之相位差。並且，相位感測泵2 ό產生一類比控制 信號VCON2。 類比控制信號VCON2之電壓位準受回饋信號FCLK2與有 關之參考時脈信號RCLK2之相位差之方向控制。此即，當 回饋信號FCLK2之相位較該參考時脈信號RCLK2者為早 時，類比控制信號VCON2之電壓位準沿按照延遲電路2 2 之增加延遲時間之方向變化。並且，當回饋信號FCLK2之 相位較該參考時脈信號RCLK2之相位為遲時，類比控制信 號VCON之電壓位準沿按照可變延遲電路2 2之減少延遲時 -10- 本纸張尺度適用中國國家標準(CNS) Α4規格(210X 297公釐) ·； 裝 訂Installation line 522651 V. Description of the invention (5, the drawing emphasizes that FIG. 1 is a conventional block diagram of a delay lock loop; FIG. 2 is a block diagram of a delay lock loop according to a specific embodiment of the present invention; FIG. 3 is a view of FIG. 2 A schematic block diagram of a variable delay circuit; FIG. 4 is a circuit diagram of a phase inversion controller of FIG. 2; FIG. 5A is a diagram of a delayed clock signal DCLK2 and a reference clock signal RCLK2 The phase difference is; the time diagram of the main terminal when r or smaller and 5B are shown in Figure 4. When the phase difference between a delayed clock signal DCLK2 and a related reference clock signal RCLK2 is; Terminal timing diagram; Figure 6 is a block diagram showing a delay controller of Figure 2; Figure 7 is a circuit diagram of an offset controller of Figure 6; Figure 8 is a timing diagram of the main terminal according to Figure 7; and Figure 9 It is a circuit diagram of a phase shifter as shown in Fig. 2. Detailed Description of Selected Specific Embodiments The present invention will be fully explained with reference to the following drawings, in which specific selected embodiments of the invention are shown. These specific provided Examples will be thoroughly and fully disclosed The scope of the invention expresses the person skilled in this skill, this invention may in any case be embodied in many different forms and the description here should not be interpreted as a limitation of the invention. The reference number in all is the component code. Figure 2, —The delay lock loop 20 includes an input buffer 21, a variable delay circuit 22, a phase shifter 23, and a delay compensation circuit-8-522651 A7 B7 V. Description of the invention (6) 2 4, A delay controller 25, a phase inversion controller 27, and a phase sensing pump 26. Input buffer 2 1 buffers an external clock signal ECLK2 and sends a reference clock signal RCLK2. Variable delay circuit 22Receiving the reference clock signal RCLK2 generates a delayed clock signal that can generate a prior clock signal. The variable delay circuit 22 includes a plurality of delay terminals. The delayed clock signal RCLK2 is the reference time by the delay terminal. The pulse signal RCLK2 is delayed by one signal. Preferably, the number of delay terminals activated by the variable delay circuit 22 is controlled by the count signal group QC output from the delay controller 25. The phase shifter 2 is connected to 3 The delayed clock signal DCLK2 and a prior clock signal ICLK2 are provided. The phase relationship between the prior clock signal ICLK2 and the delayed clock signal DCLK2 is determined by the delayed clock signal DCLK2 and the related reference clock. The phase difference between the signals RCLK2 is determined. That is, when the phase difference between the delayed clock signal DCLK2 and the related reference clock signal RCLK2 is greater than a predetermined phase value, the delay of the clock signal DCLK2 The phase is shifted according to the reference phase value to generate a leading clock signal ICLK2. When the phase difference between the delayed clock signal DCLK2 and the related reference clock signal RCLK2 is less than the reference phase value, the leading one is generated The clock signal ICLK2 has the same phase as the delayed clock signal DCLK2. Preferably, the reference phase value is 7Γ, so that when the phase difference between the delayed clock signal DCLK2 and the related reference clock signal RCLK2 is 7Γ or more, the preceding clock signal ICLK2 is delayed by an inversion. Clock signal -9 · This paper size applies to China National Standard (CNS) A4 specification (210 X 297 mm) 522651 A7 B7 V. Description of the invention (7) Signal of DCLK2. When the phase difference between the delayed signal DCLK2 and the related reference clock signal RCLK2 is 7Γ or less, the preceding clock signal ICLK2 is a signal of the delayed clock signal DCLK2 which is not inverted. The delay compensation circuit 24 is a circuit for compensating the phase shifter 23, that is, the compensation of one point transmission delay time from one output point distance of the delay lock loop 20 to the preceding clock signal ICLK2. If the occurring delay time is when the reference clock signal RCLK2 reaches the phase sensing pump 2 6, the delay compensation circuit 24 compensates the delay time. If the delay lock circuit 20 does not include the delay compensation circuit 24, an asymmetry occurs due to the transmission delay time between a point close to the output point of the delay lock circuit 20 and a point farther from the output point. In any case, if the delay compensation circuit 24 is not included in the delay lock loop, this effect can be achieved according to the present invention. In addition, an output signal of one of the delay compensation circuits 24 may be a feedback signal FCLK2 provided to one of the phase sensing pumps 26. The phase sensing pump 26 senses the phase difference between the reference clock signal RCLK2 and the feedback signal FCLR2. And, the phase sensing pump 2 generates an analog control signal VCON2. The voltage level of the analog control signal VCON2 is controlled by the direction of the phase difference between the feedback signal FCLK2 and the related reference clock signal RCLK2. That is, when the phase of the feedback signal FCLK2 is earlier than the reference clock signal RCLK2, the voltage level of the analog control signal VCON2 changes along the direction of increasing the delay time of the delay circuit 22. In addition, when the phase of the feedback signal FCLK2 is later than the phase of the reference clock signal RCLK2, the voltage level of the analog control signal VCON is reduced in accordance with the delay of the variable delay circuit 22. This paper scale applies to China National Standard (CNS) Α4 Specification (210X 297 mm) ·; Binding
522651 A7 B7 五、發明説明（8 ) 間之方向變化。 最好，相位感測泵26由可變延遲電路22決定之延遲端 子之數目被起動後藉由一信號START來被起動。 相位反轉控制器2 7感測參考時脈信號RCLK2及被延遲之 時脈信號DCLK2間之相位差，選出一相位偏移控制信號 INV及一延遲控制器起動信號BYE。 相位偏移控制信號INV控制相位偏移器2 3。當被延遲之 時脈信號DCLK2與有關之參考時脈信號RCLK2之相位差較 參考之相位值為多時，相位偏移控制器INV被起動。並 且，當被延遲之時脈信號DCLK2與有關之參考時脈信號 RCLK2之相位差較參考之相位值為少時，相位偏移控制信 號INV不被起動。最好參考之相位值為7Γ。 當相位偏移信號INV被起動時，相位偏移器2 3反轉被延 遲之時脈信號DCLK2產生先行之時脈信號ICLK2。 延遲控制起動信號BYE被起動使延遲控制器2 5在其被決 定是否或者不將被延遲之時脈信號DCLK2予以反轉後來起 ' 動。即，是否相位偏移信號是或不被起動。 延遲控制器2 5感測參考時脈信號RCLK2與回饋信號 FCLK2間之相位差，送出一類比起動信號START及記數信 號群QC。 記數信號群QC包括η個信號，即QC[i]，此處i為1至η。 並且，記數信號QC[i]為被起動者，此處i依照參考時脈信 號RCLK2與回饋信號FCLK2間相位差而增加。 在可變延遲電路22中之被起動之延遲端子之數目受記數 -11 - 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐) 522651 A7 ---—____B7__.__ 五、發明説明（9 ) 信號群QC來控制，因之，在可變延遲電路22中之被起動 之延遲端子之數目由參考時脈信號RCLK2與回饋信號 FCLK2間相位差之寬度來決定。 類比起動信號START被起動在可變延遲電路22中被起動 之延遲端子之數目被決定後來起動相位感測泵2 6。 圖3為圖2之一可變延遲電路22之圖解方塊圖。參見圖 3 ’可變延遲電路22包括η個延遲端子3]Li，此處丨為1至 η。並且，由記數信號群QC[n:i]來控制延遲端子之數目。 每一延遲端子31 一i經第一輸入端子D1及第二輸入端子 D 2接收資料’及經輸入端子〇ut輸出資料。當記數信號 QC[i]與被起動之延遲端相符時，延遲端於3丨」經第二輸 入端子按一預先決定之延遲值Td將一輸入信號延遲至輸 出被延遲之值。當相符之信號QC[i]不被起動時，經第一 輸入袖子〇1輸入之信號被延遲一延遲值Td並輸出被延遲 之值。同時，記數信號群QC[n:1]之一信號被起動。 接地電壓Vss送至第一延遲端子31—n之第一輸入端子 D1，及先前之延遲端子之一輸出信號送至次一延遲端子 31 一ι(第一輸入端子D1，此處卜^丨至丨。參考時脈信號 RCLK2送至延遲端子31J之第二輸入端子〇2，此處丨為1 至η 〇 因而，當致能第一延遲端子31_η的記數信號QC[n]被起 動，參考時脈信號RCLK2經延遲端子31—n之第二輸入端子 D2被輸入至由n延遲端子所延遲之輸出信號。結果，最後 延遲端子3U之輸出信號ICLK2自參考時脈信‘rclk2起 -12- 本紙張尺度適用中國國家標準(CNs) A4規格(210 X 297公釐) 522651 五、發明説明（10 ) 受n*Td之延遲。 當致能第一延遲端子3丨一丨的記數信號（^。"被啟動， 參考時脈信號RCK2經延遲端子之第二輸入端子〇2 被輸入至由1延遲端子所延遲之輸出信號。結果，最後延 遲端子31 —1之輸出信號ICLK2相對於參考時脈信號 RCLK2延遲Td的相位差。 按照本發明，可變延遲電路包括n個受記數信號qc控制 之端子，及可變延遲電路22之最後延遲端子3ι ι之輸出 信號為先行之時脈信號1(：1^2。無論如何，可變延遲電路 22在不考慮記數信號qc之起動下可包括—外加之被:動 之端子及延遲端子將參考時脈信號延遲—不同於延遲值 T d之時間期間。 、可變延遲電路22之延遲端子之數目被決定後，類比起動 信號START被起動至高。因而，可變延遲電路^之延遲 端子之數目未變化及相位感測泵2 6被起動。 圖4為圖2之相位反轉控制器27之電路圖。圖5八為圖4 當被延遲之時脈信號DCLK2#有關之參考時脈信號rclk2 之相位差為7Γ或較小時之主端子之時間目，及圖冗為圖4 田被延遲之時脈#號DCLK2有關之參考時脈信號之 相位差為7Γ或較多時之主端子之時間圖。 圖4之正反器45，47，57及59受一起始信號ΙΝΙΤΒ之起 動而被起動。當有一固定之外部電力供應被送入或一内部 運轉模式程式為一同步DRAM即SDRAM情形在完成時， 起始信號INITB被起動。522651 A7 B7 5. Direction of invention (8) changes. Preferably, the number of delay terminals of the phase sensing pump 26 determined by the variable delay circuit 22 is activated by a signal START. The phase inversion controller 27 senses the phase difference between the reference clock signal RCLK2 and the delayed clock signal DCLK2, and selects a phase offset control signal INV and a delay controller start signal BYE. The phase shift control signal INV controls the phase shifter 2 3. When the phase difference between the delayed clock signal DCLK2 and the related reference clock signal RCLK2 is greater than the reference phase value, the phase offset controller INV is activated. Also, when the phase difference between the delayed clock signal DCLK2 and the related reference clock signal RCLK2 is smaller than the reference phase value, the phase offset control signal INV is not activated. The best reference phase value is 7Γ. When the phase shift signal INV is activated, the phase shifter 23 reverses the delayed clock signal DCLK2 and generates the preceding clock signal ICLK2. The delay control start signal BYE is activated to cause the delay controller 25 to start after it is determined whether or not to delay the delayed clock signal DCLK2. That is, whether or not the phase shift signal is activated. The delay controller 25 senses the phase difference between the reference clock signal RCLK2 and the feedback signal FCLK2, and sends an analog start signal START and a count signal group QC. The count signal group QC includes n signals, that is, QC [i], where i is 1 to n. In addition, the count signal QC [i] is the person being activated, where i increases according to the phase difference between the reference clock signal RCLK2 and the feedback signal FCLK2. The number of activated delay terminals in the variable delay circuit 22 is counted -11-This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 522651 A7 ---__ B7 __.__ 5 (9) The signal group QC is used to control. Therefore, the number of activated delay terminals in the variable delay circuit 22 is determined by the width of the phase difference between the reference clock signal RCLK2 and the feedback signal FCLK2. The analog start signal START is activated and the number of delay terminals activated in the variable delay circuit 22 is determined to subsequently start the phase sensing pump 26. FIG. 3 is a schematic block diagram of the variable delay circuit 22 of FIG. 2. Referring to FIG. 3 ', the variable delay circuit 22 includes n delay terminals 3] Li, where 1 to n. The number of delay terminals is controlled by the count signal group QC [n: i]. Each delay terminal 31-i receives data through the first input terminal D1 and the second input terminal D2 and outputs data through the input terminal OUT. When the count signal QC [i] is consistent with the activated delay terminal, the delay terminal is at 3 ″ ″ via the second input terminal to delay an input signal to a value where the output is delayed. When the matching signal QC [i] is not activated, the signal input through the first input sleeve 〇1 is delayed by a delay value Td and the delayed value is output. At the same time, one of the count signal group QC [n: 1] is activated. The ground voltage Vss is sent to the first input terminal D1 of the first delay terminal 31-n, and the output signal of one of the previous delay terminals is sent to the next delay terminal 31-1 (the first input terminal D1, here ^ 丨 to丨 The reference clock signal RCLK2 is sent to the second input terminal 〇2 of the delay terminal 31J, where 丨 is 1 to η 〇 Therefore, when the count signal QC [n] enabling the first delay terminal 31_η is activated, refer to The clock signal RCLK2 is input to the output signal delayed by the n delay terminal via the second input terminal D2 of the delay terminal 31-n. As a result, the output signal ICLK2 of the last delay terminal 3U starts from the reference clock signal 'rclk2-12- This paper size applies the Chinese National Standard (CNs) A4 specification (210 X 297 mm) 522651 V. Description of the invention (10) Delayed by n * Td. When the first delay terminal 3 丨 a 丨 count signal is enabled ( ^. &Quot; Activated, the reference clock signal RCK2 is input to the output signal delayed by the 1 delay terminal via the second input terminal 〇2 of the delay terminal. As a result, the output signal ICLK2 of the delay terminal 31-1 is finally relative to the reference Phase difference of clock signal RCLK2 delayed by Td According to the present invention, the variable delay circuit includes n terminals controlled by the count signal qc, and the output signal of the last delay terminal 3 of the variable delay circuit 22 is the leading clock signal 1 (: 1 ^ 2. No matter How, the variable delay circuit 22 may include without considering the start of the counting signal qc-plus the passive terminal and the delay terminal delay the reference clock signal-a time period different from the delay value T d. After the number of delay terminals of the delay circuit 22 is determined, the analog start signal START is activated to a high level. Therefore, the number of delay terminals of the variable delay circuit ^ remains unchanged and the phase sensing pump 26 is started. The circuit diagram of the phase inversion controller 27. Figure 5-8 is the timing diagram of the main terminal when the phase difference of the reference clock signal rclk2 related to the delayed clock signal DCLK2 # is 7Γ or less, and the figure is redundant Figure 4 is the timing diagram of the main terminal when the phase difference of the reference clock signal related to the clock ## DCLK2 which is delayed is 7Γ or more. The flip-flops 45, 47, 57 and 59 in Figure 4 receive a start The signal INNITB is activated and activated. A fixed external power supply is fed in or an internal operating mode program is a synchronous DRAM, i.e. the SDRAM case. When completed, the start signal INITB is activated.
522651 A7 B7 五、發明説明（11 ) 當被延遲之時脈信號DCLK2與有關之參考時脈信號 RCLK2之相位差θ 1為7Γ或較少時，相位反轉控制器2 7之 運轉將併同參考圖4及5 A加以說明之。 NAND閘極4 9及5 1之N46及N48之輸出信號之起始狀態 為高。相位偏移控制信號IN V之起始狀態為低，及一反轉 器55之一輸出信號N50之起始狀態為高。 當被延遲之時脈信號DCLK2產生正反器45及47之時脈 輸入信號被起動至一邏輯高值時，如圖5A由tl所示參考 時脈信號RCLK2之邏輯狀態為高。然後，在NAND閘極49 之輸出信號N46維持為高，NAND閘極5 1之輸出信號N48 變為低。結果，相位偏移控制信號INV之邏輯狀態如前為 低。反相器55之輸出信號N50至低。起始信號INITB被起 動至低，及然後延遲控制起動信號BYE對延遲第二被起動 之時脈信號DCLK2之第二上升邊緣反應被起動至高。 當延遲之時脈信號DCLK2與有關之參考時脈信號RCLK2 之相位差Θ1為7Γ或較多時，相位反轉控制器27之運轉將 參考圖4及5B加以說明之。 與圖5 A之情況相似，NAND閘極4 9及5 1之N46及N48之 輸出之起始狀態為高。相位偏移控制信號INV之起始狀態 為低，及反相器5 5之一輸出信號N50之起始狀態為高。 當被延遲之時脈信號DCLK2產生正反器45及47之時脈 輸入信號被起動至一邏輯高值時，如圖由5B tl所示，參 考時脈信號RCLK2之邏輯狀態為高。然後，在NAND閘極 4 9 一輸出信號N46變為低。NAND閘極5 1之輸出信號N48 -14- 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐) 522651 A7 B7 五、發明説明（12 ) 保持為高。結果相位偏移控制信號INV被起動至一邏輯高 值。起始信號INITB被起動至低，及被起動之延遲控制器 起動信號BYE對被做為一第二被起動之被延遲之時脈信號 之第二上升邊緣反應至高。 如以上所述，延遲控制器起動信號BYE在相位偏移控制 信號INV之起動被決定後在二時脈皆為邏輯高之一點上被 起動，及起動延遲控制器25 (見圖2)。 當被延遲之時脈信號DCLK2有關之參考時脈信號RCLK2 之相位差為7Γ或較大時，相位偏移器被信號INV被起動， 及當相位差為7Γ以内時維持起動狀態。 圖6為圖2之一延遲控制器25之方塊圖。參見圖2，延遲 控制器2 5包括一偏移控制器6 1及一偏移暫存器6 3。 當延遲控制器致能信號BYE致能偏移控制器6 1。偏移控 制器6 1感測參考時脈信號RCLK2與回饋時脈信號FCLK2 間之相位差，產生一暫存器控制信號RSTB及類比起動信 號START 。 在可變延遲電路22中被起動之延遲端子數目被決定後類 比起動信號START即為用於起動相位感測泵2 6之一起動 信號。此即，當可變延遲電路22 (見圖2)之延遲端子數目 被控制時，類比起動信號START變為高。 暫存器控制信號RSTB，當在所屬相位與回饋信號 FCLK2之滞後於有關之參考時脈信號RCLK2相一致時，轉 變為一邏輯狀態。暫存器控制信號控制偏移暫存器63。 偏移暫存器受暫存器控制信號RSTB被起動，並且，偏 -15- 本纸張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐) 522651522651 A7 B7 V. Description of the invention (11) When the phase difference θ 1 between the delayed clock signal DCLK2 and the related reference clock signal RCLK2 is 7Γ or less, the operation of the phase inversion controller 2 7 will be the same This will be described with reference to Figs. 4 and 5A. The initial state of the output signals of N46 and N48 of NAND gates 49 and 51 is high. The initial state of the phase shift control signal IN V is low, and the initial state of an output signal N50 of an inverter 55 is high. When the delayed clock signal DCLK2 generates the clock input signals of the flip-flops 45 and 47 to a logic high value, the logic state of the reference clock signal RCLK2 is high as shown in FIG. 5A by t1. Then, the output signal N46 of the NAND gate 49 remains high, and the output signal N48 of the NAND gate 51 becomes low. As a result, the logic state of the phase shift control signal INV is low as before. The output signal N50 of the inverter 55 is low. The start signal INITB is activated low, and then the delay control activation signal BYE is activated high to delay the second rising edge of the second activated clock signal DCLK2. When the phase difference Θ1 between the delayed clock signal DCLK2 and the related reference clock signal RCLK2 is 7? Or more, the operation of the phase inversion controller 27 will be described with reference to Figs. 4 and 5B. Similar to the situation in FIG. 5A, the initial states of the outputs of N46 and N48 of the NAND gates 49 and 51 are high. The initial state of the phase shift control signal INV is low, and the initial state of an output signal N50 of one of the inverters 55 is high. When the delayed clock signal DCLK2 generates the clock input signals of the flip-flops 45 and 47 to a logic high value, as shown by 5B tl, the logic state of the reference clock signal RCLK2 is high. Then, an output signal N46 goes low at the NAND gate 4 9. Output signal of NAND gate 5 1 N48 -14- This paper size is in accordance with Chinese National Standard (CNS) A4 specification (210 X 297 mm) 522651 A7 B7 V. Description of invention (12) Keep high. As a result, the phase shift control signal INV is activated to a logic high value. The start signal INITB is activated low and the activated delay controller The activation signal BYE responds high to the second rising edge of the delayed clock signal which is treated as a second activated. As described above, the delay controller start signal BYE is started at a point where both clocks are logic high after the start of the phase offset control signal INV is determined, and the delay controller 25 is started (see Fig. 2). When the phase difference of the reference clock signal RCLK2 related to the delayed clock signal DCLK2 is 7Γ or larger, the phase shifter is activated by the signal INV, and the startup state is maintained when the phase difference is within 7Γ. FIG. 6 is a block diagram of the delay controller 25 of FIG. 2. Referring to Fig. 2, the delay controller 25 includes an offset controller 61 and an offset register 63. When the delay controller enable signal BYE enables the offset controller 6 1. The offset controller 61 senses the phase difference between the reference clock signal RCLK2 and the feedback clock signal FCLK2, and generates a register control signal RSTB and an analog start signal START. After the number of delay terminals to be started in the variable delay circuit 22 is determined, the analog start signal START is one of the start signals for starting the phase sensing pump 26. That is, when the number of delay terminals of the variable delay circuit 22 (see Fig. 2) is controlled, the analog start signal START becomes high. The register control signal RSTB turns into a logic state when the phase of the register control signal RSTB coincides with that of the feedback signal FCLK2 lagging with the relevant reference clock signal RCLK2. The register control signal controls the offset register 63. The offset register is activated by the register control signal RSTB, and the offset -15- This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 522651
移暫存器接收回饋信號FCLK2來產生一具有η個信號之記 數信號群QC[n:l]。記數信號群(^(::^:^為^個信號之一起 動中之信號。並且，每當在暫存器控制信號RTSB為高之 期間中回饋信號FCLK2被起動時，記數信號群QC[n:i]起 動一信號來將可變延遲電路22之延遲單元31之延遲端子 數目增加（見圖2 )。 圖7為圖6之偏移控制器61之一電路圖。圖8為關於圖7 主信號之時間圖。在圖8之丁1期間中，回饋信號FCLK2之 相位領先於參考時脈信號RCLK2。並且，圖8之τ 2期間 中，回饋信號FCLK2之相位落後於參考時脈信。 偏移控制器6 1將參照圖7及8予以說明之。 偏移控制器6 1包括二個正反器7 1及7 3及鎖定器7 7。正 反器7 1及7 3及鎖定器7 7受延遲控制器起動信號bye被起 動。 鎖定器77之一輸出信號N80之起始狀態為高，及類比起 動仏號START之起始狀態為低。暫存器控制信號RSTB之 起始狀態為高。 圖8之期間T 1中偏移控制器6 1之運轉，其中回饋時脈信 號FCLK2之相位引前於參考時脈信號RCLK2，將說明如 下。 在期間T1中，當回饋信號FCLK2為一時脈輸入至正反器 7 1之信號，被起動時，參考時脈信號RCLK2則為送至正 反器71為低之資料輸入信號。結果，正反器？！之一輸出 化號N72保持一邏輯位址，正反器73之輸出信號N74在回 -16- 本紙張尺度適用中國國家標準(CNS) A4規格(210X297公釐) 522651 五、發明説明（14 饋#號FCLK2被起動之一點上變為高。 無論如何，由NAND閘極75來之—輸出信號N76保持於 邏，高。因之，由鎖定器77來之輸出信號N8〇保持在一邏 輯同值。並且，在起動狀態，類比起動信號灯八尺丁及暫存 器控制彳§號RSTB分別保持於低及高值。 因而，在期間τι中，相位感測泵26 (見圖2)不被起 動，及偏移暫存器63 (見圖6)被起動，來控制可變延遲電 路22 (見圖2)之延遲端子之數目。 結果，在圖8之期間T2中偏移控制器61之運轉，其中回 饋信號FCLK2之相位落後於參考時脈信號以⑴，將說明 如下。 在點t2起動中之回饋信號FCLK2為一送至正反器”之時 脈1口號參考時脈仏號RCLK2為一正反器71之資料輸入 仏號其邏輯狀態為高。由正反器71來之輸出信號N72走向 邏輯高。 因而，NAND閘極7 5之輸出信號N76走至邏輯低，及鎖 足器77之輸出仏號N80走至低。類比起動信號START走至 同，使得相位感測泵2 ό (見圖2 )被起動。暫存器控制信號 RSTB走向低，使得偏移暫存器63 (見圖㈠被起動。 圖9為圖2之相位偏移器23之電路圖。參見圖2，相位偏 移器23包括第一至第三邏輯閘極91，93及95。 第一邏輯閘極9 1，當相位偏移控制信號INV不被起動 時，反轉被延遲之時脈信號]3€^尺2及輸出被反轉之信號。 第一邏輯閘極9 3 ’當相位偏移控制信號ΙΝν被起動時反 522651 A7 B7 五、發明説明（15 ) 轉被延遲之時脈信號DCLK2之被反轉之信號及輸出被反轉 之信號。 第三邏輯閘極9 5對第一邏輯閘極9 1之輸出信號N93及第 二邏輯閘極9 3之輸出信號N94做NAND操作及輸出一所屬 之輸出信號。 按照所選之具體實施例，第三邏輯閘極9 5之輸出信號被 接至先行之時脈信號ICLK2。 先行之時脈信號，當相位偏移控制信號INV不被起動 時，具有如被延遲之時脈信號DCLK2之相同之相位。當相 位偏移控制信號INV被起動時，先行之時脈信號ICLK2與 被延遲之時脈信號DCLK2之反轉信號有相同之相位。 參見圖2，延遲鎖定迴路20之運轉步驟如下。 被延遲之時脈信號DCLK2與有關之參考時脈信號RCLK2 之相位差被感測，因此，決定被延遲之時脈信號DCLK2是 否反轉。 當被延遲之時脈信號DCLK2之反轉被決定時，可變延遲 電路22之延遲端子之數目被決定。 可變延遲電路22中延遲端子之數目被決定後，由相位感 測泵2 6來之類比控制信號VCON2輸出，按照可變延遲電 被類比控制而延遲時間。 在規範中，用於一延遲相位鎖定迴路之具體實施例已予 以說明。無論如何，本發明可使用用於產生對一參考時脈 信號同步之一先行之時脈信號之所有的鎖定迴路上。 並且，在規範中，經延遲補償電路24，被轉送至延遲控 -18- 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐) 522651 A7 B7 五、發明説明（16 ) 制器2 0及相位感測泵2 6，再由相位偏移器2 3輸出先行之 時脈信號ICLK2，但亦可直接轉送至延遲控制器2 5及相位 感測泵2 6。 在圖面及規範中，本發明所選之具體例已予以揭示及且 僅為說明，這些使用僅為一般及說明性之意而非限制之目 的，發明之範圍如陳述如下之申請專利範圍。 -19 - 本紙張尺度適用中國國家標準(CNS) A4規格(210X297公釐)The shift register receives the feedback signal FCLK2 to generate a count signal group QC [n: l] with n signals. Counting signal group (^ (:: ^: ^ is one of the ^ signals being activated. And, whenever the feedback signal FCLK2 is activated during the period when the register control signal RTSB is high, the counting signal group QC [n: i] activates a signal to increase the number of delay terminals of the delay unit 31 of the variable delay circuit 22 (see FIG. 2). FIG. 7 is a circuit diagram of an offset controller 61 of FIG. 6. Figure 7 Time chart of the main signal. In the period of D1 in Figure 8, the phase of the feedback signal FCLK2 is ahead of the reference clock signal RCLK2. In the period of τ2 in Figure 8, the phase of the feedback signal FCLK2 is behind the reference clock. The offset controller 61 will be described with reference to Figs. 7 and 8. The offset controller 61 includes two flip-flops 7 1 and 7 3 and a latch 7 7. The flip-flops 7 1 and 7 3 and The latch 7 is activated by the delay controller start signal bye. One of the latches 77 has a high initial state of the output signal N80, and the initial state of the analog start signal START is low. Starting from the register control signal RSTB The initial state is high. During the period T 1 in FIG. 8, the operation of the offset controller 61 is performed, in which the phase of the feedback clock signal FCLK2 is induced. The reference clock signal RCLK2 will be described as follows. In the period T1, when the feedback signal FCLK2 is a clock input to the flip-flop 71, when it is activated, the reference clock signal RCLK2 is sent to the flip-flop 71. Input the signal for the low data. As a result, one of the flip-flops N72 keeps a logical address, and the output signal N74 of the flip-flop 73 is back to -16- This paper standard applies to China National Standard (CNS) A4 Specifications (210X297mm) 522651 V. Description of the invention (14 FCLK2 becomes high at one point when it is activated. In any case, it comes from the NAND gate 75-the output signal N76 is kept at logic high. Therefore, by The output signal N80 from the latch 77 is maintained at a logical value. Also, in the starting state, the analog start signal eight feet and the register control 彳 § number RSTB are kept at low and high values, respectively. Therefore, during the period In τι, the phase sensing pump 26 (see FIG. 2) is not activated, and the offset register 63 (see FIG. 6) is activated to control the number of delay terminals of the variable delay circuit 22 (see FIG. 2). As a result, the operation of the offset controller 61 during the period T2 in FIG. 8, where The phase of the feedback signal FCLK2 lags behind the reference clock signal, which will be explained as follows. The feedback signal FCLK2 at the start of point t2 is one sent to the flip-flop. The data input signal of the device 71 has a logic state of high. The output signal N72 from the flip-flop 71 goes to logic high. Therefore, the output signal N76 of the NAND gate 75 goes to logic low and the output of the foot lock 77 No. N80 goes low. The analog start signal START goes to the same, so that the phase sensing pump 2 (see Figure 2) is started. The register control signal RSTB goes low, so that the offset register 63 (see Fig. ㈠) is activated. Fig. 9 is a circuit diagram of the phase shifter 23 of Fig. 2. Referring to Fig. 2, the phase shifter 23 includes first to The third logic gate 91, 93, and 95. The first logic gate 9 1. The clock signal is delayed when the phase shift control signal INV is not activated. The first logic gate 9 3 'is inverted when the phase shift control signal INV is activated. 522651 A7 B7 V. Description of the invention (15) The inverted signal and output of the clock signal DCLK2 whose rotation is delayed are inverted. The third logic gate 95 performs a NAND operation on the output signal N93 of the first logic gate 91 and the output signal N94 of the second logic gate 93 and outputs an associated output signal. In a specific embodiment, the output signal of the third logic gate 95 is connected to the preceding clock signal ICLK2. The preceding clock signal has a delayed clock signal when the phase offset control signal INV is not activated. The same phase of DCLK2. When the phase shift control signal INV is activated, first The clock signal ICLK2 has the same phase as the inverted signal of the delayed clock signal DCLK2. See Figure 2. The operation steps of the delay lock loop 20 are as follows. The delayed clock signal DCLK2 and the related reference clock signal The phase difference of RCLK2 is sensed, so it is determined whether the delayed clock signal DCLK2 is inverted. When the delayed clock signal DCLK2 is inverted, the number of delay terminals of the variable delay circuit 22 is determined. After the number of delay terminals in the variable delay circuit 22 is determined, the analog control signal VCON2 from the phase sensing pump 26 is output, and the delay time is controlled by analog according to the variable delay. In the specification, it is used for a delay phase Specific embodiments of the lock loop have been described. In any case, the present invention can be used on all lock loops for generating a preceding clock signal synchronized to a reference clock signal. And, in the specification, delay compensation is used Circuit 24, transferred to delay control -18- This paper size applies Chinese National Standard (CNS) A4 specification (210 X 297 mm) 522651 A7 B7 V. Description of invention (16) 2 0 and the phase sensing pump 26, and then the phase shifter 23 outputs the leading clock signal ICLK2, but it can also be directly transferred to the delay controller 25 and the phase sensing pump 26. In the drawing and specifications In the present invention, the specific examples selected have been disclosed and are for illustration only. These uses are for general and illustrative purposes rather than limiting purposes. The scope of the invention is as stated in the scope of patent application. -19-This paper Standards apply to China National Standard (CNS) A4 specifications (210X297 mm)