TW522515B - Redistribution process - Google Patents

Redistribution process Download PDF

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Publication number
TW522515B
TW522515B TW091100099A TW91100099A TW522515B TW 522515 B TW522515 B TW 522515B TW 091100099 A TW091100099 A TW 091100099A TW 91100099 A TW91100099 A TW 91100099A TW 522515 B TW522515 B TW 522515B
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TW
Taiwan
Prior art keywords
layer
patterned
copper
titanium
copper layer
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Application number
TW091100099A
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English (en)
Inventor
Jau-Fu Weng
Original Assignee
Advanced Semiconductor Eng
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Publication date
Application filed by Advanced Semiconductor Eng filed Critical Advanced Semiconductor Eng
Priority to TW091100099A priority Critical patent/TW522515B/zh
Priority to US10/248,293 priority patent/US6867122B2/en
Application granted granted Critical
Publication of TW522515B publication Critical patent/TW522515B/zh

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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
    • H01L21/2885—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition using an external electrical current, i.e. electro-deposition
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經濟部中夬標準局員工消費合作社印裝 522515 8089twf.doc/0l2 A7 __ B7 五、發明説明（/ ) 本發明是有關於一種重配置製程，且特別是有關於一 種以苯環丁烯爲介電層之重配置製程。 所謂的重配置（redisUibution)製程，其主要是在晶圓 的輸入輸出接點（通常是金屬銲墊）之上，利用一重配置線 路層，重新配置出新的輸入輸出接點。其常見於覆晶技術 (flip chip)中，用以將原外周分布型的銲墊，重配置爲面積 分布的形態。並於重配置之後的輸入輸出接點之上形成凸 塊，作爲對外的連接。此輸入輸出接點除了上述的凸塊以 外，亦可以是銲墊。 習知在進行重配置製程時，常使用的線路材質爲銅 材，而常使用的介電層有聚亞醯胺、苯環丁烯等絕緣材料。 然而，當使用苯環丁烯爲介電層時，因苯環丁烯和銅的接 合性不佳，故當於銅線路層上形成苯環丁烯層時，極易在 苯環丁烯的顯影過程中，使苯環丁烯呈片狀脫落，造成製 程不良。 習知的重配置製程詳如下述，請依序參考第1圖〜第 7圖，其繪示習知的晶圓重配置製程流程側視剖視圖。 如第1圖，首先，提供一晶圓1〇〇，具有多個銲墊102 及一保護層104覆於銲墊102之表面，並暴露出銲墊102。 依序於晶圓100之表面形成一'欽層106、一*銅層108。如 第2圖，形成一圖案化光阻層112覆蓋於鈦層106之表面， 此圖案化光阻層112具有多個開口 112a，暴露出部分之銅 層108，之後於暴露出的銅層108之表面電鑛一銅層109。 如第3圖，蝕刻去除圖案化光阻層1 12，並以銅層109 3 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐〉 (請先閲讀背面之注意事項再填寫本頁)
522515 五、發明説明（〕） 爲罩幕，融刻去除部分之銅層108及鈦層106，以形成一 圖案化線路層150。如第4圖，形成一圖案化苯環丁烯層 114。此圖案化苯環丁烯層114具有多個開口 114a，暴露 出銅層109。並形成一銅層116覆蓋於圖案化苯環丁烯層 Π4之表面，並覆蓋於暴露出之銅層109之表面。 如第5圖，形成一圖案化光阻層118於銅層116之表 面。此圖案化光阻層118具有多個開口 118a，暴露出部分 之銅層116。利用電鍍之方法，依序電鍍一銅層120及一 錫鉛銲料層122於暴露出的銅層116之表面。如第6圖， 蝕刻去除圖案化光阻層118,並以錫鉛銲料層122爲罩幕， 去除銅層116。最後，如第7圖，進行一回焊步驟，將錫 鉛銲料層122的圖案形成凸塊122a。 如上所述，當習知使用苯環丁烯作爲介電層時，因苯 環丁烯和銅的接合性不佳，故在第4圖的步驟中，當欲於 圖案化線路層150上形成圖案化苯環丁烯層114時，便極 易在圖案化苯環丁烯層114之顯影過程中，使圖案化苯環 丁烯層114呈片狀脫落，造成製程不良。 經濟部中央標準局貝工消費合作社印裝 (請先閲讀背面之注意事項再填寫本頁) 本發明的目的係，提出一種重配置製程，其形成之圖 案化線路層和苯環丁烯之接合性較習知爲佳，故當以苯環 丁烯作爲介電層，不會在顯影過程中呈片狀脫落，而能維 持製程之良率。 爲解決習知的問題點，及達成本發明上述及其他目 的，本發明提出一種重配置製程，包括以下製程。提供一 晶圓，於晶圓之表面依序形成一第一鈦層、一第一銅層及 本紙張尺度適用中國國家標隼（CNS ) A4規格（210X297公釐） 522515 8' 0 8 9 τ: w f . d 〇 c / 0 1 2 A7 B7 經濟部中央標準局貝工消費合作社印策 五、發明説明（^ ) 一第二鈦層。之後，定義第二鈦層、第一銅層及第一鈦層， 以形成一圖案化線路層。形成一圖案化苯環丁烯層，以暴 露出第二鈦層。接著，去除暴露出之第二鈦層，以暴露出 第一銅層。再形成多個輸入輸出接點，覆於圖案化苯環丁 烯層之上，與暴露出之第一銅相連接。其中，晶圓具有多 個銲墊，且，每一輸入輸出接點係藉由圖案化線路層，分 別與每一銲墊相連接。 依照本發明的特徵，圖案化線路層係由第一鈦層、 第一銅層及第二鈦層所組成。是故，在形成介電層之圖案 化苯環丁烯層時，係由第二鈦層和圖案化苯環丁烯層相接 合。又由於鈦金屬和苯環丁烯間之接合性較銅金屬與苯環 丁烯之接合性較佳。所以，本發明之圖案化線路層和圖案 化苯環丁烯層能維持優於習知的接合性，而提高製程良 率。 依照本發明的特徵，在形成圖案化苯環丁烯層之後， 更去除部分之第二鈦層，以暴露出部分之第一銅層，並使 第二銅層和圖案化線路層之第一銅層相連接。除了兼顧到 鈦和苯環丁烯的接合性之外，更可維持線路間良好的電性 連接。 爲讓本發明之上述和其他目的、特徵、和優點能更 明顯易懂，下文特舉一較佳實施例’並配合所附圖式，作 詳細說明如下： 本紙張尺度適用中國國家標隼（CNS ) A4規格（210X297公釐） UAW— (请先閲讀背面之注意事項再填寫本頁) -訂 經濟部中央榇準局貝工消費合作社印裝 522515 8089twf.doc/012 A7 A / -- B7 五、發明説明（A ) 圖式之簡單胃兌明 第1圖〜第7圖繪示習知的晶圓重配置製程流程側視 剖視圖； 第8圖〜第20圖繪示依照本發明較佳實施例之一種 晶圓重配置製程流程側視剖視圖。 圖式標號之簡蚩說明 100、200 ··晶圓 102、202 :銲墊 104、204 ··保護層 106 :鈦層 108、109、116、120 :銅層 112、118、212、218 :圖案化光阻層 112a、114a、118a、212a、214a、218a :開口 114、214 :圖案化苯環丁烯層 122 :錫鉛銲料層 122a、222a :凸塊 150、250 :圖案化線路層 206:第一鈦層 208:第一銅層 210:第二鈦層 216··第二銅層 220 :銅層圖案 222 ··銲料層圖案 260 :輸入輸出接點 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） — (請先閲讀背面之注意事項再填寫本頁) 訂 522515 S089twf.doc/012 Β7 五、發明説明（I ) 較佳實施例 請參考第8圖〜第20圖，其繪示依照本發明較佳實施 例之一種重配置製程流程側視剖視圖。 如第8圖，提供一晶圓200，具有多個銲墊202及一 保護層204覆蓋於晶圓200之表面並暴露出銲墊202。並 於晶圓200之表面依序形成一*第一欽層206、一'第一銅層 208及一第二鈦層210。其中，保護層204之材質包括二 氧化矽或氮化砂等。 如第11圖，定義第二鈦層210、第一銅層208及第 一鈦層206，以形成一圖案化線路層250。此圖案化線圖 路層250係與每一銲墊202相連接，並暴露出保護層204。 其中，定義第二鈦層210、第一銅層208及第一鈦層206 之方法詳如第9圖〜第11圖所述。 經濟部中央標準局貝工消費合作社印裝 (請先閲讀背面之注意事項再填寫本頁) 如第9圖，以微影之方法，形成一圖案化光阻層212， 覆於第二鈦層210之表面。此圖案化光阻層212具有多個 第二開口 212a，且第二開口 212a暴露出第二鈦層210。 如第10圖，蝕刻去除暴露出之第二鈦層210、第一銅層208 及第一鈦層206。接著，如第11圖所示，去除該圖案化光 阻層212。 如第12圖，採用一感光型之苯環丁烯，以微影之方 法，形成一圖案化苯環丁烯層214，覆蓋於圖案化線路層 250之表面。其中，圖案化苯環丁烯層214具有多個第一 開口 214a，暴露出第二鈦層210。如第Π圖，蝕刻去除 暴露出之第二鈦層210，以暴露出第一銅層208。 7 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 522515 8089twf.doc/012 Β7 五、發明説明（t) 最後，如第20圖，形成多個輸入輸出接點260，覆 於圖案化苯環丁烯層214之上，與暴露出之第一銅層208 相連接。且每一輸入輸出接點260係藉由圖案化線路層 250，分別與每一銲墊2〇2相連接。此輸入輸出接點可以 是銲墊、凸塊，在此實施例中，係以凸塊222a爲例作一 說明。形成凸塊212a之方法詳如第14圖〜第20圖所述。 如第I4圖，形成一第二銅層216覆於圖案化苯環丁 烯層214之表面。如第15圖，以微影之方法，形成一圖 案化光阻層218覆於第二銅層216之表面。且圖案化光阻 層218具有多個第三開口 218a，暴露出第二銅層216。如 第16圖，電鍍一銅材於暴露出之第二銅層216的表面， 以形成多個銅層圖案220。 經濟部中央標準局員工消費合作社印製 --------參！ (請先閲讀背面之注意事項再填寫本頁) 如第17圖，利用電鍍或印刷塡入之方法，將一銲料 塡入第三開口 218a中，並覆於銅層圖案220的表面，以 形成多個銲料層圖案2U。接著，如第18圖，去除圖案化 光阻層218。如第19圖，以蝕刻之方法，並以銲料層圖案 222爲罩幕，去除未受銅層圖案220覆蓋而暴露出之第二 銅層208。最後，如第20圖，進行一回焊步驟，以使每一 銲料層圖案222形成一凸塊222a。 依照本發明的特徵，在形成介電層之圖案化苯環丁 烯層214之前，先由第一鈦層206、第一銅層208及第二 鈦層210形成圖案化線路層250。是故，在形成介電層之 圖案化苯環丁烯層214時，係由第二鈦層210和圖案化苯 環丁烯層214相接合。又由於鈦金屬和苯環丁烯間之接合 8 本紙張尺度適用中國國家標準（CNS ) Α4規格（210Χ297公釐） 522515 8〇89twf(>d〇c/〇12 A7 B7 ^____ 經濟部中失梂準局貝工消費合作社印裝 發明説明（^) 性較銅金屬與苯環丁烯之接合性較佳。所以，本發明之圖 案化線路層250和圖案化苯環丁烯層214能維持優於習知 的接合性，而提高製程良率。 依照本發明的特徵，在形成圖案化苯環丁烯層2H 之後’更去除部分之第二鈦層210，以暴露出部分之第一 銅層208，並使第二銅層216和圖案化線路層250之第一 銅層208相連接，除了兼顧到鈦和苯環丁烯的接合性之外， 更可維持線路間良好的電性連接（因銅的導電性佳）。 依照上述本發明之實施例可知，本發明至少具有下列 優點： (1) .本發明之重配置製程，在形成圖案化苯環丁烯層之前， 先形成一第二鈦層，是故，在形成介電層之圖案化苯 環丁烯層時，係由第二鈦層和圖案化苯環丁烯層相接 合。因此，本發明之圖案化線路層和圖案化苯環丁烯 層能維持優於習知的接合性，而提高製程良率。 (2) 本發明之重配置製程，在形成圖案化苯環丁烯層之後， 更去除部分之第一欽層’以暴露出部分之第一^銅層， 並使第二銅層和圖案化線路層之第一銅層相連接。除 了兼顧到鈦和苯環丁嫌的接合性之外，更可維持良好 的線路導電性。 雖然本發明已以一較佳實施例揭露如上，然其並非用 以限定本發明，任何熟習此技藝者，在不脫離本發明之精 神和範圍內，當可作些許之更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者爲準。 9 I-—------0------tr------争 (請先閲讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標隼（CNS ) A4規格（210X297公釐）

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  1. 522515 8089twf.doc/012 gg C8 D8 、申請專利乾圍 1. 一種重配置製程，包括： 提供一晶圓，具有複數個銲墊及一保護層覆蓋於該晶 圓之表面並暴露出該些銲墊； 於該晶圓之表面依序形成一第一鈦層、一第一銅層及 一第二鈦層； 定義該第二鈦層、該第一銅層及該第一鈦層，以形成 一圖案化線路層，與每一該些銲墊相連接，並暴露出該保 護層； 形成一圖案化苯環丁烯層，覆蓋於該圖案化線路層之 表面，該圖案化苯環丁烯層具有複數個第一開口，該些第 一開口暴露出該第二鈦層； 去除暴露出之該第二鈦層，以暴露出該第一銅層； 形成複數個輸入輸出接點，覆於該圖案化苯環丁烯層 之上，與暴露出之該第一銅層相連接，其中，每一該些輸 入輸出接點係藉由該圖案化線路層，分別與每一該些銲墊 相連接。 2. 如申請專利範圍第1所述之重配置製程，其中，該 保護層之材質包括二氧化矽。 經濟部中央標準局員工消費合作社印製 (請先閲讀背面之注意事項再填寫本頁) 3. 如申請專利範圍第1所述之重配置製程，其中，該 保護層之材質包括氮化矽。 4. 如申請專利範圍第1所述之重配置製程，其中，形 成該圖案化苯環丁烯層之方法包括微影。 5. 如申請專利範圍第1所述之重配置製程，其中，定 義該第二鈦層、該第一銅層及該第一鈦層之方法，包括： 10 本紙張尺度適用中國國家標準（CNS〉A4規格（210X297公釐） 522515 8089twf.doc/012 gg C8 D8 六、申請專利範圍 形成一圖案化光阻層，覆於該第二鈦層之表面，其中， 該圖案化光阻層具有複數個第二開口，該些第二開口暴露 出該第二鈦層； 去除暴露出之該第二鈦層、該第一銅層及該第一鈦層； 以及 去除該圖案化光阻層。 6. 如申請專利範圍第5所述之重配置製程，其中形成 該圖案化光阻層之方法包括微影。 7. 如申請專利範圍第1所述之重配置製程，其中，該 些輸入輸出接點包括凸塊，且形成該些凸塊之方法，包括: 形成一第二銅層覆於該圖案化苯環丁烯層之表面； 形成一圖案化光阻層覆於該第二銅層之表面，其中， 該圖案化光阻層具有複數第三開口，該些第三開口係分別 暴露出該第二銅層； 電镀一銅材於暴露出之該第二銅層的表面，以形成複 數個銅層圖案； 將一銲料塡入該些第三開口中，並覆於該些銅層圖案 的表面，以形成複數個銲料層圖案，； 去除該圖案化光阻層； 經濟部中央標準局員工消費合作社印製 (請先閲讀背面之注意事項再填寫本頁) 去除未受該些銅層圖案覆蓋而暴露出之該第二銅層; 以及 進行一回焊步驟，以使每一該些銲料層圖案形成一凸 塊。 8. 如申請專利範圍第7所述之重配置製程，其中，塡 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 522515
    六、申請專利範圍 入該銲料之方法，包括電鑛。 9·如申請專利範圍第7所述之重配置製程，其中，塡 入該銲料之方法，包括印刷塡入。 1〇_如申請專利範圍第7項所述之重配置製程，其中， 形成該圖案化光阻層之方法包括微影。 (請先閲讀背面之注意事項再填寫本頁) 訂 經濟部中央標準局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS〉A4規格（21〇X297公慶〉
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US8749011B2 (en) * 2005-02-28 2014-06-10 Broadcom Corporation System and method for reducing voltage drops in integrated circuits
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US7872347B2 (en) * 2007-08-09 2011-01-18 Broadcom Corporation Larger than die size wafer-level redistribution packaging process
US7667335B2 (en) * 2007-09-20 2010-02-23 Stats Chippac, Ltd. Semiconductor package with passivation island for reducing stress on solder bumps
US8643164B2 (en) * 2009-06-11 2014-02-04 Broadcom Corporation Package-on-package technology for fan-out wafer-level packaging
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