A7 531861 五、發明說明（1 ) 【發明領域】： 本發明係有關於一種半導體封裝件及其製法，尤扑一 種具有偽導腳（Dummy Lead)之膠片載具式半導體封裝件 (Tape Carrier Package, TCP)及其製法。 【發明背景】： 踢片載具式半導體封裝技術（Tape Carrier paekaging， TCP )為一種改良式半導體封裝技術，其特點係利用一具 有置晶穴之膠片載具（Tape Carrier)取代傳統導線架或基 板來作為安置半導體晶片之基底，並透過膠片自動銲結^ 程（Tape Automated Bonding，TAB )於連續膠片列上成批 操作來進行封裝製程。惟每一膠片載具中央部皆設有一置 晶穴，且該置晶穴外圍各側邊皆預設有複數個導腳銲結區 域，遂待半導體晶片植入該置晶穴後，可執行導腳銲結步 驟（Inner Lead Bonding，ILB )將該晶片藉多數導腳電性導 接至外部電路上。 第5圖係為習知膠片載具式半導體封裝件之上視示音 圖，如圖所示，該半導體封裝件2具有一内設置晶穴2〇1 之膠片載具20，其中，於該置晶穴200内係置有一半導體 曰曰片23，該晶片23具有一電路表面（未圖示），且該電路 表面上各侧邊皆設有複數個輸出入銲墊27以供多數錫銲 凸塊（未圖示）植接導電之用。惟晶片角端部位（如圖中 虛線圈所示部分）常因銲線位置受限無法配置銲墊致使該 晶片角端部位無法獲得導腳支撐，因此，置晶穴2〇〇侧邊 一之導腳銲結區域2〇1内的多數功能性導腳21於銲結過程中 ‘紙張尺度適國家標準（CNS)心規格⑽χ视公复）------— 16493 , 卜— I』^ (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 一-JJ、« n n ·ϋ I ϋ m I i— ί ϋ 1^1 II ϋ I- — i l n I i n i n -I I I ϋ n n I ϋ - 1 531861 經濟部智慧財產局員工消費合作社印製 A7 五、發明說明（2 , 極易受應力破壞產生斷裂或扭曲，甚至婷接後施以膠體封 裝製程時’更易因為角端處空隙…遠大於相鄰導腳間隔p (Leadmg SPace )而引發樹脂充填不均造成溢穋 (deeding)產生’使產品之品質信賴性大幅降低。 有鑑於此，美國專利第5,925 926冑、美國專利第 5,25M42號提出—種增強晶U端應力承受能力之半導 體裝置。如第6A及6B圖所示’是種改良式封裝件3亦具 有-膠片載具30及一安置於該膠片載具％上之半導體晶 片33’然較傳統封裝件進步者在於該封裝結構3之半導體 晶片 33各角端部位^j-、 （未圖不）上額外形成多數金質銲塊 34 ( Gold Bump )，並藉一她和· 〜业稽知#結於膠片載具30角落位置 之複數個支撐元件32 (如铜飧μ、人 、如銅泊片）令該等銲塊34與支撐 元件32間穩固銲結而能維牲 月匕维待功能性導腳3 1之結構完整 性。 惟上述製法須先於該曰y 兀、忑曰日片33電路表面330上增設多 個未具電性傳遞功能$後# # 此之偽鲜墊38，方可施加銲料形成多數 金質婷塊34。若遇晶片雷软, 乃罨路佈局（Layout)無法變更或製 作晶片時未於角端部位特別 此付圳女置偽知墊等情況下，缺乏偽 銲墊之半導體晶片將盔法楹 …、凌徒供金質釦塊植設而難與偽導腳 接合’使得晶片角端部位欠 议人缺克撺而導致功能性導腳摧 折，甚至引發傳輸中斷或雜訊產生。 【發明概述】： 本發月之主要目的係提供一種無須增加封裝成本，即 能按實際製程需要於半導靜曰 -----一干等體阳片上另增多數補強銲塊，# l· . 0------- —訂---------線丨* (請先閱讀背面之注意事項再填寫本頁) 2 16493 經濟部智慧財產局員工消費合作社印製 ^31861 B7 五、發明說明（3 ) 阳片可藉其與支撐元件（如爲導 腳等）形成穩固銲結，以 裝能導腳之結構完整性之膠片載具式半導體封 本發明之再一目的係提供一種 e 裡惶需運用現有技術即 ； 曰曰片上增設補強銲塊，進而提昇晶片與支撐元 件間之接合強度’使功能性導腳不致受應力破壞而能增進 產时良率之膠片載具式半導體封裝件及其製法。 鑒於上述及其他目的，本發明之半導體封裝件製法係 包含以下步驟：先備一膠片載具，其中央處具有一置晶穴， 且該置晶穴各側邊及角落部位上已預先形成有多條功能性 導腳以及偽導腳；而後，另取一半導體晶片，該晶片具有 表面，、上並具有一絕緣保護層，於該絕緣保護層 表面濺鍍上金屬沉積層以及光阻覆蓋、曝光、顯影、蚀刻 等技術俾开> 成一個以上之補強銲塊，致使晶片對位壓接到 置晶穴後得藉該等補強銲塊與偽導腳間形成強固銲結。 本發明製法不同於傳統銲塊仰賴鮮墊固結到晶片的 方法，而係直接於晶片電路面之絕緣保護層上形成補強銲 塊，藉以改善半導體晶片上未具偽銲墊或偽銲墊佈設數量 不足之缺失，使膠片載具角落部位安置之多數支撐元件（如 偽導腳）可透過該等補強銲塊與該晶片形成穩固銲結，藉 以增強晶片角端位置之應力耐受性，使功能性導腳於後續 製程之溫度循環下不致受熱應力破壞而能大幅減少傳輸中 斷或雜訊之發生。 【圖式簡單說明】： 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）A7 531861 V. Description of the invention (1) [Field of invention]: The present invention relates to a semiconductor package and a method for manufacturing the same, and particularly to a film carrier semiconductor package (Dummy Lead) with a dummy lead. , TCP) and its manufacturing method. [Background of the Invention]: Tape carrier semiconductor packaging technology (Tape Carrier paekaging, TCP) is an improved semiconductor packaging technology, which is characterized by the use of a film carrier (Tape Carrier) with a cavity instead of a traditional lead frame or The substrate is used as a substrate on which the semiconductor wafer is placed, and the packaging process is performed in a batch operation on a continuous film row through a tape automatic bonding process (Tape Automated Bonding, TAB). However, each film carrier is provided with a cavity in the center, and a plurality of guide pin bonding areas are preset on each side of the periphery of the cavity. After the semiconductor wafer is implanted in the cavity, it can be executed. A lead bonding step (Inner Lead Bonding, ILB) electrically connects the chip to an external circuit by a majority of the lead pins. FIG. 5 is a top view of a conventional film carrier-type semiconductor package. As shown in the figure, the semiconductor package 2 has a film carrier 20 with a cavity 2101 therein. A semiconductor chip 23 is arranged in the cavity 200. The wafer 23 has a circuit surface (not shown), and each side of the circuit surface is provided with a plurality of input / output pads 27 for most soldering. The bumps (not shown) are implanted to conduct electricity. However, the corner portion of the wafer (as shown by the virtual circle in the figure) often cannot be equipped with pads due to the limited position of the bonding wire, so that the corner portion of the wafer cannot be supported by the guide pins. Therefore, one of the sides of the wafer cavity 200 During the welding process, most of the functional guide pins 21 in the guide pin welding area 201 are 'the paper size conforms to the national standard (CNS) heart size (⑽χ see public copy) ------ 16493, BU — I ’ ^ (Please read the notes on the back before filling this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs I-JJ, «nn · ϋ I ϋ m I i— ί ϋ 1 ^ 1 II ϋ I- — iln I inin -III ϋ nn I ϋ-1 531861 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, printed A7 V. Description of the invention (2, It is easy to be broken or distorted by stress damage, even when the colloidal packaging process is applied after the connection. Because the gap at the corner end is much larger than the distance between adjacent guide pins (Leadmg SPace), the uneven filling of the resin causes deeding, which reduces the quality reliability of the product. In view of this, US Patent No. 5,925 926胄, U.S. Patent No. 5,25M42 proposed-a kind of enhancement A semiconductor device capable of withstanding the stress on the U-side of the wafer. As shown in Figures 6A and 6B, 'is an improved package 3 also has-a film carrier 30 and a semiconductor wafer 33 placed on the film carrier%' The traditional package advancer is that most corner bumps 34 (Gold Bump) are formed on the corners of the semiconductor wafer 33 of the package structure 3 (not shown), and borrowed from her and · ~知 # A plurality of supporting elements 32 (such as copper 飧 μ, human, such as copper poker) knotted at the corner position of the film carrier 30 can securely bond the solder bumps 34 and the supporting elements 32 to maintain the moon and the moon. Subject to the structural integrity of the functional guide pins 31. However, the above method must be preceded by the addition of multiple non-electrical transfer functions on the circuit surface 330 of the Y-YU and Y-YU-33 films. # 后 # # This pseudo-fresh pad 38, only solder can be applied to form most of the gold Ting block 34. If the wafer is soft, it is impossible to change the layout of the road or the wafer is not placed at the corners when the wafer is placed. The semiconductor wafer of the pseudo pads is difficult to plant the helmet method ... "Pseudo-lead-foot joints" make the corners of the chip fail to meet the needs of the people, leading to the destruction of the functional guide pins, and even cause transmission interruption or noise. [Summary of the Invention]: The main purpose of this month is to provide a package without additional packaging. Cost, that is, according to the actual process requirements, it can be added to the semi-conductor static ----- one additional body to increase the number of welding pads, # l ·. 0 ------- —order ------ --- Line 丨 * (Please read the notes on the back before filling out this page) 2 16493 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs ^ 31861 B7 V. Description of the invention (3) The positive film can be borrowed with the supporting element ( If it is a guide pin, etc.), a stable solder joint is formed, and a film carrier type semiconductor package capable of mounting the structural integrity of the guide pin is provided. Another object of the present invention is to provide an electronic device that requires the use of existing technology; Solder bumps, thereby improving the bonding strength between the wafer and the support element, so as to prevent the functional guide pins from being damaged by stress and improve the yield rate of the film carrier type semiconductor package and its manufacturing method. In view of the above and other objectives, the method for manufacturing a semiconductor package of the present invention includes the following steps: first prepare a film carrier with a cavity in the center, and the sides and corners of the cavity have been formed in advance. A plurality of functional guide pins and dummy guide pins; then, another semiconductor wafer is taken, the wafer has a surface, and an insulating protection layer is formed on the surface of the insulating protection layer; a metal deposition layer and a photoresist cover are sputtered on the surface of the insulating protection layer; Exposure, development, etching and other technologies have been developed to form one or more reinforcing solder bumps, resulting in the formation of a strong solder joint between the reinforcing solder bumps and the dummy guide pins after the wafers are aligned and pressed into the cavity. The manufacturing method of the present invention is different from the traditional method of relying on a fresh pad to consolidate the wafer, and directly forms a reinforced solder block on the insulating protective layer of the circuit surface of the wafer, thereby improving the semiconductor wafer without a dummy pad or a dummy pad layout. The lack of insufficient number allows the majority of supporting elements (such as dummy guide pins) placed at the corners of the film carrier to form a stable solder joint with the wafer through the reinforcing solder pads, thereby enhancing the stress tolerance of the corner position of the wafer, so that The functional guide pin will not be damaged by thermal stress under the temperature cycle of the subsequent process, which can greatly reduce the occurrence of transmission interruption or noise. [Schematic description]: This paper size applies to China National Standard (CNS) A4 (210 X 297 mm)
^ --------訂------.—線丨二 (請先閱讀背面之注意事項再填寫本頁) 3 16493 531861 經濟部智慧財產局員工消費合作社印製 4 A7 五、發明說明（4 ) 以下茲以最佳具體例配合所附圖式詳細說明本發明 之特點及功效： 第1圖係本發明铸體裝财晶片㈣導腳辉結部位 之局部放大剖視圖； σ 第2圖係本發明半導體裝置中膠片載具之上視示惫 «· ^ 第3圖係未運用本發明半導體裝置製法處理前之晶圓 剖視圖； ％ 第4 A至4D圖係本發明半導體裝置製法之整體製作流 程示意圖； 第5圖係習知未俱支撐元件之TCp半導體封裝件之上 視示意圖； 第6A圖係曰本專利第9〇641〇7號Tcp半導體封裝件 之上視示意圖；以及 第6B圖係第6A圖中剖面線6B_6B之剖面示意圖。 【發明詳細說明】： 以下即配合第1至4圖詳細揭露本發明半導體封裝件 及其製法之實施例，惟各圖式倶為例釋該實施例中元件配 置關係之簡化圖示，封裝結構之實際元件佈局型態，元件 佈設數量以及作動關係均將更形複雜。 第1圖係為利用本發明製法製得之Tcp半導體封裝件 其晶片角端部位之局部放大剖視圖。如圖所示，該半導體 裝置1係包含一膠片載具10，於該膠片載具1〇各側邊及 角落部位上分別形成有多條功能性導腳u以及偽導腳 本紙張尺度適用中國國家標準（CNS)A4規格（210 x 297公釐） 16493 (請先閱讀背面之注意事項再填寫本頁)^ -------- Order ------.-- Line 丨 II (Please read the notes on the back before filling out this page) 3 16493 531861 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 4 A7 5 4. Description of the invention (4) The following is a detailed detailed description of the features and effects of the present invention with the best specific examples and the attached drawings: Figure 1 is a partial enlarged cross-sectional view of the glow-knotted portion of the guide leg of the foundry-mounted wafer of the present invention; σ Fig. 2 is a diagram showing the exhaustion of a film carrier in a semiconductor device of the present invention «· ^ Fig. 3 is a cross-sectional view of a wafer before the semiconductor device manufacturing method of the present invention is used for processing;% 4A to 4D are semiconductor devices of the present invention Schematic diagram of the overall manufacturing process of the manufacturing method; Figure 5 is a schematic top view of a conventional TCp semiconductor package with no supporting components; Figure 6A is a schematic top view of a Tcp semiconductor package of this patent No. 06410077; And FIG. 6B is a schematic cross-sectional view of the section line 6B_6B in FIG. 6A. [Detailed description of the invention]: The embodiments of the semiconductor package and its manufacturing method according to the present invention will be disclosed in detail with reference to FIGS. 1 to 4 below. However, each diagram 图 is a simplified diagram illustrating the component arrangement relationship in this embodiment, and the package structure. The actual component layout type, the number of component layouts, and the operating relationship will be more complicated. FIG. 1 is a partial enlarged cross-sectional view of a corner portion of a wafer of a Tcp semiconductor package manufactured by the manufacturing method of the present invention. As shown in the figure, the semiconductor device 1 includes a film carrier 10, and a plurality of functional guide pins u and pseudo guide script papers are formed on each side and corner of the film carrier 10. The paper size is applicable to the country of China. Standard (CNS) A4 size (210 x 297 mm) 16493 (Please read the precautions on the back before filling this page)
531861 經濟部智慧財產局員工消費合作社印製 5 A7 B7 五、發明說明（5 ) 12,俾供該等功能導腳及偽導腳熱壓接於一半導體晶片 上，其中，該晶片13得視實際需要另外增設至少一補強銲 塊14( Dummy Gold Bump)以供該等偽導腳12與之壓接， 同時該等補強銲塊14之接設不須仰賴銲墊固接便可直接 形成於晶片1 3之絕緣保護層〗32上。現以第2至*圖詳述 本發明製法之整體製作流程： 首先’如第2圖所示，備一特製之膠片載具1〇，其中 央部形成有一置晶穴1 〇〇，且該置晶穴〗〇〇各側邊以及角 落位置已預先定義出複數個導腳銲結區1〇1與支撐元件銲 結區1 02。而後，於此等側邊導腳銲結區！ 〇丨以及支撐元 件銲結區1 02上分別蝕刻製得多數提供訊號傳遞之功能性 導腳11及不具電性功能之複數條偽導腳12，俾增強待承 載晶片之應力耐受程度。上述步驟俱為習知遂不另多述， 惟該等偽導腳12之一端須伸入置晶穴100内適當位置以供 待承載晶片上多數補強銲塊（未圖示）可與之對位壓接。 之後，如第3圖所示，取一半導體晶圓13( Wafer)(即 半導體晶片13未獲切割前之連接狀態稱之，其標號與晶片 13相同），β亥曰曰圓13具有一作用表面13〇 (即佈設有多數 電子電路與電子元件之表面）及一相對之非作用表面 ’其中晶圓13之作用表面130上具有一絕緣防護層132 (Passivation )並接設有複數個與該功能性導腳（未圖示） 對應壓接之輸出入銲塾17。531861 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 5 A7 B7 V. Description of the invention (5) 12, for the functional guide pins and pseudo guide pins to be thermally crimped onto a semiconductor chip, where the chip 13 is subject to inspection Actually, it is necessary to add at least one reinforcing solder bump 14 (Dummy Gold Bump) for crimping of these dummy guide pins 12, meanwhile, the connection of the reinforcing solder bumps 14 can be directly formed without relying on the bonding pads to be fixed. The insulating protection layer 32 of the chip 13 is provided. The overall production process of the manufacturing method of the present invention is described in detail in Figures 2 through *: First, as shown in Figure 2, a special film carrier 10 is prepared, and a central cavity 100 is formed in the central part, and the Set the crystal cavity] 00. Each of the side edges and the corner positions has been previously defined with a plurality of guide pin bonding areas 101 and supporting component bonding areas 102. Then, solder on these side guides! 〇 丨 and the supporting component soldering area 102 are etched to provide a large number of functional guide pins 11 and a plurality of dummy guide pins 12 having no electrical function to enhance the stress tolerance of the wafer to be carried. The above steps are all familiar, so I wo n’t go into details, but one of the ends of the pseudo guide legs 12 must be inserted into the cavity 100 in a suitable position for most of the reinforcing solder bumps (not shown) on the wafer to be carried. Bit crimp. Then, as shown in FIG. 3, a semiconductor wafer 13 (wafer) is taken (that is, the connection state of the semiconductor wafer 13 before it is cut is called, and its reference number is the same as that of the wafer 13). The beta circle 13 has a function The surface 13o (that is, the surface on which most electronic circuits and electronic components are arranged) and a relatively non-active surface. Among them, the active surface 130 of the wafer 13 has an insulating protection layer 132 (Passivation), and a plurality of the protective surfaces 132 The functional guide pin (not shown) corresponds to the input / output welding pad 17 of the crimp.
本發明之特徵係於該絕緣防護層丨32上增設一或多個 補強鲜塊14以供該等偽導腳12補強銲結之用。如第4A 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐) '' 16493 f請先閱讀背面之注意事項再填寫本頁}A feature of the present invention is that one or more reinforcing fresh blocks 14 are added on the insulating protection layer 32 for the pseudo guide pins 12 to strengthen the welding joint. If the 4A standard of this paper applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) '' 16493 f Please read the precautions on the back before filling in this page}
531861 A7 B7 五、發明說明（6 ) 圖至第4D圖所示，藉由習用物理氣相沉積法（physical (請先閱讀背面之注意事項再填寫本頁)531861 A7 B7 V. Description of the invention (6) Figures to 4D, using the conventional physical vapor deposition method (physical (Please read the precautions on the back before filling this page)
Vapor Deposition，PVD)或化學氣相沉積法（Chemical Vapor Deposition，CVD)使該絕緣防護層132表面上濺鍍 (Sputtering )形成一鈦鎢金金屬沉積層 15( Ti/W/Au Deposition );而後，復於該鈦鎢金金屬沉積層表面15覆 蓋一補強銲塊形成光罩16( Bump Photo Mask )，將覆有光 罩16之金屬沉積層15施以曝光、顯影、電鍍金塊 (Electroplating Gold)等步驟；最後再將該光罩16以及 金屬沉積層15蝕除使該絕緣防護層132裸露，即完成於該 絕緣防護層132上形成純金材質多數補強銲塊14之製程作 業。經過晶圓分割將複數片半導體晶片13逐一安置於膠片 載具10上便能與各導腳11，12進行内導腳銲結作業（inner Lead Bonding，ILB ) 〇 經濟部智慧財產局員工消費合作社印製 接續第4D圖所示，由於該等補強銲塊14無須仰賴偽 銲墊（Dummy Pad，類似圖中17之結構，多係不具電性傳 導功能之鋁墊）固結即可直接形成於晶片13作用表面13〇 之絕緣保護層1 3 2上，是以該等補強銲塊14可配合偽導腳 12尺寸以及封裝實際製程考量安置於晶片13作用表面ι3〇 上任何位置，大幅放寬偽導腳12之適用限制。另一方面， 晶片13製作中若不能預置足量偽銲墊（未圖示）提供銲塊 植接’則該晶片1 3仍可在絕緣保護層上形成補強銲塊14， 使偽導腳與晶片形成穩固接合關係，增強晶片支撐性以避 免功能導腳遭應力破壞。 _以上所述僅為本發明之較佳實施例而已，並非用以限 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 6 16493 531861Vapor Deposition (PVD) or Chemical Vapor Deposition (CVD) causes sputtering (Sputtering) on the surface of the insulating protection layer 132 to form a titanium tungsten gold metal deposition layer 15 (Ti / W / Au Deposition); and The surface 15 of the titanium-tungsten-gold metal deposition layer is covered with a reinforcing solder bump to form a photomask 16 (Bump Photo Mask). The metal deposition layer 15 covered with the photomask 16 is exposed, developed, and electroplating gold. Etc .; finally, the photomask 16 and the metal deposition layer 15 are etched to expose the insulating protective layer 132, and the process of forming the majority of the reinforcing solder bumps 14 made of pure gold on the insulating protective layer 132 is completed. After the wafer is divided, a plurality of semiconductor wafers 13 are placed on the film carrier 10 one by one, and inner lead bonding (ILB) can be performed with each of the guide pins 11, 12 〇 Consumers' cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs As shown in Figure 4D following the printing, since the reinforcing pads 14 do not need to rely on dummy pads (similar to the structure in Figure 17), most of them are aluminum pads without electrical conductivity. They can be directly formed on the pads. On the insulating protective layer 1 3 2 of the active surface 13 of the chip 13, the reinforcing solder pads 14 can be placed at any position on the active surface of the chip 13, in accordance with the size of the dummy guide pin 12 and the actual packaging process considerations. Applicable restrictions on guide pin 12. On the other hand, if a sufficient amount of dummy solder pads (not shown) cannot be provided in the manufacture of the wafer 13 to provide solder bump implantation, the wafer 13 can still form a reinforcing solder bump 14 on the insulating protective layer to make the dummy guide pin. Form a stable bonding relationship with the wafer, enhance the support of the wafer to avoid stress damage to the functional guide pin. _The above is only a preferred embodiment of the present invention, and is not intended to limit the paper size to the Chinese National Standard (CNS) A4 (210 X 297 mm) 6 16493 531861
10,20,30膠片載具 101,201,301導腳銲結區 11，21，31功能性導腳 13,23,33半導體晶片 131,331非作用表面 14 補強銲塊 15 鈇鎢金金屬沉積層 17,27 輪出入銲墊 定本發明之實質技術内容範圍。本發明之實質技術内容係 廣義地定義於下述之申請專利範圍中，任何他人所完成之 技術實體或方法，若與下述申請專利範圍所定義者係為完 全相同或為一種等效之變更，均將被視為涵蓋於此專利範 圍之中。 【符號標號說明】： 1，2 TCP半導體封裝件 100,200置晶穴 1〇2 支撐元件銲結區 12,32 偽導腳（支撐元件） 130,330作用表面 132,332絕緣保護層 34 金質銲塊 16 補強銲塊形成光阻 38 偽鮮塾 -------：----ί-----------訂---------線 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 適 度 尺 張 j紙 本 格 規 A4 5) N (C 準 標 家 29 7 93 6410,20,30 Film carrier 101,201,301 Guide pin soldering zone 11, 21, 31 Functional guide pin 13, 23, 33 Semiconductor wafer 131, 331 Non-active surface 14 Reinforcing solder bump 15 Tungsten tungsten metal deposit layer 17, 27 Wheels in and out The solder pad determines the essential technical content of the present invention. The essential technical content of the present invention is broadly defined in the scope of the patent application described below. Any technical entity or method completed by another person is the same as or equivalent to the definition of the scope of the patent application described below. Are deemed to be covered by this patent. [Description of Symbols and Symbols]: 1, 2 TCP semiconductor packages 100, 200 with cavities 10 2 Supporting component soldering area 12, 32 Pseudo-leads (supporting components) 130, 330 Active surface 132, 332 Insulating protective layer 34 Gold solder bump 16 Reinforcing welding The block forms a photoresist 38 pseudo fresh 塾 -------: ---- ί ----------- order --------- line (please read the note on the back first Please fill in this page for further information.) The Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs prints a moderate size sheet of paper A4 5) N (C Standard bidder 29 7 93 64