TW518627B - Field emission display and method - Google Patents

Abstract

Method for operating a field emission display (10) and a field emission display (10) that has a plurality of column conductors (17, 18, 19) on which electron emitter structures (24) are disposed. Column conductor driver circuits (47, 48, 49) are coupled to respective column conductors (17, 18, 19) and row conductor driver circuits (37, 38, 39) are coupled to respective row conductors (27, 28, 29) to form sub-pixels (50, 57, 58, 60, 67, 68, 70, 77, 78). The column conductor driver circuits (47, 48, 49) and the row conductor driver circuits (37, 38, 39) cooperate to cause the electron emitter structures (24) to emit electrons. The column conductor driver circuits (47, 48, 49) measure a signal change on at least one of the column conductors and thereby adjusts the operating state of the electron emitter structures (24) are adjusted in accordance with the comparison results.

Description

518627 A7 B7 V. Description of the invention (1) Scope of the invention The present invention relates generally to a field emission display and, in particular, to a method and circuit for controlling the emission current in a field emission display. BACKGROUND OF THE INVENTION A field emission display (FED,) is a conventional technology. A field emission display includes an anode plate and a cathode plate which define a thin casing. The cathode plate contains a matrix of row and column conductors, which are used to generate electron emission from electron emitter structures, such as Spindt tips. FED's also include a current-limiting resistor between the electron emitter structure and the cathode plate for controlling electron emission current. Generally, a current-limiting resistor has a resistance number greater than ten million ohms. Because of the high resistance number, current-limiting resistors are difficult to manufacture and are highly temperature sensitive, which results in uneven current emission in temperature from the electron emitter structure. Another disadvantage encountered with field emission displays is the differential aging of the electron emission configuration. Therefore, there is a need for a method and apparatus for controlling emission current in a field emission display that overcomes at least one of these disadvantages. Brief Description of the Drawings Figure 1 represents a specific cut isometric diagram and circuit configuration of a field emission display according to an embodiment of the present invention; Figure 2 represents the equivalent circuit of the field emission display of Figure 1; Figure 3 is a diagram related to the present invention 1-line conductor driver circuit diagram; and -4- This paper size applies to Chinese National Standard (CNS) A4 specification (210X297 mm) 518627 A7 B7 V. Description of the invention (2) Figure 4 is used for the field emission display of Figure 1 One of the operations is a clock diagram. For simplicity and clarity of illustration, elements in the drawings are not necessarily drawn to scale, and the same reference numerals in different drawings represent the same elements. DETAILED DESCRIPTION OF THE DRAWINGS In general, the present invention includes a method and a field emission display for maintaining an average emission current during the operating life of the display. The method includes using a row conductor driver circuit to drive a FED row conductor and a column conductor driver circuit to drive the FED column conductor, wherein the row conductor driver circuit is configured with a high voltage, or a low voltage, or a high impedance state in the row. On the conductor. In addition, when the row conductor driver circuit is in a high impedance state, it monitors the voltage on the row conductor to which it is coupled. When the output of the row and column driver circuits approaches zero volts, the FED system is turned off. When the row conductor driver circuit is in a high impedance state and the column conductor driver circuit is in a high voltage step, the sub-pixels related to the column conductor and the row conductor transmit an emission current. The voltage at which a particular column of conductors turns on the sub-pixels is referred to as a column selection voltage. If the electric charge is emitted, the voltage on the row conductor is related to the structure of the electron emitter whose electron emission increases. This voltage increase or charge is monitored and compared to a predetermined voltage by the row conductor driver circuit. The predetermined voltage system is also referred to, for example, an intensity voltage number and can be determined when the display system is activated. Once the ideal voltage increase is reached, that is, when the ideal luminosity is reached, the output of the row conductor driver is switched from a high impedance state to a high voltage state to adjust the operating state of the electron emitter structure. For example, the electron emitter structure and therefore the sub-pixels are cut off. Better, the guidance of the pixels -5- This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X 297 mm) 518627 A7 B7 V. Description of the invention (3) Generated during the opening and closing of a single frame clock . The row conductor driver circuit can operate in both an amplitude modulation (AM) mode and a dynamic pulse width modulation (PWM) mode. In the amplitude modulation mode, the capacitance of the row conductor is charged and discharged to a preselected step. In the AM mode, one row of a strong sub-pixel is discharged to a positive voltage to reduce the emission current above a full discharge range, while one row of a weak sub-pixel is discharged to zero volts. In the PWM mode, the stronger emitting sub-pixel has a pulse width shorter than a normal pulse width and the weaker emitting sub-pixel has a longer pulse width. FIG. 1 is a specific cut isometric diagram and circuit configuration of a field emission display (FED) 10 according to an embodiment of the present invention. The FED 10 includes a FED device 11 and a control circuit 12 for controlling the emission current in the FED device 11. The FED device 11 includes a cathode plate 13 and an anode plate 14. The cathode plate 13 includes a substrate 16 which can be made of glass, silicon, and the like. A first-row conductor I7, a second-row conductor 18, and a third-row conductor 19 are disposed on the base body 16. An electronic layer 21 is disposed on the row conductors 17, 18, and 19, and still defines a plurality of wells 22. An electron emitter structure 24, such as a Spindt tip, is disposed in each well 22, and column conductors 27, 28, and 29 are formed on the electron layer 21. The column conductors 27, 28, and 29 are arranged in close proximity to the electron emitter structure 24, respectively. The column conductors 27, 28, and 29 contain a plurality of holes 30, which merge the related wells 22 and the electron emitter structure 24 to form a current emitting portion 31. Row conductors 17, 18, and 19 and column conductors 27, 28, and 29 are used in the selective addressing electron emitter structure 24. -6- This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) 518627 A7 B7 V. Description of the invention (4 is easy to understand the invention, Figure M illustrates three column and row conductors. However, its system Ideal for understanding any number of column and row conductors can be used. The standard number of column conductors used in FED devices is 24o and the standard number of row conductors is 96o. Field emission displays for addressable materials The method of the cathode plate is known to those skilled in the art. The anode plate 14 is arranged in a receiving-transmitting electrode, which is determined by the electrons emitted by the electron emitter structure 24. The anode plate is called a For example, a transparent substrate 33 made of glass. An anode 34 is disposed on the transparent substrate. The anode 34 is preferably made of a transparent conductive material, such as an indium tin oxide. In a preferred embodiment, The anode 34 is the continuous b with respect to the entire emission area of the cathode plate, that is, the anode 34 is the whole with respect to the electron emitter structure 24. A plurality of phosphors are arranged on the anode 34, and the phosphorescent plutonium emits light from the cathode. Light object 36 is The activity of the radio current 32 emits light. The method for manufacturing the anode plate of the field axis indicator for an addressable matrix is also known to those skilled in the art. Related to one embodiment of the present invention, the fabrication The two J-made circuits I2 include column-conductor driver circuits 37, 38, and 39 and row-conductor driver circuits 47, 48, and 49. Column-conductor driver circuits 37, 38, and 39 Only eight w, and 39 are coupled to the column conductors 27, 28, and 29, and the row conductor driver circuit 47, 48, and the row conductors 17, 18, and 19. respectively, and 49 are coupled to

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Figure 2 is a layout diagram of FED Π, 18, and 19, 27, 28, and 29, 10. The row conductor driver circuit 47 and the column conductor driver circuit 37 shown in FIG. 2 represent one of the row conductors 48, 49, and the column conductors 38, 39.

518627

. It should be understood that although only three column-conductor driver circuits and three row-conductor driver circuits are disclosed, they can be more or fewer column-conductor driver circuits and more or fewer row-conductor driver circuits. Figure 2 also illustrates the structure of the electron emitter, the sub-pixel capacitance, and the current-limiting resistors associated with each column and row conductor. In particular, the sub-pixel capacitor sub-pixel current-limiting resistor 52, an electron emitter structure 24 (27) related to the sub-pixel 50, is disclosed as being coupled to the column conductor 27 and the row conductor 17. The electron emitter structure 24 (27 '17) is a centralized parameter element that reveals the structure of the electron emitter such as _ which represents the% of all sub-pixels. It should be understood that the reference number 24 has been roughly used to identify the structure of the electron emitter. To help explain the implementation shown in FIG. 2 For example, the structure of the electron emitter has been defined by adding a subscript to the reference number 24. For example, the structure of the electron emitter related to the column conductor 27 and the row conductor 17 has been defined by the reference number 24 (27 17). The structure of the electron emitters in the column conductor 28 and the row conductor 17 has been defined by the reference number ^ from ⑺, and the structure of the electron emitters related to the column conductor 27 and the row conductor 18 has been defined by the reference number 24 (27, 18). Limitation, etc. Sub-pixel electric valley 5 3, Sub-pixel mud-limiting resistor 5 4 and related to the sub-pixel 57 < electron emitter structure 24 (2S17) reveals such as ballasting on column conductor 28 and row conductor 17. hair The emitter structure reveals a centralized parameter element that represents all the electron emitter structures related to the sub-pixel 57. The sub-pixel electric valley 5 5, the sub-pixel current limiting resistor 56, and the electron emitter related to the sub-pixel 58. Structure 24 (29, m) reveals such as _ combined in column conductors and row conductors 17. Electron emitter structure 24 (29, n>) reveals as a centralized parameter element representing all electron emitter structures related to sub-pixel 58.- 8 -

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This paper size applies Chinese National Standard (CNS) A4 specification (210X 297 mm) 518627 A7 B7 V. Description of the invention (6) Sub-pixel capacitor 6 1. Sub-pixel current limiting resistor 62, and electronics related to sub-pixel 60 The emitter structure 24 (27, ...) reveals, for example, a coupled parametric element coupled to the column conductor 27 and the row conductor 18. The electron emitter structure 24 (27, ...) reveals, for example, a centralized parameter element representing all electron emitter structures related to the sub-pixel 60. The sub-pixel capacitor 63, the sub-pixel current limiting resistor 64, and the electron emitter structure 24 (28, referred to as the sub-pixel 67) are disclosed as being coupled to the column conductor 28 and the row conductor 18. The electron emitter structure 24 (28, 18) Reveals a centralized parameter element that represents all the electron emitter structures related to sub-pixel 67. Sub-pixel capacitance 65, sub-pixel current limiting resistor 66, and electron emitter structure 24 related to sub-pixel 68 ( 29, ... reveals as coupled to column conductor 29 and row conductor 18. Electron emitter structure 24 (29, ... reveals as a centralized parameter element representing all electron emitter structures related to sub-pixel 68. Sub-pixel capacitance 71, Sub-image The current-limiting resistor 72 and the electron emitter structure 24 (27,19) related to the sub-pixel 70 are disclosed as coupled to the column conductor 27 and the row conductor 19. The electron emission #structure 24 (27,19) is disclosed as a representative All centralized parameter elements related to the electron emitter structure of the sub-pixel 70. The sub-pixel capacitor 73, the sub-pixel current limiting resistor 74, and the electron emitter structure 24 (28, 19) related to the sub-pixel 77 are disclosed as coupling In the column conductor 28 and the row conductor 19. The electron emitter structure 24 (28, 19) reveals a centralized parameter element that represents all the electron emitter structures related to the sub-pixel 77. Sub-pixel capacitor 75, sub-pixel current-limiting resistor 76, and the electron emitter structure 24 (29, 19) related to the sub-pixel 78 is disclosed as being coupled to the column conductor 29 and the row conductor 19. The electron emitter structure 24 (291 is disclosed as a representative of all the related to the sub-pixel 78 Concentrated parameter elements of the structure of the electron emitter. This paper size applies to the Chinese National Standard (CNS) A4 specification (210X297 mm) 518627 A7 B7 V. Description of the invention (7) Refer briefly to Figure 3, which reveals the details of Row conductor An embodiment of one of the actuator circuits 47, 48, and 49. In other words, each circuit block 47, 48, and 49 contains the circuit configuration shown in Figure 3. The row conductor driver circuits 47, 48, and 49 include a sample And a synchronization circuit 80, a comparator 81, a driver control circuit 82, a tri-state driver 83, a single-stage series-to-parallel converter 79, and a correction circuit 88. In particular, an input terminal 84 is used to receive an analog Video signal, VIDA. An output 85 of the sampling and synchronization circuit 80 is coupled to a non-inverting input terminal 86 of the comparator 81. An output terminal 87 of a comparison circuit 81 is coupled to an input terminal 111 of a driver control circuit 82. The driver control circuit 82 includes an amplitude modulation section 93 and a pulse width modulation section 94. An output terminal 89 of the driver control circuit 82 is coupled to an input terminal 90 of the tri-state driver 83. An output terminal 9 1 is commonly coupled to the input terminal 92 of the comparator 81 and the row conductor shown in FIG. 2. An input terminal 95 of the correction circuit 88 is used for receiving a start signal for coupling, and an output terminal 96 of the correction circuit 88 is coupled to the control terminal 97 of the comparator 81. An output terminal 98 of the correction circuit 88 is coupled to an input terminal 99 of a single-stage series-to-parallel converter 79. One of the additional input terminals 101 of the single-stage series-to-parallel converter 79 is used to receive and couple a series input from channel n-1. An output terminal 102 of the single-stage series-to-parallel converter 79 is coupled to an input terminal 103 of the driver control circuit 82 and a series output such as a series output coupled to a channel n + 1. One output terminal 110 of the single-stage series-to-parallel converter 79 is connected to the input terminal 11 of the driver control circuit 82. In operation, when the display 10 is powered on, the correction circuit 88 transmits a reference signal to the comparator 81 through the control terminal 97. In addition, the correction circuit 88 -10- This paper size applies to China National Standard (CNS) A4 specification (210X297 mm)

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Line V. Description of the invention (Cycle display 10 to display an all-white 庠 Kuishan 彳, > Bai Rong 桊 In particular, the display 10 is selected in sequence by sequentially starting the column conductor driver circuit in 3 columns. In the column When the conductor driver circuit 37 is selected; and = Selection-enabled driver control circuit 82 wx circuit 88 Gan Caitong is coupled to the child image of the column conductor 27 + Βφ For example, the column driver circuit 37 is configured with large Ten-volt and row-conductor drives configure zero-volts on the row conductors 17, 18, and 19, respectively, 7 =: ㈣, ... to conduct current. Ideally, each is sufficient to build a mutual-white signal. For its strong transmitter For the sub-pixels, the voltage appearing at the output of the driver circuit is larger than 'causes the comparator to jump. Therefore, for that sub-pixel, -logic two-voltage steps are stored in the series-to-parallel converter 79. ^ Compare益 不 跳 '-The logic low or zero-voltage serial-to-parallel converter 79 for that sub-pixel is stored in the.-The stop of the linear clock, the matter of information is out of the line driver register and stored in external memory. ) Medium For example, 'in-stop of the linear clock, + intensity or luminosity information of 50, 2, and 70 pixels is flowed into the register', and then the information is sent to external memory. Then the lower-column system is selected And the process continues until all sub-pixels are lacking to be identified, such as a strong pixel or a weak pixel. In this method, all of them are displayed to map a line at a clock, with one bit for the output of each sub-pixel. This image acquires a frame clock, which is two-tenths of a second.-Once the display is imaged, the data stored in memory is appended to the appropriate digital video bit data as it flows into the display. Know the line The paper size of this paper applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 11 51862?

Jade, description of the invention (9-actuator circuit, it is expected that each addition and concealment, regardless of the sub-pixel display--weak sub-pixels. For example,-logical one is in digital video, the sub-pixel system-strong emission sub-pixel On the other hand, if the-logic is added to the digital video bit, the sub-pixel is-the weak emission sub-pixel. Once the mentality has been mapped, the correction circuit 88 is shut down. Figure 4 shows the description-a kind used in-display mode One of the methods of operating fed U) is a clock diagram. The display mode is identified by the creation of a display image at the anode 14. It should be understood that the clock diagram shown in FIG. 4 will be provided with Figures 2 and 3 together. The selective addressing and activation of the sub-pixels 50, 57, and 58 represented in FIG. It should be understood that the sub-pixels 60, ⑺, ⑽, 70, 77 ', and 78 can be selected in a similar manner as by activating the row conductor driving circuit. At clock t. All display capacitors are discharged by driving the output voltages of the row conductor driver circuits 47, 48 'and 49 and the column conductor driver circuits η, 38' and 39 to a voltage lower than the threshold voltage of the respective electron emitter structure. To zero volts. By way of example, the output voltages of the row driver circuits 47, 48, and 49 and the column conductor drivers; the output voltages of the circuits 37, 38 ', and 39 are driven to zero volts. In addition, the nodes 101, 102, 103, 104, 105, 106, 107, 108, and the system are driven to zero volts. Each of the capacitors 51, 53, M, Y, M, μ, 71, 73, and 75 is at a completely zero volt voltage. At clock t1, the row conductor driver circuits 47'48, and 49 are arranged in a high-impedance state and are therefore not connected from F E D i 0. It should be noted that the clock diagram 100 only discloses that the row conductor driver circuit 47 is configured in a high impedance state. Then the column driver circuits 37, 38, and 39 are as shown in Figure 4 -12-518627 A7

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518627 V. Description of the invention (11 R act〗 7 represents the current-limiting resistance of the column conductor coupled to one of the signals coupled to the row conductor 7 to activate; and η is the number of column conductors of FED 10. It should be noted that each row conductor Has a separate effective capacitance and effective current-limiting resistance similar to one of them. For example, the effective capacitance 2 of each individual row conductor 2 and the effective current-limiting resistance are activated by all but one of the conductor systems. given:

Ceft, i8 = (n-1) * Caetl8

Reffl8 = l / (n-l) * Ractu where

Cem8 represents the capacitance related to the concentrated parameter of the conductor at the center of the zero-volt row of conductors and the conductors at the center of the column;

Cactl8 represents the capacitance of the column conductor related to the activation of one of the signals coupled to the row conductor 18; represents the current-limiting resistance related to the concentrated parameter of the column conductor coupled to the zero-volt row conductor ^) column conductor;

Ractl 8 represents the current-limiting resistance associated with a column conductor that is actuated by one of the signal conductors in the row; and η is the number of conductors in the FED 10. The effective capacitance and effective current-limiting resistance related to the row conductor 19 are given by: cem9 = (nl) * cactl9 Reffi9 = l / (nl) * Ractl9 where -14- This paper scale is suitable for national standards of fiscal countries ( CNS)! ^: Grid (2Ι ^ Γ297 public love) binding

518627 A7 B7 V. Description of the invention (12) ceffl9 represents the capacitance related to the concentration parameter coupled to the conductor of the (η-1) column of the conductor 19 in the row of zero volts;

Caetl9 represents the capacitance of the column conductor associated with the activation of one of the signals coupled to the row conductor 19;

Rem9 represents the current-limiting resistance related to the concentrated parameter coupled to the conductor of the (η-1) column of the row conductor 19 at zero volts;

RacU9 represents the current-limiting resistance of the conductor associated with one of the signals coupled to the row conductor 19 to activate; and η is the number of 歹 J conductors in FED 10. Returning to the operating instructions of a sub-pixel, for example, sub-pixel 50, capacitor 51, and C effl7 from the capacitor voltage divider network. Because the number of capacitances of Ceffl7 is much larger than the number of capacitances of capacitor 51, the voltage at node 101 Maintaining approximately zero volts and essentially all the voltage from the column conductor driver circuit 37 appears across the capacitor 51. If the voltage on the column conductor is greater than the threshold voltage of the electron emitter structure 24 (27, m), the electron emitter structure 24 (27, 17) emits electrons, thereby discharging the capacitor 51 and charging the effective capacitance Ceffl7. Therefore, at the node When the voltage of 101 increases, the voltage across the electron emitter structure 24 (27, m) is reduced. When the voltage of the electron emitter structure 24 (27, ⑺ decreases to a number below the threshold voltage, it stops emitting electrons, that is, Comparator 8Γ (shown in Figure 3) cooperates with output terminal 91 to monitor the voltage on the row conductor when the row conductor driver circuit is in a high impedance state and the electron emitter structure is transmitting current. On the row conductor The change in the measured voltage is symmetrical to the charge emitted by the electron emitter structure. For example, the row conductor driver circuit 47 compares the measured change in the voltage on the row conductor 17 -15- This paper is for China Standard (CNS) A4 (210 X 297 mm)

Installation gas 518627 A7 B7 V. Description of the invention (13) A voltage symmetrical to the ideal intensity of the sub-pixel 50, wherein the symmetrical voltage is determined as described above with reference to FIG. 2. The row conductor driver circuit 47 turns off the sub-pixels 50 after an appropriate amount of charges have been emitted. For sub-pixel 50, when the electron emitter structure 24 (27, 17) emits current, the change in the charge at node 10 1 is given by the association: q = * cactl7 * AV101 where q is borrowed The entire charge emitted by the electron emitter structure 24 (27, ⑺;

Cactl7 is related to the capacitance of a column conductor that is coupled to row conductor 17 and ΔV1 () l is the change in the voltage of node 101. The row conductor driver circuit 47 includes an amplitude modulation section 93 such that the capacitor 51 is discharged to a preselected voltage instead of zero volts. Therefore, a row of conductors of a strong sub-pixel, that is, a strong electron emitter structure, is discharged to a positive voltage, and the current emitted by the discharge is reduced compared to that when the capacitor 51 is at a discharge voltage of zero volts. The total number of discharges. A row of conductors of a weak sub-pixel, that is, a weak electron emitter structure, is discharged to zero volts. The determination of whether the structure of the electron emitter is strong or weak can be performed when the FED 10 is powered by, for example, displaying a completely white single frame and determining which electron emitter structure switches or jumps the comparator circuit. Those that are suitably strong electron emitter structures and those that are inappropriately weak electron emitter structures. The locations of the strong and weak electron emitter structures can be stored in a memory location. After the electron emitter structure 24 (27,17) has emitted the ideal current, it is cut by -16- This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm)

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518627 A7 B7 V. Description of the invention (14) The line-conductor driver circuit 47 is cut from a high-impedance state to a high-voltage state. This reveals the clock t3 as shown in FIG. 4. During this clock period, when the output voltage of the row-conductor driver circuit 47 is switched to the south voltage state, the voltage at the node 101 increases because of the Ce 7 charging. At clock t4, the output voltage of the column conductor driver circuit 37 is switched from a high voltage, such as eighty volts, to a low voltage, such as zero volts; thereby discharging the capacitors 51, 53, and 55 related to the row conductor 17 . At clock t5, the row conductor driver circuit 47 is arranged in a high impedance state and the output voltage of the column conductor driver circuit 38 is switched from a low voltage state, such as zero volts, to a high voltage state, such as eighty volts. The row conductor driver circuit 47 monitors the voltage on the row conductor 17 and the current emitted by the electron emitter structure 24 (28, 17). The row conductor driver circuit 47 compares the measured change in the voltage on the row conductor 17 to a voltage symmetrical to the ideal intensity of the sub-pixel 57, where the symmetrical voltage was previously determined as described with reference to FIG. 2. The row conductor driver circuit 48 turns off the sub-pixel 57 after a proper total of charges have been emitted. For sub-pixel 57, when the electron emitter structure 24 (28, 17) emits current, the change in the charge at node 104 is given by the association: q = * cactl7 * AV104 where q is borrowed The entire charge emitted by the electron emitter structure 24 (28, ⑺;

CaeU7 is related to a capacitor that is coupled to a column conductor of row conductor 17 and ΔV1Q4 is a change in the voltage at node 104. -17- This paper size applies to China National Standard (CNS) Α4 size (210X 297 mm). Η

518627 A7 B7 V. Description of the invention (15) After the electron emitter structure 24 (28, 17) has emitted the ideal current, it is cut off from the high-impedance state to the high-voltage state by switching the row conductor driver circuit 47. This reveals the clock t6 as shown in FIG. 4. At clock t7, the output voltage of the column conductor driver circuit 38 is switched from a high voltage, such as eighty volts, to a low voltage, such as zero volts; thereby discharging the capacitors 51, 53, and 55 related to the row conductor 17 . At clock t8, the row conductor driver circuit 47 is arranged in a high impedance state and the output voltage of the column conductor driver circuit 39 is switched from a low voltage state, such as zero volts, to a high voltage state, such as eighty volts. The row conductor driver circuit 47 monitors the voltage on the row conductor 17 and the current emitted by the electron emitter structure 24 (29.17). The row conductor driver circuit 47 compares the change measured in the voltage on the row conductor 17 to a voltage symmetrical to the ideal intensity of the sub-pixel 58, wherein the symmetrical voltage is determined as described above. The row conductor driver circuit 47 cuts off the sub-pixel 58 after an appropriate total amount of charge has been emitted. When the electron emitter structure 24 (29, m is the emission current, the change in the charge at the node 107 is given by the association : Q = * Cactl7 * AV107 where q is the total charge emitted by the electron emitter structure 24 (29,17);

Cactl7 is related to the capacitance of a column of conductors coupled to row conductors 17 and Δ Vi. 7 is the change in the electricity of node 107. After the electron emitter structure 24 (29, ⑺ has emitted an ideal current, it is switched from a high-impedance state to a high-voltage state by switching the row conductor driver circuit 47-18- 210X 297 mm) 518627

Mouth to cut off. This reveals the clock shown in Figure 4 ^. It should also be noted that in the clock ^, the output voltage of the column conductor driver circuit 39 is switched from-high voltage two, such as eighty volts, to-low voltage, such as zero volts; thereby discharging the capacitors related to the row conductor Π 5 丨, 53, and 55. As can be seen from the clock diagram 100, another advantage of the present invention is the additional use: amplitude modulation to control the emission current, and the pulse width modulation section 94 of each row conductor driver circuit performs pulse width modulation. For example, assume that the clock and variable pulse widths shown in the clock diagram 100 and the ideal intensity of the sub-pixels 50, 57, and 58 are the same. Its row-conductor driver circuit 47 is the total number of clocks in a high-impedance state. A small part is used for the clock period between the clocks and most of it is used for the clock period between the clocks and t9. Therefore, the electron emitter structure is a stronger emission configuration than the electron emitter structure 24 (29, ⑺. In other words, the sub-pixel 57 is a stronger emission sub-pixel than the sub-pixel 58. The sub-pixel 5 1 is one in emission Intensities are between those of subpixels 5 7 and 5 8. Therefore, a row of conductor drivers operating in a pulse width modulation mode helps to improve the uniformity of the luminous intensity of FED 10. Although only subpixels 50, 57, and The operation of 58 has been explained. It should be understood that the changes in the voltages of the other sub-pixel emitter nodes of FED 10, namely nodes 04, 105, 106, 107, 108, and 109, are symmetrically related to each other by The electron emitter structure of a specific node, that is, all the charges emitted by 24 (28 17), 24 (28,18), 24 (28,19), 24 (2917), 24 (29 18), 24 (29 19) And its operation is similar to that described for subpixels 60, 67, 68, 70, 77, and 78 It should be understood now that it uses both amplitude modulation and pulse width modulation to apply the Chinese National Standard (CNS) A4 specification (210X297 mm) to this paper size 518627 A7 B7 V. Description of the invention (17) Control its light emission Degree field emission displays are already available. The FED includes a control circuit containing a tri-state driver that monitors the voltage on the row conductor and uses pulse width modulation to control the current emitted from the electron emitter structure. In addition The control circuit includes an amplitude modulation part that controls the charging steps on the capacitors related to the row conductors. When a specific embodiment of the present invention has been disclosed and explained, those skilled in the art will produce additional Modifications and improvements. It is understood that the present invention is not limited to the specific format shown and that it is intended to be used in addition to the scope of the patent application to cover all modifications which leave the spirit and scope of the invention below. For example, columns and rows The conductor driver circuit can be implemented using a microprocessor. In addition, the row conductor driver circuit can be designed using changes in voltage The rate is consistent with the control of luminosity. -20- This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm)

Claims (1)

518627 Patent Application No. 090118461 Amendment to Chinese Patent Application Range (October 91) A B c D 6. Scope of patent application 1. A method for operating a field emission display. The field emission display has a plurality of rows of conductor emitter structures arranged thereon, and has a plurality of columns of conductors with holes inside. One of the conductor driver circuits is The first row of conductors coupled to one of the plurality of rows of conductors, and the plurality of rows of conductors and the plurality of rows of conductors cooperate to form a sub-pixel. The method includes: making a part of the electron emitter structure emit electrons, thereby defining an emission current, A change in a signal on at least one row of conductors of a row of conductors, thereby defining a measured voltage change; comparing an intensity voltage value with the measured voltage change, thereby defining an adjusted voltage value; and adjusting the emission current according to the adjusted voltage value An operating state of one of the structure of the electron emitter. 2. The method of claim 1, wherein causing the portion of the electron emitter structure to emit electrons includes applying a selection voltage to a column of conductors in a plurality of conductors. 3. A method as claimed in claim 1 in which causing the portion of the electron emitter structure to emit electrons includes arranging a row conductor driver circuit in a high impedance state. 4. The method according to item 1 of the patent application range, wherein measuring a change in signal on at least one conductor of a plurality of conductors includes a conductor voltage change. 5. The method according to item 4 of the patent application, wherein adjusting the operating state includes stopping at least one electron emitter structure. 6. For the method of the first scope of the patent application, the adjustment includes the use of the amplitude. The paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 518627 A8 B8 C8 D8. The scope of the patent application is adjusted to change. Electron emission from a predetermined electron emitter structure 0 7. The method of claim 6, wherein the adjustment includes using pulse width modulation to increase electron emission from a predetermined electron emitter structure. 8. The method of claim 7 in which the adjustment is performed during a single signal frame clock. 9. The method of claim 1 wherein the adjustment includes using pulse width modulation to increase electron emission from a predetermined electron emitter structure. 10. A method for operating a field emission display having a first conductor coupled to a second conductor via a first capacitor and a first conductor coupled to a third conductor via a second capacitor, one of which A first conductor drive circuit is coupled to the first conductor and a plurality of electron emitter structures are disposed on the first conductor and a second conductor drive circuit is coupled to the second conductor. The method includes: enabling a plurality of electron emitters The structure emits electrons, thereby defining an emission current, and stopping emission of electrons from the complex electron emitter structure when the emission current exceeds a predetermined current. 11. A field emission display comprising: a first conductor; a first conductor driver circuit coupled to the first conductor, the first conductor driver circuit can operate in a high impedance state; -2- this paper is applicable China National Standard (CNS) A4 specification (210 X 297 mm) 518627 A8 B8 C8 D8, patent application scope a second conductor, the second conductor is coupled to the first conductor via a first capacitor; a second conductor driver A circuit coupled to the second conductor; a third conductor coupled to the first conductor via a second capacitor; a third conductor driver circuit coupled to the third conductor; and a plurality of electron emitter structures Is disposed on the first conductor. -3- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm)