JPH01193797A - Spontaneous light emission type display device - Google Patents

Abstract

PURPOSE:To reduce the power consumption by controlling the display volume so that the increase of display volume is suppressed based on the detection output of a display volume detecting means. CONSTITUTION:The display volume of display data displayed on a plasma display panel 1 is finely detected by a display volume detecting means 37. The display volume of the plasma display panel 1, namely, the discharge time of a cell in the discharge state is finely controlled based on the detected display volume by a display volume control means 38. Consequently, the power consumption for the number of cells in the display state is gently changed. Thus, the power consumption is reduced without damaging the visual recognizability of display.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to self-luminous display devices such as plasma display devices, electroluminescence display devices, electrochemical display devices, fluorescent display tubes, and light emitting diode display devices.

[Summary of the invention]

The present invention provides a self-emissive display device having a self-emissive display and a drive circuit for driving the self-emissive display.
The drive circuit includes a display amount detection means for detecting the display amount of the self-luminous display, and a method for suppressing an increase in the display amount of the self-luminous display based on the detection output of the display amount detection means. By including display amount control means for controlling the display amount, power consumption can be reduced without impairing the visibility of the display of the self-luminous display.

[Conventional technology]

A conventional plasma display device suitable for applying the present invention will be described below.

First, with reference to FIG. 8, a plasma display panel used in a plasma display device will be described.

There are two types of plasma display panels: AC type and DC type.
The plasma display panel shown in FIG. 8 is of a DC type.

In Fig. 8, FGP is a transparent rectangular front glass plate,
RGP is a rectangular rear glass plate, and each of these
They are opposed to each other at a predetermined interval, and their peripheries are hermetically sealed. The airtight space formed by the front glass plate FGP and the rear glass plate RGP is filled with a mixed gas of Ne gas and Ar gas at a pressure of 450 Torr.

On the front glass plate FGP, eight thin strip-shaped anodes (x electrodes) are deposited in parallel at predetermined intervals, and barrier ribs BR are deposited between adjacent anodes A in parallel thereto. There is. This barrier rib BR has a thickness that is sufficiently larger than the thickness of the anode A.

Further, on the rear glass plate RGP, several sheet-like trigger electrodes TG are attached, each corresponding to a predetermined number of cathodes, which will be described later. An insulating layer (dielectric layer) IL is deposited on the trigger electrode GT.

Then, on this insulating layer IL, strip-shaped cathodes K are arranged in parallel at a predetermined interval so as to be perpendicular to the anode A and facing each other at a predetermined interval (equal to the thickness of the barrier rib BR, 100 μm). It is worn.

Trigger electrode TG is connected to this, cathode K and anode A.
A trigger discharge (a kind of AC type discharge) is caused between the anode A and the cathode, and this is used as a pilot flame to quickly start the discharge between the anode A and the cathode, thereby improving the contrast of the display.

Next, a conventional plasma display device (double tone type) using a plasma display panel as described with reference to FIG. 8 will be described with reference to FIG. 9. (1) shows the plasma display panel described in FIG. 8, and illustration of the trigger electrode TG is omitted here. This plasma display panel (1) has 400 cathodes K(1) to K(40
0) and 640 anodes A (1) to A (640)
are arranged so as to be orthogonal to each other, and a discharge cell (2) is formed at each intersection. In addition, the number of cathodes is 4.
There are cases where it is 80, in which case 1. Some frequencies of each signal differ from the values described below.

Next, a drive circuit (20) for driving this plasma display panel (1) will be explained. First, a cathode example circuit will be described. (3) is a 400-bit serial-in/parallel-out shift register. This shift register (3) receives 60H from the input terminal (4).
A vertical synchronizing signal of z is supplied as cathode shift data KSD, and a cathode shift clock KCK synchronized with a 25 kHz horizontal synchronizing signal (one period is 40 μsec) is supplied from the input terminal (5).
The cathode shift data KSD is shifted by K. The 400 cathode scanning pulses per vertical period, sequentially shifted by a predetermined phase, from the shift register (3) are supplied as a switching control signal to a high voltage cathode driver (switch circuit) (6). Then, the cathodes K(1) to K(40
0) is scanned sequentially and cyclically connected to ground at a frequency of 25 kHz.

Next, the anode side circuit will be explained.

(7) is a 640-bit serial-in/parallel-out shift register. This shift register (7)
, 1-bit display data DT is input from the input terminal (8).
is supplied, and from the input terminal (9), 21MHz
A data shift clock DSCK is supplied, and the display data DT is shifted by this clock DSCK.

The 640-bit parallel data from the shift register (7) is supplied to the latch circuit (10) and input to the input terminal (11).
) is launched every horizontal period by the latch clock (horizontal synchronization signal') LCK from .

The 640-bit parallel data from the launch circuit (10) is supplied as a switching control signal to 640 switch circuits of the high voltage anode driver (12). Then, depending on whether the 640-bit parallel data is 0.1 or not, and based on the time width that corresponds to the brightness adjustment of the output enable signal OE from the input terminal (13), A voltage of 200V is selectively supplied to (1) to A (640).

(18) is a trigger electrode drive circuit, which has an input terminal (
19) is supplied, a trigger electrode control signal is generated here, and this trigger electrode control signal is supplied to a trigger electrode TG (not shown).

Next, a conventional plasma display device (16 gradation type) using a plasma display panel as explained with reference to FIG.
will be explained with reference to FIG. (1) is the 8th
The plasma display panel described in the figure is shown, and illustration of the trigger electrode is omitted here. This plasma display panel (1) has 400 cathodes K(1) to K(40
0) and 640 anodes A(1) to A(640) are arranged perpendicularly to each other, and a discharge cell (2) is formed at each intersection. Furthermore, the number of cathodes is 480.
In some cases, the frequencies of some of the signals differ from the values described below.

Next, a drive circuit (20) for driving this plasma display panel (1) will be explained. First, the cathode side circuit will be explained. (3) is a 400-bit serial-in/parallel-out shift register. This shift register (3) receives 60
A Hz vertical synchronizing signal is supplied as cathode shift data KSD, and a cathode shift clock KCK synchronized with a 25 kHz horizontal synchronizing signal (one period is 40 μsec) is supplied from the input terminal (5).
The cathode shift data KSD is shifted by CK. The 400 cathode scanning pulses per vertical period, which are sequentially shifted by a predetermined phase from the shift register (3), are sent as switching control signals to the 400 on/off switches of the high voltage cathode driver (switch circuit) (6). Supplied. Then, this cathode driver (6) drives the cathodes K(1) to K(4).
00) are scanned sequentially and cyclically connected to ground at a frequency of 25 kHz.

Next, the anode side circuit will be explained.

(7) is a 640-byte (=640×4 bits) serial-in/parallel-out shift register.

From the input terminal (8) to this shift register (7),
Display data DT of 4 bits, that is, 16 gradations is supplied, and a 21 MHz data shift clock DSCK is supplied from the input terminal (9).
The display data DT is shifted by.

The 640x4 bit parallel data from the shift register (7) is supplied to the latch circuit (10) and input terminal (
11) is latched for one horizontal period by the launch clock (horizontal synchronization signal) LCK.

The 640x4 bit parallel data from this launch circuit (10) is transferred to a device width modulation circuit (17) consisting of a pulse width counter (15) and a pulse width comparison circuit (14).
is supplied to its pulse width comparison circuit (14). This pulse width comparison circuit (14) includes 640 pulse generators. A pulse width clock PWCK is supplied to the pulse width counter (15) from an input terminal (16). This pulse width clock PWCK has l horizontal period (40
It has a period that is 15 times slightly shorter than .mu.sec) and therefore has a frequency close to 25.times.15 kHz.

In addition, a pulse width counter (15) and a pulse width comparison circuit (
14) is supplied with a set pulse (a signal synchronized with a horizontal synchronizing signal) SP from an input terminal (21). and,
The pulse width counter (15) is cleared by this set pulse SP. Further, this cent pulse sp is supplied to the pulse generator of the pulse width comparison circuit (14).

Then, the 4-bit pulse width code signal (gray scale data) output from the pulse width counter (15) is supplied to the pulse width comparison circuit (14), and the 640 pulse width code signals from the 7,000 circuit (10) are supplied to the pulse width comparison circuit (14). The 4-bit and 2-bit display data are compared. Then, 6 of the pulse width comparison circuit (14)
Pulses are obtained from selected ones of the 40 pulse generators and are selectively supplied as switching control signals to the 640 on/off switches of the high voltage anode driver (12). And 6 within one horizontal period
A voltage of 200 cm is selectively supplied to the anodes A(1) to A(640) for a time corresponding to the pulse width of the 16th order (including 0) of the 40-dot pulse.

(18) is a trigger electrode drive circuit, which has an input terminal (
19), a vertical synchronization signal is supplied, and a trigger electrode control signal is generated here, and this trigger electrode control signal is
It is supplied to a trigger electrode TG (not shown).

[Problem to be solved by the invention]

However, such conventional plasma display devices have a problem in that their power consumption is larger than that of liquid crystal display devices and the like. This problem also applies to other self-luminous display devices.

In view of this point, the present invention seeks to propose a self-emissive display device that can reduce power consumption without impairing the visibility of the self-emissive display device.

[Means to solve the problem]

A first aspect of the present invention provides a self-emissive display device including a self-emissive display (1) and a drive circuit (20) for driving the self-emissive display (1), wherein the drive circuit (20) is , display amount detection means for detecting the display amount of the self-luminous display (1)
37), and display amount control means (38) for controlling the display amount of the self-luminous display (1) based on the detection output of the display amount detection means (37) so as to suppress an increase in the display amount of the self-luminous display (1).
It is equipped with the following.

A second aspect of the present invention is a self-emitting device based on the first aspect of the present invention, in which the display amount detection means (37) detects the electric power supplied from the power source (31) to the drive circuit (20) during a unit time. The display amount control means (38) is configured to detect the display amount of the mold indicator (1), and the display amount control means (38) is configured to detect the display amount detection means (
Based on the detection output of 37), the light emitting time of the self-luminous display device (1) is controlled so as to suppress an increase in the display amount of the self-luminous display device (1).

A third aspect of the present invention provides a display method based on the first aspect of the present invention, in which the display amount detection means (37) causes the self-luminous display (1) in the display data supplied to the drive circuit (20) to be in a light emitting state. The display amount of the self-luminous display (1) is detected by detecting the amount of data per unit time, and the display amount control means (38) is configured to detect the display amount of the self-emitting display (1) by detecting the amount of data per unit time.
Based on the detection output of 37), the light emitting time of the self-luminous display device (1) is controlled so as to suppress an increase in the display amount of the self-luminous display device (1).

[Effect]

According to the first to third aspects of the present invention, the display amount detection means (
Based on the detection output of 37), display amount control means (38)
Control the display amount of the self-luminous display (38) by
An increase in the display amount of the self-luminous display (1) is suppressed.

〔Example〕

Most of the power consumed in the plasma display device described above is consumed by the plasma display panel.

That is, when the display amount of the plasma display panel is Q and its power consumption is P, P becomes a function of Q, and the relationship is as follows.

P=f(Q) =αQ+Po... (1) However, α: Proportionality constant Po: Value of P at Q=Q Here, the display amount Q is the double positive plasma display shown in Figure 9. In the case of a device, the maximum value, that is, the display capacity Q cap of the plasma display panel, is proportional to the number N of cells in the discharge state (light emission state) of the plasma display panel.
The value is proportional to 640x400. In addition, in the case of the 16-story plasma display device shown in FIG.
is a value proportional to the sum of the display gradation numbers 0 to 15 of all cells of the plasma display panel.

Therefore, it can be seen that in order to reduce the power consumption of a plasma display panel, that is, a plasma display device, it is sufficient to reduce the display amount of the plasma display panel as much as possible.

In the case of a plasma display panel, - For fishing on a boat, in order to reduce the display amount, it is sufficient to shorten the discharge time of the cells in the discharge state (light-emitting state). However, when the number of cells in the discharge state of a plasma display panel is small, shortening the discharge time of the cells in the discharge state will impair the visibility of the display, but the number of cells in the discharge state will decrease. When the amount of discharge is relatively high, the visibility of the display will not be lost even if the discharge time of the cells in the discharge state is shortened.

Therefore, embodiments of the present invention that take these points into consideration will be described below.

First, with reference to FIG. 1, an embodiment will be described in which the present invention is applied to a double positive type plasma display device as described with reference to FIG. In FIG. 1, parts corresponding to those in FIGS. 8 to 10 described above will be described with the same reference numerals.

(31) is a 200μ high voltage DC power supply, its positive terminal is connected to the anode driver (12) through a low resistance resistor (32) for current detection, and its negative terminal is grounded together with the cathode driver (6). Ru.

A detector (33) is connected to both ends of the resistor (32) to detect the voltage across the resistor (32) and detect the current flowing through the resistor (32). The detection output of this detector (33) is then supplied to an integrating circuit (34) and integrated. The resistor (32), the detector (33), and the integrating circuit (34) constitute a display amount output means (37).

The output of this integrating circuit (34) is then supplied to the voltage controlled oscillator (35) as an oscillation frequency control signal.

The oscillation output of this oscillator (35) is generated by the pulse generation circuit (3
6). This pulse generation circuit (36) generates a pulse having a time width corresponding to the oscillation cycle of the oscillation unit (35). The pulse from this pulse generation circuit (36) is used as an output enable signal at the input terminal (13).
) is supplied to the anode driver (12). These voltage controlled oscillators (35) and pulse generation circuits (
36) and the anode driver (12) constitute display amount control means.

Next, the operation of this embodiment will be explained. Integrating circuit (34
) outputs the detection output of the detector (33) over the display data period of one frame period, for example, every several hundred frames (one frame = one field) according to the control signal from the input terminal (34a). is integrated and the value is held for a period of several hundred frames. When this integrating circuit (34) starts an integrating operation, this integrating circuit (34) is reset by a reset pulse synchronized with the vertical synchronizing signal from the input terminal (34a). From then on, this operation is repeated.

Now, if the number of cells in which a discharge is occurring is W, and the on-time of the switch during one horizontal period when the N1 anode driver (12) is turned on is W, and the proportionality constant is k, then the display amount Q is expressed as follows. be done.

Q=kxNxW ・ ・ ・ ・ ・ ・ ・ ・ ・
- (2) Therefore, the above-mentioned equation (1) can be expressed as follows, assuming po=o.

P=αXkXNXW... (3) Discharge condition of plasma display panel (1)! The maximum value of the number N of cells in the 3 (light emitting state) is Nmax (in the case of Figure 9, Nm
ax = 640X400), and the number N is from O to Nmax
/2 (for example, when displaying orange text on a black background),
The on time W within one horizontal period of the switch that turns on the anode driver (12) is set to the maximum time width Wmax (in this case, Q = k x N x Wmax, and p
= α x k
ax (for example, when the display is reversed, that is, when black characters are displayed on the ground), the anode driver (12) is turned on according to the increase in the number N of cells in the discharge state (light-emitting state). By shortening the on time W within one horizontal cycle period, the display amount Q is set to a constant value Qcap.
/ 2 (However, Qcap is a plasma display panel (1
), i.e. display capacity) (in this case, kXN
XW=Qcap/2), that is, P is αx
Keep at Qcap/2.

Furthermore, when the number N of cells in the discharge state of the plasma display panel (1) is from O to Nmax/2 (for example, when orange characters are displayed on a black background), the anode driver (12)
The on time W within one horizontal cycle period of the switch that turns on
to the maximum time width Wmax (in this case, Q=kxN
At XWmax, with p=αX1(XNXWmax),
When the number N of cells in the discharge state exceeds Nmax / 2 and reaches Nmax (for example, when the display is reversed, that is, when black characters are displayed on the ground), as the number N increases,
The ON time within one horizontal period of the switch that turns on the anode driver (12) is shortened so that the display iQ satisfies, for example, Q=(1/2)kxNxW, that is, P is P= (1/2)αXkXNXW
The display amount Q is kept below a certain value.

In addition, when applying the idea of the embodiment of FIG. 1 to the plasma display device of FIG. 10, in the embodiment of FIG. The output may be supplied to the pulse width counter (15) in FIG. 10 as the pulse width clock PWCK.

Next, another embodiment will be described with reference to FIG. OR
The n-bit display data DT is supplied to the gate (42). In the case of a double positive type plasma display device as shown in FIG. 9, n is l, so the OR gate (42) is not necessary. The output of the OR gate (42) is a NAND game)
(43). Also, this NAND gate (43
) is also supplied with a 21 MHz dot clock DCK.

The output of this NAND gate (43) is then supplied as a clock to an n-bit counter (41) and counted. Also, the vertical synchronization signal VD is supplied to this counter (41) as a clear signal. Of the n-bit output of the counter (41), for example, MSB to MS
The 4-bit output of B-3 is connected to a 4-bit latch circuit (4 bits).
4) and is latched every vertical period by the vertical synchronizing signal VD. Note that the number of bits n of the counter (41) is equal to the maximum value Nmax (=6
40×400) is selected to be a value between 2 to the n-1 power and 2 to the n power.

Moreover, the reason why the output of the upper 4 bits of the counter (41) is supplied to the latch circuit (44) is to roughly detect the display amount of the plasma display panel (1).
This is to simplify the circuit configuration. Thus, the display amount detection means (37) is composed of the OR game (42), the NAND gate (43), the counter (41), and the launch circuit (44).

The 4-bit output of the latch circuit (44) is sent to the data selector (45) as data selection control signals A3 A2 A, A,
Supplied closed. By the data selector (45),
The selected data is 16 data DO%DI ~DI
5. Then, an output enable signal OE is obtained as an output of the data selector (45), and the anode driver (12) of FIG. 1, which is not shown in FIG.
is supplied to the input terminal (13) of. Then, in this data selector (45) and anode driver (12),
A display amount control means (38) is configured.

Next, the operation of this embodiment will be explained with reference to FIGS. 3 and 4. FIG. 3 shows the on-time W within one horizontal cycle period (IH) of the switch that turns on the anode driver (12), that is, Wo, WI, ..., W8 (however, W□ = Wmax > Wl＞・・・・・・＞W6=
Pulse P O% P with Wn+ax/2)
1, . . . , P8 are prepared, and the data selector (45)
supply to.

Do ”'Dt = ... = 07 = P (ID8 = P
.

D9=P2 Dis"'pH+ FIG. 4 shows that the on-time W within one horizontal cycle period (IH) of the switch that turns on the anode driver (12) is WO% Wl, ..., W8, respectively. The relationship between the number N of cells in the discharge state of the plasma display panel (1) and the power consumption P (W) in the case of FIG.

Then, depending on the control signals A3, A2, A, and A supplied to the data selector (45), the anode driver (12) is turned on in one horizontal cycle (IH) of the switch.
The on time W within the period is determined as follows.

That is, the number N of cells in the discharge state (light emitting state) is 0 to 8.
When Nmax/16, W of p=αXkXW×N is fixed to Wo, and after that, each time N increases by Nmax/16, W of P=αxkxNxW is set to N'/+ "'W6
(=WO/2), and the gradient is gradually lowered. Thus, the data selector (4
5), the pulse P is output as the output enable signal OE. , P1 to P8 are output, and the on time W is W.

, W1 to W8.

Therefore, the display amount Q is below Qcap/2, that is, P
is suppressed to below P=(α/2)×Qcap.

FIG. 3 shows that when rloooJ is supplied as the selection control signal A3A2A1Ao supplied to the data selector (45), the output of the data selector (45), that is, the output enable signal OE, is the pulse P1. ing.

FIG. 5 shows a cell in a discharge state when the on-time W within one horizontal period (IH) of the switch that turns on the anode driver (12) is Wo, W1, ..., Wl, respectively. Another example of the relationship between the number N and power consumption P will be shown. In this case, the number N is from 0 to Nmax/8, then Nmax
For every x/8, the time W of P=α×kxWxN is
, WI, ..., Wl, and the slope becomes gradually gentler, and the display amount Q is k
Keep P below x, that is, keep P αx k x Wl X
It can be suppressed to below Ntaax. Note that illustration and description of the configuration of the embodiment in this case will be omitted.

In the embodiment shown in FIG. 2 described above, the display amount detection means (37
) detects in detail the display amount of display data to be displayed on the plasma display panel (1), and based on this, the display amount of the plasma display panel (1) is determined by the display amount control means (38), that is, the cells in the discharged state. By finely controlling the discharge time of , it is possible to smooth the change in power consumption with respect to the number N of cells in the display state in FIGS. 4 and 5.

Display amount detection means (37) in the embodiment shown in FIG. 2 above
As shown in FIG. 6, a part of the circuit can be made into an analog circuit. That is, the display data DT supplied to the input terminal (51) is controlled every several hundred frames over the display data period of one frame period based on the control signal supplied to the input terminal (53). Through the on/off switch (52), which is turned on when 55)
and converts it into n-bit digital data. Then, of the n-bit data of the A/D converter (55), for example, the upper 4 bits of data are supplied to the launch circuit (44), and the launch circuit (44) is launched for one vertical period by the vertical synchronization signal VD, and its output is The data is supplied to a data selector (45) similar to that shown in FIG. Note that the operation of this embodiment is substantially the same as that of the embodiment shown in FIG. 2, so a description of the operation will be omitted.

Next, the operation of the embodiment shown in FIG. 2 when the present invention is applied to the 16-story plasma display device explained in FIG. 10 is as follows.
This will be explained with reference to FIG. Data DOSDI,..., D to be supplied to the data selector (45) and selected
The period of I5 is one horizontal period (IH) as shown in Figure 7.
Within, D.

It is the same for ~D6, and becomes gradually shorter from D6 to DI5. Then, selection control signal A
3A2A, Ao, these data Do, D1,...
, DI5 is selected and supplied to the pulse width counter (15) of the plasma display device shown in FIG. 10 from its input terminal (16). Also, the anode driver (
14) includes a set pulse SP synchronized with the horizontal synchronization signal.
is supplied. Then, according to the 640 pieces of 4-bit display data DT supplied to the shift register (7), the leading edge matching the trailing edge of the cent pulse SP and the selected data DO% DI, . . . A pulse having a trailing edge that coincides with the trailing edge of each pulse in DI5 is output from the pulse width comparator circuit (14), which in turn is connected to the anode driver (14).
2) is supplied to each switch. In FIG. 7, when the selection control signals A3 A2A and AO are rloooJ,
Data D8 is selected by the data selector (45) and generated based on this, and the anode driver (12)
It shows pulses GSI-GSN supplied to each switch.

Then, the data selector (45) selects the discharge state of the plasma display panel (1)! If the number N of cells in the 3 (light emitting state) is, for example, less than Nmax/2, the unit time (l) of the on period W of the switch of the anode driver (12)
111 adjustment time) is maximized, and the unit time of the on-period W is gradually shortened from exceeding Nraax/2 to Nmax.

In each of the above embodiments, the display amount is controlled by controlling the on-time of each switch of the anode driver. This may be done by controlling the time.

Furthermore, in the above embodiment, the power consumption was controlled by controlling the discharge time (light emitting time) of the cell, but depending on the type of self-emissive display device, the power consumption may be controlled by changing the voltage applied to the cell. You can also.

〔Effect of the invention〕

According to the present invention described above, it is possible to obtain a self-luminous display device that can reduce power consumption without impairing display visibility.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention, FIG. 2 is a block diagram showing another embodiment, FIG. 3 is a timing chart for explaining the embodiment, and FIGS. 4 and 5 6 is a block diagram showing still another embodiment of the present invention, FIG. 7 is a timing chart for explaining the embodiment, and FIG. 8 is a conventional plasma display. FIG. 9 is a block diagram showing a conventional double-toned plasma display device, and FIG. 10 is a block diagram showing a conventional 16-gradation plasma display device. (1) is a plasma display panel, (20) is a drive circuit, (
37) is a display amount detection means, and (38) is a display amount control means. Actual self-example (Figure 1 Timing 7' Officer Yard Figure 3 Student / 1
Figure 5 Diagram 6. !

Claims (1)

[Claims] 1. In a self-emissive display device having a self-emissive display and a drive circuit that drives the self-emissive display, the drive circuit controls the display amount of the self-emissive display. and display amount control means for controlling the display amount of the self-luminous display so as to suppress an increase in the display amount of the self-luminous display based on the detection output of the display amount detection means. A self-luminous display device characterized by: 2. In a self-emissive display device having a self-emissive display and a drive circuit that drives the self-emissive display, the drive circuit is configured to: A display amount detecting means for detecting the display amount of the self-luminous display, and an increase in the display amount of the self-luminous display based on the detection output of the display amount detecting means. 1. A self-luminous display device comprising: a display amount control means for controlling the light emission time of the self-luminous display device. 3. In a self-emissive display device having a self-emissive display device and a drive circuit that drives the self-emissive display device, the drive circuit may detect the self-emissive type in the display data supplied to the drive circuit. Display amount detection means for detecting the display amount of the self-luminous display by detecting the amount of display data that causes the display to emit light during a unit time, and based on the detection output of the display amount detection means. A self-luminous display device comprising: display amount control means for controlling the light emitting time of the self-luminous display device so as to suppress an increase in the display amount of the self-luminous display device.