WO2002021492A1 - Field emission display and method - Google Patents
Field emission display and method Download PDFInfo
- Publication number
- WO2002021492A1 WO2002021492A1 PCT/US2001/023408 US0123408W WO0221492A1 WO 2002021492 A1 WO2002021492 A1 WO 2002021492A1 US 0123408 W US0123408 W US 0123408W WO 0221492 A1 WO0221492 A1 WO 0221492A1
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- WO
- WIPO (PCT)
- Prior art keywords
- conductor
- electron emitter
- column
- coupled
- row
- Prior art date
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Classifications
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0275—Details of drivers for data electrodes, other than drivers for liquid crystal, plasma or OLED displays, not related to handling digital grey scale data or to communication of data to the pixels by means of a current
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/02—Improving the quality of display appearance
- G09G2320/029—Improving the quality of display appearance by monitoring one or more pixels in the display panel, e.g. by monitoring a fixed reference pixel
Definitions
- the present invention relates, in general, to field emission displays and, more particularly, to methods and circuits for controlling emission current in field emission displays.
- a field emission display includes an anode plate and a cathode plate that define a thin envelope.
- the cathode plate * includes a matrix of column conductors and row conductors, which are used to cause electron emission from electron emitter structures such as, Spindt tips.
- FED's further include ballast resistors between the electron emitter structures and the cathode plate for controlling the electron emission current.
- the ballast resistors have resistance values greater than ten megohms . Because of the high resistance values, the ballast resistors are difficult to fabricate and are highly temperature sensitive, which results in uneven current emission from the electron emitter structures over temperature. Another drawback encountered with field emission displays is differential aging of the electron emission structures.
- FIG. 1 is a partially cut-away isometric view and circuit schematic representation of a field emission display in accordance with an embodiment of the present invention
- FIG. 2 is an equivalent circuit representation of the field emission display of FIG. 1;
- FIG. 3 is a circuit diagram of a column conductor driver circuit of FIG. 1 in accordance with the present invention.
- FIG. 4 is a timing diagram for the operation of the field emission display of FIG. 1.
- the present invention includes a method and a field emission display for maintaining a uniform emission current over the operating lifetime of the display.
- the method includes using column conductor driver circuits to drive the column conductors of an FED and row conductor driver circuits to drive the row conductors of the FED, wherein the column conductor driver circuits place a high voltage, or a low voltage, or a high impedance state on the column conductors.
- the column conductor driver circuit when the column conductor driver circuit is in a high impedance state it monitors the voltage on the column conductor to which it is coupled.
- the FED When the column conductor driver circuits and the row conductor driver circuits output approximately zero volts, the FED is off.
- the column conductor driver circuit When the column conductor driver circuit is in a high impedance state and a row conductor is at a high voltage level the sub-pixel associated with that row conductor and column conductor transmit an emission current.
- the voltage at which a particular row conductor turns on the sub-pixel is referred to as a row select voltage.
- the voltage on the column conductor associated with the electron emitter structures that are emitting electrons rises. This voltage rise or change is monitored by the column conductor driver circuit and compared with a predetermined voltage. This predetermined voltage is also referred to as an intensity voltage value and may be determined when the display is started.
- the column conductor driver output is switched from a high impedance state to a high voltage state to adjust the operating state of the electron emitter structures.
- the electron emitter structures and therefore the sub-pixels are turned off.
- the turning on and off of the pixels occurs in a single frame time.
- the column conductor driver circuit is capable of operating in both an amplitude modulation (AM) mode and a dynamic pulse width modulation (PWM) mode.
- AM amplitude modulation
- PWM dynamic pulse width modulation
- the capacitances associated with the column conductors are charged and discharged to pre-selected levels.
- AM amplitude modulation
- PWM pulse width modulation
- the PWM mode stronger emitting sub-pixels have pulse widths that are shorter than a nominal pulse width and weaker emitting sub- pixels have pulse widths that are longer.
- FIG. 1 is a partially cut-away isometric view and circuit schematic representation of a field emission display (FED) 10 in accordance with an embodiment of the present invention.
- FED 10 includes an FED device 11 and control circuitry 12 for controlling emission current in FED device 11.
- FED device 11 includes a cathode plate 13 and an anode plate 14.
- Cathode plate 13 includes a substrate 16, which can be made from glass, silicon, and the like.
- a first column conductor 17, a second column conductor 18, and a third column conductor 19 are disposed on substrate 16.
- a dielectric layer 21 is disposed upon column conductors 17, 18, and 19, and further defines a plurality of wells 22.
- An electron emitter structure 24 such as, for example, a Spindt tip, is disposed in each of wells 22.
- Row conductors 27, 28, and 29 are formed on dielectric layer 21. Row conductors 27, 28, and 29 are spaced apart from and proximate to electron emitter structures 24. Row conductors 27, 28, and 29 include a plurality of apertures 30 which cooperate with corresponding wells 22 and electron emitter structures 24 to form current emission regions 31. Column conductors 17, 18, and 19 and row conductors 27, 28, and 29 are used to selectively address electron emitter structures 24.
- FIG. 1 depicts only three row and column conductors. However, it is desired to be understood that any number of row and column conductors can be employed.
- An exemplary number of row conductors for an FED device is 240 and an exemplary number of column conductors is 960.
- Methods for fabricating cathode plates for matrix-addressable field emission displays are known to one of ordinary skill in the art.
- Anode plate 14 is disposed to receive an emission current 32, which is defined by the electrons emitted by electron emitter structures 24.
- Anode plate 14 includes a transparent substrate 33 made from, for example, glass.
- An anode 34 is disposed on transparent substrate 33.
- Anode 34 is preferably made from a transparent conductive material, such as indium tin oxide.
- anode 34 is a continuous layer that opposes the entire emissive area of cathode plate 13. That is, anode 34 preferably opposes the entirety of electron emitter structures 24.
- a plurality of phosphors 36 is disposed upon anode 34. Phosphors 36 are cathodoluminescent . Thus, phosphors 36 emit light upon activation by emission current 32.
- control circuitry 12 comprises row conductor driver circuits 37, 38, and 39 and column conductor driver circuits 47, 48, and 49.
- Row conductor driver circuits 37, 38, and 39 are coupled to row conductors 27, 28, and 29, respectively, and column conductor driver circuits 47, 48, and 49 are coupled to column conductors 17, 18, and 19, respectively.
- FIG. 2 is a schematic diagram of FED 10. What is shown in FIG. 2 is a schematic representation of column conductors 17, 18, and 19, column conductor driver circuits 47, 48, and 49, row conductors 27, 28, and 29, and row conductor driver circuits 37, 38, and 39. It should be understood that although only three row conductor driver circuits and three column conductor driver circuits are shown, there may be more or fewer row conductor driver circuits and more or fewer column conductor driver circuits.
- FIG. 2 further illustrates electron emitter structures, sub-pixel capacitances, and ballast resistors associated with each row and column conductor of FED 10. More particularly, sub-pixel capacitance 51, sub-pixel ballast resistor 52, an electron emitter structure 24 (2717) associated with sub-pixel 50 are shown as being coupled to row conductor 27 and column conductor 17. Electron emitter structure 24 ⁇ 27 ⁇ l7) is shown as a lumped element representing all the electron emitter structures associated with sub-pixel 50. It should be understood that the reference number 24 has been used to identify electron emitter structures in general. To help explain the embodiment shown in FIG. 2, the electron emitter structures have been further defined by appending subscripts to reference number 24.
- the electron emitter structures associated with row conductor 27 and column conductor 17 have been identified by reference number 24 (27
- the electron emitter structures associated with row conductor 28 and column conductor 17 have been identified by reference number 24 (2817)
- the electron emitter structures associated with row conductor 27 and column conductor 18 have been identified by reference number 24 (2718)
- Sub-pixel capacitance 53, sub-pixel ballast resistor 54, and electron emitter structure 24 (28 associated with sub-pixel 57 are shown as being coupled to row conductor 28 and column conductor 17.
- Electron emitter structure 24 (2817) is shown as a lumped element representing all the electron emitter structures associated with sub-pixel 57.
- Sub-pixel capacitance 55, sub-pixel ballast resistor 56, and electron emitter structure 24 (2 . (17) associated with sub-pixel 58 are shown as being coupled to row conductor 29 and column conductor 17.
- Electron emitter structure 24 (2917) is shown as a lumped element representing all the electron emitter structures associated with sub-pixel 58.
- Sub-pixel capacitance ' 61, sub-pixel ballast resistor 62, and electron emitter structure 24 (2718) associated with sub-pixel 60 are shown as being coupled to row conductor 27 and column conductor 18. Electron emitter structure 24 (2718) is shown as a lumped element representing all the electron emitter structures associated with sub-pixel 60.
- Sub-pixel capacitance 63, sub-pixel ballast resistor 64, and electron emitter structure 24 (28 8) associated with sub-pixel 67 are shown as being coupled to row conductor 28 and column conductor 18. Electron emitter structure 24 (2818) is shown as a lumped element representing all the electron emitter structures associated with sub-pixel 67. Sub-pixel capacitance 65, sub-pixel ballast resistor 66, and electron emitter structure 24 ( 8) associated with sub-pixel 68 are shown as being coupled to row conductor 29 and column conductor 18. Electron emitter structure 24 (2918) is shown as a lumped element representing all the electron emitter structures associated with sub-pixel 68.
- Sub-pixel capacitance 71, sub-pixel ballast resistor 72, and electron emitter structure 24 (27 _ 19) associated with sub-pixel 70 are shown as being coupled to row conductor 27 and column conductor 19.
- Electron emitter structure 24 (2719) is shown as a lumped element representing all the electron emitter structures associated with sub-pixel 70.
- Sub-pixel capacitance 73, sub-pixel ballast resistor 74, and electron emitter structure 24 (28 ⁇ 9) associated with sub-pixel 77 are shown as being coupled to row conductor 28 and column conductor 19.
- Electron emitter structure 24 (2819) is shown as a lumped element representing all the electron emitter structures associated with sub-pixel 77.
- Sub-pixel capacitance 75, sub-pixel ballast resistor 76, and electron emitter structure 24 (29 ⁇ l9) associated with sub-pixel 78 are shown as being coupled to row conductor 29 and column conductor 19. Electron emitter structure 24 (2919) is shown as a lumped element representing all the electron emitter structures associated with sub-pixel 78.
- each column conductor driver circuit 47 is shown.
- each circuit block 47, 48, and 49 comprises the circuit structure shown in- FIG. 3.
- Column conductor driver circuits 47, 48, and 49 each include a sample and hold circuit 80, a comparator 81, a driver control circuit 82, a tri-state driver 83, a one-stage serial-to-parallel converter 87, and a calibration circuit 88.
- an input terminal 84 is coupled for receiving an analog video signal, VID A .
- An output terminal 85 of sample and hold circuit 80 is coupled to a non-inverting input terminal 86 of comparator 81.
- An output terminal 87 of comparator 81 is coupled to an input terminal 111 of driver control circuit 82.
- Driver control circuit 82 includes an amplitude modulation portion 93 and a pulse width modulation portion 94.
- An output terminal 89 of driver control circuit 82 is coupled to an input terminal 90 of tri-state driver 83.
- An output terminal 91 is commonly coupled to inverting input terminal 92 of comparator 81 and to the column conductors as shown in FIG. 2.
- An input terminal 95 of calibration circuit 88 is coupled for receiving a start signal and an output terminal 96 of calibration circuit 88 is coupled to a control terminal 97 of comparator 81.
- An output terminal 98 of calibration circuit 88 is coupled to an input terminal 99 of one-stage serial-to-parallel converter 87.
- Another input terminal 101 of one-stage serial-to-parallel converter 87 is coupled for receiving a serial input from channel n-1.
- An output terminal 102 of one-stage serial-to-parallel converter 87 is coupled to an input terminal 103 of driver control circuit 82 and as a serial output for coupling to channel n+1.
- An output terminal 110 of one-stage serial-to-parallel converter 87 is connected to input terminal 111 of driver control circuit 82.
- calibration circuit 88 transmits a reference signal to comparator 81 via control ⁇ terminal 97.
- calibration circuit 88 cycles display 10 to display a full white screen.
- the rows of display 10 are sequentially selected by sequentially activating row conductor driver circuits 37, 38, and 39.
- row conductor driver circuit 37 When row conductor driver circuit 37 is selected, it activates row conductor 27, while calibration circuit 88 enables driver control circuit 82 to turn on the sub-pixels coupled to row conductor 27.
- row conductor driver circuit 37 places about eighty volts on row conductor 27 and column conductor driver circuits 47, 48, and 49 place about zero volts on column conductors 17, 18, and 19, respectively, thereby causing sub-pixels 50, 60, and 70 to conduct current.
- each sub-pixel emits a sufficient current to create a white signal .
- the voltage appearing at the output of the column driver circuit is greater than the reference voltage V REF causing the comparator to trip.
- a logic high or one voltage level is stored in serial-to-parallel converter 87.
- serial-to-parallel converter 87 for that sub-pixel.
- this serial information is streamed out of the column driver register and stored in external memory (not shown) .
- the intensity or luminance information of sub-pixels 50, 60, and 70 is streamed into register 87. The information is then transmitted to the external memory.
- next row is then selected and the process continues until all the sub-pixels have been characterized as a strong pixel or a weak pixel. In this way, the entire display is mapped one line at a time, with one bit being output for each sub-pixel.
- This mapping takes one frame time, i.e., one-sixtieth of one second.
- the data stored in memory is appended to the proper digital video byte data as it streams into the display.
- the column driver circuits know, for each row scanned, whether the sub-pixel to be displayed is a strong or a weak sub-pixel. For example, if a logic one is appended to the digital video byte, the sub-pixel is a strong emitting sub-pixel, whereas if a logic zero is appended to the digital video byte, the sub-pixel is a weak emitting sub-pixel.
- FIG. 4 is a timing diagram 100 illustrating a method for operating FED 10 in a display mode.
- the display mode is characterized by the creation of a display image at anode 14. It should be understood that timing diagram 100 shown in FIG. 4 will be described together with FIGS. 1, 2, and 3. Represented in FIG. 4 is the selective addressing and activation of sub-pixels 50, 57, and 58. It should be understood that subpixels 60, 67, 68, 70, 77, and 78 can be selected in a similar fashion by activating row conductor driver circuits 48 and 49.
- all of the display capacitances are discharged to zero volts by driving the output voltage of column conductor driver circuits 47, 48, and 49 and row conductor driver circuits 37, 38, and 39 to a voltage lower than the threshold voltage of the corresponding electron emitter structures.
- the output voltages of column conductor driver circuits 47, 48, and 49 and the output voltages of row conductor driver circuits 37, 38, and 39 are driven to zero volts.
- nodes 101, 102, 103, 104, 105, 106, 107, 108, and 109 are driven to zero volts.
- capacitances 51, 53, 55, 61, 63, 65, 71, 73, and 75 each are at a voltage of substantially zero volts.
- timing diagram 100 only shows column conductor driver circuit 47 being placed in high impedance state.
- Row conductor driver circuits 37, 38, and 39 are then sequentially activated as indicated in timing diagram 100 shown in FIG. 4.
- row conductor driver circuits 37, 38, and 39 are outputting, for example, zero volts. This places zero volts on row conductors 27, 28, and 29, respectively.
- the outputs of column conductor driver circuits 47, 48, and 49 remain in a high impedance state.
- row conductor driver circuit 37 is activated and places a voltage greater than the -, threshold voltage of the electron emitter structures on row conductor 27.
- the voltage placed on row conductor 27 is eighty volts.
- Row conductor driver circuits 38 and 39 continue to maintain row conductors 28 and 29, respectively, at zero volts .
- capacitances 53 and 55 are effectively in parallel and have an effective capacitance denoted by C effl7 .
- C effl7 an effective capacitance
- the capacitance value of effective capacitance C effl7 is typically much larger than that of capacitance 51.
- the ballast resistors 54 and 56 are effectively in parallel and have an effective resistance value denoted R effl7 , which is typically much less than that of resistance value 52. More particularly, the effective capacitance and the effective resistance values C e£fl7 and R effl7 , respectively, are given by:
- C e££17 represents the lumped capacitance associated with the (n-1) row conductors coupled to column conductor 17 that are at zero volts;
- C actl7 represents the capacitance associated with a single activated row conductor coupled to column conductor 17 ;
- R e££17 represents the lumped ballast resistance associated with the (n-1) row conductors coupled to column conductor 17 that are at zero volts;
- R act i 7 represents the ballast resistance associated with a single activated row conductor coupled to column conductor 17; and
- n is the number of row conductors of FED 10.
- each column conductor has a similar effective capacitance and effective ballast resistance associated therewith.
- the effective capacitance and effective ballast resistance associated with column conductor 18 when all but one of the row conductors is activated is given by:
- C e££18 represents the lumped capacitance associated with the (n-1) row conductors coupled to column conductor 18 that are at zero volts;
- C actl8 represents the capacitance associated with a single activated row conductor coupled to column conductor 18;
- R e£fl8 represents the lumped ballast resistance associated with the (n-1) row conductors coupled to column conductor 18 that are at zero volts;
- R actl8 represents the ballast resistance associated with a single activated row conductor coupled to column conductor 18; and
- n is the number of row conductors of FED 10.
- C e£fl9 represents the lumped capacitance associated with the (n-1) row conductors coupled to column conductor 19 that are at zero volts;
- C actl9 represents the capacitance associated with a single activated row conductor coupled to column conductor 19;
- R ef£ i 9 represents the lumped ballast resistance associated with the (n-1) row conductors coupled to column conductor 19 that are at zero volts;
- R e££19 represents the ballast resistance associated with a single activated row conductor coupled to column conductor 19; and n is the number of row conductors of FED 10.
- capacitances 51 and C e££17 form a capacitive voltage divider network. Because the capacitance value of capacitance C e££17 is much larger than that of capacitance 51, the voltage at node 101 remains at about zero volts and essentially all of the voltage from row conductor driver circuit 37 appears across capacitance 51. If the voltage on the row conductor is greater than the threshold voltage of electron emitter structure 24 (2717) , electron emitter structure 24 (2717) emits electrons, thereby discharging capacitance 51 and charging effective capacitance C a££17 .
- the voltage at node 101 increases, reducing the voltage across electron emitter structure 24 (27 ⁇ l7) .
- the voltage across electron emitter structure 24 (2717) decreases to a value less than the threshold voltage, it stops emitting electrons, i.e., turns off.
- Comparator circuit 81 (shown in FIG. 3) cooperates with output terminal 91 to monitor the voltage on the column conductors when the column conductor driver circuits are in a high impedance state and the electron emitter structures are emitting current.
- the change in voltage measured on the column conductor is proportional to the charge emitted by the electron emitter structures.
- column conductor driver circuit 47 compares the' measured change in voltage on column conductor 17 to a voltage proportional to the desired intensity of sub-pixel 50, which proportional voltage was previously determined as described with reference to FIG. 2.
- Column conductor driver circuit 47 shuts off sub-pixel 50 after the proper amount of charge has been emitted.
- C actl7 is the capacitance associated with an activated row conductor coupled to column conductor 17;
- ⁇ V 101 is the change in voltage at node 101.
- Column conductor driver circuit 47 includes an amplitude modulation portion 93 so that capacitance 51 is discharged to a pre-selected voltage rather than zero volts.
- a column conductor with a strong sub-pixel i.e., a strong electron emitter structure
- •' • is discharged to a positive voltage, reducing the emitted current that is discharged compared to the amount discharged when capacitance 51 is at a discharge voltage of zero volts.
- a column conductor with a weak emitting sub-pixel, i.e., a weak electron emitter structure is discharged to zero volts.
- Determination of which electron emitter structures are strong or weak may be performed when powering FED 10 by, for example, displaying a single frame of full white and determining which electron emitter structures switch or trip the comparator circuit. Those that do are strong electron emitter structures and those that do not are weak electron emitter structures. The locations of the strong and weak electron emitting structures may be stored in a memory location.
- the electron emitter structure 24 (2717) has emitted the desired current, it is turned off by switching column conductor driver circuit 47 from the high impedance state to a high voltage state. This is shown as time t 3 in FIG. 4. During this time, the voltage at node 101 increases because capacitance C effl7 begins charging when the output voltage of column conductor driver circuit 47 is switched to the high voltage state.
- the output voltage of row conductor driver circuit 37 is switched from a high voltage, e.g., eighty volts, to a low voltage, e.g., zero volts; thereby discharging capacitances 51, 53, and 55 associated with column conductor 17.
- column conductor driver circuit 47 is placed in a high impedance state and the output voltage of row conductor driver circuit 38 transitions from a low voltage state, e.g., zero volts, to a high voltage state, e.g., eighty volts.
- Column conductor driver circuit 47 monitors the voltage on column conductor 17 and electron emitter structure 24 (2817) emits current.
- Column conductor driver circuit 47 compares the measured change in voltage on column conductor 17 to a voltage proportional to the desired intensity of sub- pixel 57, which proportional voltage was previously determined as described with reference to FIG. 2.
- Column conductor driver circuit 48 shuts off sub-pixel 57 after the proper amount of charge has been emitted. For sub-pixel 57, when electron emitter structure 24 (2817) is emitting current, the change in charge at node 104 is given by the relationship:
- q is the total charge emitted by electron emitter structure 24 (2817) ;
- C actl7 is the capacitance associated with an activated row conductor coupled to column conductor 17;
- ⁇ V ⁇ 0 is the change in voltage at node 104.
- the electron emitter structure 24 (2817) After the electron emitter structure 24 (2817) has emitted the desired current, it is turned off by switching column conductor driver circuit 47 from the high impedance state to a high voltage state. This is shown as time t 6 in FIG. 4.
- the output voltage of row conductor driver circuit 38 switches from a high voltage, e.g. eighty volts, to a low voltage, e.g., zero volts; thereby discharging capacitances 51, 53, and 55 associated with column conductor 17.
- column conductor driver circuit 47 is placed in a high impedance state and the output voltage of row conductor driver circuit 39 transitions from a low voltage state, e.g., zero volts, to a high voltage state, e.g., eighty volts.
- Column conductor driver circuit 47 monitors the voltage on column conductor 17 and electron emitter structure 24 (2917) emits current.
- Column conductor driver circuit 47 compares the measured change in voltage on column conductor 17 to a voltage proportional to the desired intensity of sub- pixel 58, which proportional voltage was previously determined as described hereinbefore.
- Column conductor driver circuit 47 shuts off sub-pixel 58 after the proper amount of charge has been emitted. For sub- pixel 58, when electron emitter structure 24 (2917) is emitting current, the change in charge at node 107 is given by the relationship:
- q is the total charge emitted by electron emitter structure 24 (2917) ;
- C actl7 is the capacitance associated with an activated row conductor coupled to column conductor 17 ; and ⁇ V 107 is the change in voltage at node 107.
- the electron emitter structure 24 (29 _ 17) has emitted the desired current, it is turned off by switching column conductor driver circuit 47 from the high impedance state to a high voltage state. This is shown at time t 9 in FIG. 4. It should also be noted that at time t 9 , the output voltage of row conductor driver circuit 39 switches from a high voltage, e.g. eighty volts, to a low voltage, e.g., zero volts; thereby discharging capacitances 51, 53, and 55 associated with column conductor 17.
- a high voltage e.g. eighty volts
- pulse width modulation portion 94 of each column conductor driver circuit performs pulse width modulation.
- pulse width modulation portion 94 of each column conductor driver circuit performs pulse width modulation.
- the amount of time that column conductor driver circuit 47 is in a high impedance state is the least for the time interval between times t s and t 6 and the most for the time interval between times t 8 and t 9 .
- electron emitter structure 24 (2817) is a stronger emission structure than electron emitter structure 24 (29>17) .
- sub-pixel 57 is a stronger emitting sub-pixel than sub-pixel 58.
- Sub-pixel 51 is intermediate sub-pixels 57 and 58 in emission strength. Accordingly, the column conductor drivers operate in a pulse width modulation mode to help improve, the luminance uniformity of FED 10.
- sub-pixels 50, 57, and 58 have been described, it should be understood the change in voltage at the other sub-pixel emitter nodes of FED 10, i.e., nodes 104, 105, 106, 107, 108, and 109, is directly proportional to the total charge emitted by the electron emitter structure associated with that particular node, i.e., 24, 2817) , 24 (2818) , 24 (2819) , 24 (29 ⁇ l7)/ 24 (29jl8) , 24 (29 ⁇ l9) , respectively, and that the operation is similar to that described for sub-pixels 60, 67, 68, 70, 77, and 78.
- the FED comprises a control circuit that includes a tri-state driver that monitors the voltage on the column conductor and uses pulse width modulation to control the current emitted from the electron emitter structures.
- the control circuit includes an amplitude modulation portion that controls the charging level on the capacitances associated with the column conductors.
- the row and column conductor driver circuits can be implemented using a microprocessor.
- the column conductor driver circuit can be designed to use the rate of change of voltage to control the uniformity of the luminance.
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Abstract
Description
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Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
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KR10-2003-7003465A KR20030029954A (en) | 2000-09-08 | 2001-07-26 | Field emission display and method |
JP2002525625A JP2004508591A (en) | 2000-09-08 | 2001-07-26 | Field emission display and method |
EP01961723A EP1330810A1 (en) | 2000-09-08 | 2001-07-26 | Field emission display and method |
AU2001282968A AU2001282968A1 (en) | 2000-09-08 | 2001-07-26 | Field emission display and method |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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US65851400A | 2000-09-08 | 2000-09-08 | |
US09/658,514 | 2000-09-08 |
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WO2002021492A1 true WO2002021492A1 (en) | 2002-03-14 |
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PCT/US2001/023408 WO2002021492A1 (en) | 2000-09-08 | 2001-07-26 | Field emission display and method |
Country Status (7)
Country | Link |
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EP (1) | EP1330810A1 (en) |
JP (1) | JP2004508591A (en) |
KR (1) | KR20030029954A (en) |
CN (1) | CN1459087A (en) |
AU (1) | AU2001282968A1 (en) |
TW (1) | TW518627B (en) |
WO (1) | WO2002021492A1 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8319413B2 (en) | 2007-11-23 | 2012-11-27 | Tsinghua University | Color field emission display having carbon nanotubes |
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US5008657A (en) * | 1989-01-31 | 1991-04-16 | Varo, Inc. | Self adjusting matrix display |
US5477110A (en) * | 1994-06-30 | 1995-12-19 | Motorola | Method of controlling a field emission device |
WO1999049445A1 (en) * | 1998-03-24 | 1999-09-30 | Motorola, Inc. | Driving field emission display including feedback control |
-
2001
- 2001-07-26 AU AU2001282968A patent/AU2001282968A1/en not_active Abandoned
- 2001-07-26 KR KR10-2003-7003465A patent/KR20030029954A/en not_active Application Discontinuation
- 2001-07-26 WO PCT/US2001/023408 patent/WO2002021492A1/en not_active Application Discontinuation
- 2001-07-26 CN CN01815865A patent/CN1459087A/en active Pending
- 2001-07-26 EP EP01961723A patent/EP1330810A1/en not_active Withdrawn
- 2001-07-26 JP JP2002525625A patent/JP2004508591A/en active Pending
- 2001-07-27 TW TW090118461A patent/TW518627B/en active
Patent Citations (3)
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US5008657A (en) * | 1989-01-31 | 1991-04-16 | Varo, Inc. | Self adjusting matrix display |
US5477110A (en) * | 1994-06-30 | 1995-12-19 | Motorola | Method of controlling a field emission device |
WO1999049445A1 (en) * | 1998-03-24 | 1999-09-30 | Motorola, Inc. | Driving field emission display including feedback control |
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Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8319413B2 (en) | 2007-11-23 | 2012-11-27 | Tsinghua University | Color field emission display having carbon nanotubes |
Also Published As
Publication number | Publication date |
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AU2001282968A1 (en) | 2002-03-22 |
CN1459087A (en) | 2003-11-26 |
KR20030029954A (en) | 2003-04-16 |
TW518627B (en) | 2003-01-21 |
JP2004508591A (en) | 2004-03-18 |
EP1330810A1 (en) | 2003-07-30 |
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