JP2004508591A - Field emission display and method - Google Patents

Abstract

A method of operating a field emission display (FED) (10) and an FED having a plurality of conductors (17, 18, 19) on which an electron emission structure (24) is located. Column conductor drive circuits (47, 48, 49) are connected to respective column conductors (17, 18, 19), and row conductor drive circuits (37, 38, 39) are coupled to respective column conductors (27, 28, 29). To form sub-pixels (50, 57, 58, 60, 67, 68, 70, 77, 78). The column conductor drive circuits (47, 48, 49) and the row conductor drive circuits (37, 38, 39) together form an electron emission structure (24) for emitting electrons. The column conductor drive circuit (47, 48, 49) measures at least one signal change of the column conductor and thereby adjusts the operating state of the electron emission structure (24) based on the comparison result.

Description

Ｃ_{ｅｆｆ１７}は、ゼロボルトである列導体１７と接続する（ｎ−１）行導体に接続する集合静電容量を示す；
【００３４】
Ｃ_{ａｃｔ１７}は、列導体１７と接続する単一のの始動している行導体に接続する静電容量を示す；
Ｒ_{ｅｆｆ１７}は、ゼロボルトである列導体１７と接続する（ｎ−１）行導体に接続する集合抵抗を示す；
【００３５】
Ｒ_{ａｃｔ１７}は、列導体１７と接続する１つの始動している行導体に接続する抵抗を示す；
ｎはＦＥＤ１０の列導体の数である。
列導体はそれぞれ同様な実効静電容量と実効抵抗値とを有する。例えば、列導体の１つ以外のすべてが起動しているときの、列導体１８と接続する実効静電容量と実効抵抗値は、次式で与えられる。
【００３６】
【数２】

Ｃ_{ｅｆｆ１８}は、ゼロボルトである列導体１８と接続する（ｎ−１）行導体に接続する集合静電容量を示す；
【００３７】
Ｃ_{ａｃｔ１８}は、列導体１８と接続する１つの始動している行導体に接続する静電容量を示す；
Ｒ_{ｅｆｆ１８}は、ゼロボルトである列導体１８と接続する（ｎ−１）行導体に接続する集合抵抗を示す；
【００３８】
Ｒ_{ａｃｔ１８}は、列導体１８と接続する１つの始動している行導体に接続する抵抗を示す；
ｎはＦＥＤ１０の列導体の数である。
列導体１９と接続する実効静電容量と実効抵抗値は、次式で与えられる。
【００３９】
【数３】

Ｃ_{ｅｆｆ１９}は、ゼロボルトである列導体１９と接続する（ｎ−１）行導体に接続する集合静電容量を示す；
【００４０】
Ｃ_{ａｃｔ１９}は、列導体１９と接続する１つの始動している行導体に接続する静電容量を示す；
Ｒ_{ｅｆｆ１９}は、ゼロボルトである列導体１９と接続する（ｎ−１）行導体に接続する集合抵抗を示す；
【００４１】
Ｒ_{ａｃｔ１９}は、列導体１９と接続する１つの始動している行導体に接続する抵抗を示す；
ｎはＦＥＤ１０の列導体の数である。
例えば、サブ画素５０の動作の説明に戻ると、静電容量５１とＣ_{ａｃｔ１７}とは、静電容量電圧ディバイダ・ネットワークを形成する。静電容量Ｃ_{ａｃｔ１７}の静電容量値は静電容量５１の静電容量値よりずっと大きいので、ノード１０１での電圧はほぼゼロボルトを維持し、行導体駆動回路３７からの電圧の殆どすべては静電容量５１を越えて出現する。列導体の電圧が電子放出構造体２４_{（２７，１７）}のしきい値電圧よりも高い場合は、電子放出構造体２４_{（２７，１７）}は、電子を放出して、それにより、静電容量５１を放電して、実効静電容量Ｃ_{ｅｆｆ１７}を
【００４２】
荷電する。従って、ノード１０１での電圧は増大し、電子放出構造体２４_{（２７，１７）}を越えた電圧は減少する。電子放出構造体２４_{（２７，１７）}を越えた電圧がしきい値電圧よりも低くなった場合は、電子放出構造体２４_{（２７，１７）}は電子放出を停止して、オフになる。
【００４３】
比較回路８１（図３に示す）は出力端子９１と共同して、列導体駆動回路が高インピーダンス状態であって電子放出構造体が電流を放出している時の列導体上の電圧をモニターする。列導体上で測定される電圧の変化は、電子放出構造体によって放出される電荷に比例する。例えば、列導体駆動回路４７は、列導体１７の電圧変化の測定値とサブ画素５０の所望強度と比例する電圧とを比較する。その比例する電圧は図２で説明した方法で予め決定される。列導体駆動回路４７は、適量の電荷が放出された後にサブ画素５０を遮断する。
【００４４】
サブ画素５０において、電子放出構造体２４_{（２７，１７）}が電流を放出している時に、ノード１０１で荷電される電荷は次の関係式で示される。
【００４５】
【数４】

ｑは、電子放出構造体２４_{（２７，１７）}によって放出される全電荷である。
Ｃ_{ａｃｔ１７}は、列導体１７と接続する始動している行導体に接続する静電容量である。
【００４６】
ΔＶ_１０１はノード１０１での電圧中の電荷である。
列導体駆動回路４７は振幅変調部９３を含み、静電容量５１はゼロボルトではなくて、予め選択された電圧に放電される。従って、強いサブ画素すなわち強い電子放出構造体を有する列導体は、正電圧に放電され、静電容量５１がゼロボルトの放電電圧の時の放電量と比較して、放出電流を減少させる。弱いサブ画素すなわち弱い電子放出構造体を有する列導体は、ゼロボルトに放電される。
【００４７】
ＦＥＤ１０を駆動させたときに、どの電子放出構造体が強いか弱いかの判断は、例えば、完全に白色の単一フレームをディスプレイし、どの電子放出構造体が比較回路をオン・オフするかによって決定される。それをするものが強い電子放出構造体で、それをしないのが弱い電子放出構造体である。強い電子放出構造体と弱い電子放出構造体との場所はメモリで記憶される。
【００４８】
電子放出構造体２４_{（２７，１７）}が所望の電流を放出した後に、電子放出構造体２４_{（２７，１７）}は列導体駆動回路４７によって、高インピーダンス状態から高電圧状態に切り換ることにより、オフにされる。これは図４のｔ_３で示される。この時間に、列導体駆動回路４７の出力電圧が高電圧状態に切り換る時に、静電容量Ｃ_{ｅｆｆ１７}が荷電を開始するので、ノード１０１での電圧は増加する。
【００４９】
ｔ_４で、列導体駆動回路３７の出力電圧は、高電圧、例えば８０ボルト、から、低電圧、例えばゼロボルト、に切り換り、それによって、列導体１７に接続している静電容量５１、５３、５５を放電する。
【００５０】
ｔ_５で、列導体駆動回路４７は高インピーダンス状態に置かれ、列導体駆動回路３８の出力電圧は、低電圧、例えばゼロボルトから、高電圧、例えば８０ボルトに転じる。列導体駆動回路４７は列導体１７上の電圧をモニターし、電子放出構造体２４_{（２８，１７）}は電流を放出する。列導体駆動回路４７は列導体１７上の電圧変化値とサブ画素５７の所望強度に比例する電圧とを比較する。この所望強度に比例する電圧は、図２に関して説明したように予め決められる。列導体駆動回路４８は、適量の電荷が放出された後にサブ画素５７を切り離す。サブ画素５７については、電子放出構造体２４_{（２８，１７）}が電流を放出しているときは、ノードで荷電される電荷は次式に示される。
【００５１】
【数５】

ｑは、電子放出構造体２４（２８，１７）によって放出される全電荷、Ｃａｃｔ１７は列導体１７に接続される起動された列導体と接続した静電容量、ΔＶ１０４はノード１０４での電圧変化である。
【００５２】
電子放出構造体２４（２８，１７）は、所望の電流を放出した後、列導体駆動回路４７を高インピーダンス状態から高電圧状態に切り換えることによって、オフにされる。これは図４中のｔ６で示されている。
【００５３】
ｔ７で、列導体駆動回路３８の出力電圧は、高電圧、例えば８０ボルトから、低電圧、例えばゼロボルトに切り換り、それによって、列導体１７に接続している静電容量５１、５３、５５を放電する。
【００５４】
ｔ８で、列導体駆動回路４７は高インピーダンス状態に置かれ、列導体駆動回路３８の出力電圧は、低電圧、例えばゼロボルトから、高電圧、例えば８０ボルトに転じる。列導体駆動回路４７は列導体１７上の電圧をモニターし、電子放出構造体２４（２８，１７）は電流を放出する。列導体駆動回路４７は列導体１７上の電圧変化値とサブ画素５８の所望強度に比例する電圧とを比較する。この所望強度に比例する電圧は、上述したように予め決められる。列導体駆動回路４７は、適量の電荷が放出された後にサブ画素５８を切り離す。サブ画素５８については、電子放出構造体２４（２９，１７）が電流を放出しているときは、ノード１０７で荷電される電荷は次式に示される。
【００５５】
【数６】

ｑは、電子放出構造体２４（２９，１７）によって放出される全電荷、Ｃａｃｔ１７は列導体１７に接続される起動された列導体と接続した静電容量、ΔＶ１０７はノード１０７での電圧変化である。
【００５６】
電子放出構造体２４（２９，１７）は、所望の電流を放出した後、列導体駆動回路４７を高インピーダンス状態から高電圧状態に切り換えることによって、オフにされる。これは図４中のｔ９で示されている。
【００５７】
ｔ９で、列導体駆動回路３９の出力電圧は、高電圧、例えば８０ボルトから、低電圧、例えばゼロボルトに切り換り、それによって、列導体１７に接続している静電容量５１、５３、５５を放電する。
【００５８】
タイミング・ダイアグラム１００に示されるように、本発明の他の利点は、放出電流を制御するために振幅変調を使用することに加えて、それぞれの列導体駆動回路のパルス幅変調部９４がパルス幅変調を行う。例えば、タイミング・ダイアグラム１００に示される、タイミングと可変パルス幅を仮定し、更に、サブ画素５０、５７、５８の所望強度は同一と仮定する。列導体駆動回路４７が高インピーダンス状態である時間量は最少で、ｔ５とｔ６との間の時間、最大で、ｔ８とｔ９との間の時間である。従って、電子放出構造体２４（２８，１７）は、電子放出構造体２４（２９，１７）よりも強い放出構造体である。即ち、サブ画素５７はサブ画素５８よりも強力な放射をするサブ画素である。サブ画素５１の放出強度はサブ画素５７と５８との中間である。従って、列導体駆動はパルス幅変調モードで動作して、ＦＥＤ１０の発光の均一性を助長する。
【００５９】
サブ画素５０、５７、５８の動作のみを説明したが、ＦＥＤ１０の他のサブ画素エミッタ・ノード、例えばノード１０４、１０５、１０６、１０７、１０８、１０９、での電圧変化は、特定のノード、例えば２４（２８，１７）、２４（２８，１７）、２４（２８，１７）、２４（２８，１７）、２４（２８，１７）、２４（２８，１７）と接続する電子放出構造体によって放出される全電荷に、それぞれ直接比例する。また、動作はサブ画素６０、６７、６８、７０、７７、７８で説明したのと同一である。
【００６０】
ここまでで、振幅変調と発光を制御するためのパルス幅変調とを使用したＦＥＤを提供した。このＦＥＤは、列導体の電圧をモニターする三相駆動からなる制御回路を含み、電子放出構造体から放出される電流を制御するためにパルス幅変調を使用した。更に、制御回路は、列導体と接続する静電容量の荷電レベルを制御する、振幅変調部を含む。
【００６１】
本発明の具体的実施例を示して説明したが、当業者は更なる改変や改良が考えられるであろう。本発明は、ここに示した特定の形式に限定されず、本発明の精神や範囲から逸脱しないすべての改変をカバーする。例えば、列や行の導体駆動回路はマイクロプロセッサを使用して実施され得る。更に、列導体駆動回路は、発光の均一性を制御するために、電圧変化の速度を使用すべく設計され得る。
【図面の簡単な説明】
【図１】本発明の実施例によるＦＥＤの一部をカットした等長図と回路概略図。
【図２】図１のＦＥＤの等価回路図。
【図３】本発明の実施例による図１の列導体駆動回路の回路ダイアグラム。
【図４】図１のＦＥＭの動作のタイミング・ダイアグラム。[0001]
Field of the invention
The present invention relates to a field emission display, and more particularly, to a method and circuit for controlling the emission current of a field emission display.
[0002]
Background of the Invention
Field emission displays (FEDs) are well known to those skilled in the art. FEDs consist of an anode plate and a cathode plate, forming a thin envelope. The cathode plate includes rows and columns of conductors, and is used to emit electrons from an electron emission structure such as a Spindt chip. The FED further has a resistor between the electron emission structure and the cathode plate to control the electron emission current. Generally, the resistor has a resistance value of 10 megohms or more. Since the resistor has a high resistance value, it is difficult to form a resistor, and the resistor is sensitive to temperature, so that the current emission from the electron emission structure in the operating temperature range is not flat.
[0003]
Another problem with FEDs is that the aging properties of the electron emission structures are different.
Accordingly, there is a need for a method and means for controlling the emission current of a FED to overcome at least some of these problems.
[0004]
Detailed explanation of figure
The present invention comprises a method and a FED for maintaining a uniform emission current over the operating life of a display. The method uses a column conductor drive circuit for driving the column conductors of the FED and a row conductor drive circuit for driving the row conductors of the FED. The circuit is in a high voltage, low voltage, or high impedance state on the column conductor. Further, when the column conductor drive circuit is in a high impedance state, the voltage on the connected column conductor is monitored.
[0005]
The FED is off when the output of the column and row conductor drive circuits is near zero volts. When the column conductor drive circuit is in a high impedance state and the row conductor is at a high voltage level, the sub-pixels associated with the row conductor and the column conductor transmit emission current. The voltage at which a particular row conductor turns on a sub-pixel is called the row select voltage. When the charge is released, a voltage rises on the column conductor associated with the electron emitting structure emitting the electrons. The rise or change in the voltage is monitored by the column conductor driving circuit and compared with a predetermined voltage. This predetermined voltage is called the intensity voltage value and determines when the display starts. When the desired voltage rise, ie, the desired brightness, is obtained, the output of the column conductor drive is switched from a high impedance state to a high voltage state to adjust the operating state of the electron emission structure. For example, the electron emission structure, and thus the subpixel, is turned off. It is desirable that the turning on / off of the pixel be performed within one image frame time.
[0006]
The column conductor drive circuit can operate in either an amplitude modulation (AM) mode or a dynamic pulse width modulation (PWM) mode. In AM mode, the capacitance connected to the column conductor is charged or discharged to a preselected level. In AM mode, columns with strong sub-pixels are discharged to a positive potential, thereby reducing emission current in the entire discharge area, while columns with weak sub-pixels are discharged to zero volts. In the PWM mode, the stronger emitting sub-pixel has a shorter pulse width than the standard pulse width, and the weaker emitting sub-pixel has a longer pulse width than the standard pulse width.
[0007]
FIG. 1 is an isometric view and a schematic circuit diagram of an FED 10 according to an embodiment of the present invention, in which a part of the FED 10 is cut. The FED 10 includes an FED device 11 and a control circuit 12 for controlling an emission current of the FED device 11.
[0008]
The FED device 11 includes a cathode plate 13 and an anode plate 14. Cathode plate 13 includes a substrate 16 made of glass, silicon, or the like. The first column conductor 17, the second column conductor 18, and the third column conductor 19 are disposed on the substrate 16. The dielectric layer 21 is disposed on the column conductors 17, 18, 19 and forms a plurality of wells 22.
[0009]
An electron emission structure 24 such as a Spindt tip is arranged in each well 22. The row conductors 27, 28, 29 are formed on the dielectric layer 21. The row conductors 27, 28, 29 are provided apart from and close to the electron emission structure 24. The row conductors 27, 28, 29 have a plurality of openings 30 and form a current emission region 31 in cooperation with the corresponding wall 22 and the electron emission structure 24. The column conductors 17, 18, 19 and the row conductors 27, 28, 29 are used to selectively address the electron emitting structure 24.
[0010]
For ease of understanding the present invention, FIG. 1 shows only three rows and columns. However, any number of column and row conductors can be used. As an example, the FED device has 240 row conductors and 960 column conductors. Methods of forming FED cathode plates addressed by rows and columns are well known to those of ordinary skill in the art.
[0011]
The anode plate 14 is arranged to receive an emission current 32 formed by the electrons emitted by the electron emission structure 24. The anode plate 14 is made of a transparent substrate 33 such as glass. The anode 34 is disposed on the transparent substrate 33. The anode 34 is preferably made of a transparent conductive material such as indium tin oxide (ITO). In the preferred embodiment, the anode 34 is a continuous layer and is located opposite the entire emission area of the cathode plate 13. That is, it is preferable that the anode 34 is disposed so as to face the entire electron emission structure 24.
[0012]
A plurality of phosphors 36 are disposed on the anode 34. The phosphor 36 is cathodoluminescent. Accordingly, the phosphor 36 is excited by the emission current 32 and emits light. Methods of forming the anode plates of a FED addressed by a matrix are also well known to those of ordinary skill in the art.
[0013]
According to an embodiment of the present invention, control circuit 12 includes row conductor drive circuits 37, 38, 39 and column conductor drive circuits 47, 48, 49. The row conductor driving circuits 37, 38, 39 are connected to the row conductors 27, 28, 29, respectively, and the column conductor driving circuits 47, 48, 49 are connected to the column conductors 17, 18, 19, respectively.
[0014]
FIG. 2 is a schematic diagram of the FED 10. FIG. 2 shows column conductors 17, 18, 19, column conductor drive circuits 47, 48, 49, row conductors 27, 28, 29, and row conductor drive circuits 37, 38, 39. . Although only three row conductor drive circuits and three column conductor drive circuits are shown, more or fewer row and column conductor drive circuits may be provided.
[0015]
FIG. 2 further shows the electron emission structures, sub-pixel capacitances, and resistors that connect to each row and column conductor of FED 10. In particular, the sub-pixel capacitance 51, the sub-pixel resistor 52, and the electron emission structure 24 connected to the sub-pixel 50_{(27, 17)}Are connected to the row conductor 27 and the column conductor 17. Electron emission structure 24_{(27, 17)}Are shown as an aggregate component expressing all the electron emission structures connected to the sub-pixel 50. The number 24 is generally used to identify the electron emitting structure. To illustrate the embodiment shown in FIG. 2, the electron emission structure was further defined by a subscript to the number 24. For example, the electron emission structure associated with the row conductor 27 and the column conductor 17 may be 24_{(27, 17)}Identified by The electron emission structures associated with row conductors 28 and column conductors 17 are 24_{(28, 17)}Identified by The electron emission structures associated with row conductor 27 and column conductor 18 are 24_{(27, 18)}Identified by
[0016]
The sub-pixel capacitance 53, the sub-pixel resistor 54, and the electron emission structure 24 connected to the sub-pixel 57_{(28, 17)}Indicates that they are connected to the row conductor 28 and the column conductor 17. Electron emission structure 24_{(28, 17)}Is shown as an aggregate component that represents all of the electron emission structures associated with the sub-pixel 57.
[0017]
The sub-pixel capacitance 55, the sub-pixel resistor 56, and the electron emission structure 24 connected to the sub-pixel 58_(29,17)Indicates that they are connected to the row conductor 29 and the column conductor 17. Electron emission structure 24_(29,17)Are shown as an aggregate component expressing all of the electron emission structures connected to the sub-pixel 58.
[0018]
Sub-pixel capacitance 61, sub-pixel resistor 62, electron emission structure 24 connected to sub-pixel 60_{(27, 18)}Indicates that they are connected to the row conductor 27 and the column conductor 18. Electron emission structure 24_{(27, 18)}Are shown as an aggregate component expressing all of the electron emission structures connected to the sub-pixel 60.
[0019]
The sub-pixel capacitance 63, the sub-pixel resistor 64, and the electron emission structure 24 connected to the sub-pixel 67_{(28, 18)}Is connected to the row conductor 28 and the column conductor 18. Electron emission structure 24_{(28, 18)}Are shown as an aggregate component expressing all of the electron emission structures connected to the sub-pixel 67.
[0020]
The sub-pixel capacitance 65, the sub-pixel resistor 66, and the electron emission structure 24 connected to the sub-pixel 68_{(29, 18)}Indicates that they are connected to the row conductor 29 and the column conductor 18. Electron emission structure 24_{(29, 18)}Are shown as an aggregate component expressing all of the electron emission structures connected to the sub-pixel 68.
[0021]
Sub-pixel capacitance 71, sub-pixel resistor 72, and electron emission structure 24 connected to sub-pixel 70_{(27, 19)}Indicates that they are connected to the row conductor 27 and the column conductor 19. Electron emission structure 24_{(27, 19)}Are shown as an aggregate component expressing all of the electron emission structures connected to the sub-pixel 70.
[0022]
The sub-pixel capacitance 73, the sub-pixel resistor 74, and the electron emission structure 24 connected to the sub-pixel 77_(28,19)Indicates that they are connected to the row conductor 28 and the column conductor 19. Electron emission structure 24_(28,19)Are shown as an aggregate component expressing all of the electron emission structures connected to the sub-pixel 77.
[0023]
The sub-pixel capacitance 75, the sub-pixel resistor 76, the electron emission structure 24 connected to the sub-pixel 78_(29,19)Indicates that they are connected to the row conductor 29 and the column conductor 19. Electron emission structure 24_(29,19)Is shown as an aggregate component representing all of the electron emission structures associated with sub-pixel 78.
[0024]
FIG. 3 shows an embodiment of the column conductor driving circuits 47, 48, 49 according to the present invention. That is, each circuit block 47, 48, 49 has a circuit structure shown in FIG. The column conductor drive circuits 47, 48, and 49 each include a sample and hold circuit 80, a comparator 81, a drive control circuit 82, a three-phase driver 83, a single-phase serial-to-parallel converter 87, and a calibration circuit 88. . In particular, analog video signals, VID_AInput terminal 84 is connected to receive the input signal. The output terminal 85 of the sample and hold circuit 80 is connected to the non-inverting input terminal 86 of the comparator 81. The output terminal 87 of the comparator 81 is connected to the input terminal 111 of the drive control circuit 82. The drive control circuit 82 includes an amplitude modulator 93 and a pulse width modulator 94. The output terminal 89 of the drive control circuit 82 is connected to the input terminal 90 of the three-phase driver 83. As shown in FIG. 2, the output terminal 91 is normally connected to the inverting input terminal 92 of the comparator 81 and the column conductor.
[0025]
The input terminal 95 of the calibration circuit 88 is connected to receive a start signal, and the output terminal 96 of the calibration circuit 88 is connected to the control terminal 97 of the comparator 81. An output terminal 96 of the calibration circuit 88 is connected to an input terminal 99 of a single-phase serial-to-parallel converter 87. The other input 101 of the single-phase serial-to-parallel converter 87 is connected to receive a serial input from channel n-1. The output terminal 102 of the single-phase serial-to-parallel converter 87 is connected to the input terminal 103 of the drive control circuit 82 as a serial output for connection to channel n + 1. The output terminal 110 of the single-phase serial-to-parallel converter 87 is connected to the input terminal 111 of the drive control circuit 82.
[0026]
In operation, when the display 10 is activated, the calibration circuit 88 transmits a reference signal to the comparator 81 via the control terminal 97. In addition, the calibration circuit 88 cycles through the display 10 for display over the entire screen. In particular, the row of the display 10 is sequentially selected by sequentially driving the row conductor driving circuits 37, 38, and 39. When the row conductor drive circuit 37 is selected, the row conductor 27 is activated, and the drive control circuit 82 turns on the sub-pixel connected to the row conductor 27 by the calibration circuit 88. For example, the row conductor driving circuit 37 applies 80 volts to the row conductor 27, and the column conductor driving circuits 47, 48, and 49 set the column conductors 17, 18, and 19 to zero volts, respectively. , 60, 70. Ideally, each sub-pixel emits enough current to generate a white signal. In a strong emitter sub-pixel, the voltage appearing at the output of the column drive circuit is the reference voltage V_REFGreater than, so start the comparator. Thus, at that sub-pixel, a logic high, or 1 volt level, is stored in the DC to AC converter 87. If the comparator is not started, a logic low, or zero volt level, will be stored in the DC to AC converter 87 at that sub-pixel. At the end of one line operation time, this set of information flows out of the column drive resistor and is stored in an external memory (not shown). For example, at the end of one line operation time, the intensity or luminance information of sub-pixels 50, 60, 70 flows into resistor 87. This information is then transmitted to an external memory.
[0027]
This process then continues until the next row is selected and all sub-pixels are characterized as strong or weak. In this manner, all displays are mapped one line at a time, with the output of each subpixel being one bit. This mapping takes one frame time, ie, 1/60 second. Once the display is mapped, the data stored in memory flows through the display and is appended to the appropriate digital video bytes. The column drive circuit knows for each row scanned whether the displayed sub-pixel is a strong or weak sub-pixel. For example, when a logic one is added to a digital video byte, the subpixel becomes a high intensity subpixel, and when a logic zero is added to the digital video byte, the subpixel becomes a low intensity subpixel.
[0028]
Once the display has been mapped, the calibration circuit 88 is closed. FIG. 4 is a timing diagram 100 illustrating a method of operating the FED 10 in a display mode. The display mode is characterized by the formation of a display image at the anode 14. The timing diagram 100 shown in FIG. 4 will be described together with FIGS. FIG. 4 shows the selective addressing and activation of the sub-pixels 50, 57, 58. The sub-pixels 60, 67, 68, 70, 77, 78 are selected in a similar manner by activating the column conductor drive circuits 48, 49. t₀In this case, the output voltage of the column conductor driving circuits 47, 48, 49 and the column conductor driving circuits 37, 38, 39 is set to a voltage lower than the threshold value of the corresponding electron-emitting structure, so that all the displays can be controlled. The capacitance is discharged to zero volts. As an example, the output voltages of the column conductor driving circuits 47, 48, 49 and the output voltages of the column conductor driving circuits 37, 38, 39 are brought to zero volts. Further, nodes 101, 102, 103, 104, 105, 106, 107, 108, 109 are at zero volts. Therefore, the capacitances 51, 53, 55, 61, 63, 65, 71, 73, and 75 each become almost zero volt.
[0029]
t₁Thus, the column conductor drive circuits 47, 48, 49 are placed in a high impedance state, and are therefore electrically disconnected from the FED 10. Timing diagram 100 shows only column conductor drive circuit 47 placed in a high impedance state.
[0030]
As shown in the timing diagram 100 of FIG. 4, the column conductor driving circuits 37, 38, and 39 are sequentially activated. t₁Then, the column conductor driving circuits 37, 38, and 39 output, for example, zero volts. This places the column conductors 27, 28, 29 at zero volts, respectively. The outputs of the column conductor driving circuits 47, 48, and 49 maintain a high impedance state.
[0031]
t₂In this case, the column conductor driving circuit 37 is activated, and is placed at a voltage higher than the threshold value of the electron emission structure on the column conductor 27. By way of example, the voltage on column conductor 27 is 80 volts. Column conductor drive circuits 38, 39 continue to maintain column conductors 28, 29, respectively, at zero volts.
[0032]
The capacitances 53, 55 are effectively in parallel and C_eff17Has an effective capacitance represented by: A typical FED has three or more column conductors. Therefore, the effective capacitance C_eff17Is much larger than the value of the capacitance 51. Further, resistors 54 and 56 are effectively in parallel, and R_eff17Has an effective resistance value represented by This value is typically much smaller than the resistance value 52. In particular, the effective capacitance C_eff17And effective resistance R_eff17Is given by the following equation.
[0033]
(Equation 1)

C_eff17Denotes the collective capacitance connected to the (n-1) row conductor connected to the column conductor 17 which is zero volts;
[0034]
C_act17Indicates the capacitance connected to a single active row conductor connected to the column conductor 17;
R_eff17Denotes the collective resistance connected to the (n-1) row conductor connected to the column conductor 17 which is zero volts;
[0035]
R_act17Indicates a resistor connected to one activated row conductor connected to the column conductor 17;
n is the number of column conductors of the FED 10.
The column conductors have the same effective capacitance and effective resistance, respectively. For example, the effective capacitance and the effective resistance connected to the column conductor 18 when all but one of the column conductors are activated are given by the following equations.
[0036]
(Equation 2)

C_eff18Denotes the collective capacitance connected to the (n-1) row conductor which connects to the column conductor 18 which is zero volts;
[0037]
C_act18Indicates the capacitance connected to one active row conductor connected to the column conductor 18;
R_eff18Indicates the collective resistance connected to the (n-1) row conductor connected to the column conductor 18 which is zero volts;
[0038]
R_act18Indicates the resistance connected to one activated row conductor that connects to the column conductor 18;
n is the number of column conductors of the FED 10.
The effective capacitance and the effective resistance value connected to the column conductor 19 are given by the following equations.
[0039]
(Equation 3)

C_eff19Denotes the collective capacitance connected to the (n-1) row conductor connected to the column conductor 19 which is zero volts;
[0040]
C_act19Indicates the capacitance connected to one active row conductor connecting to the column conductor 19;
R_eff19Indicates the collective resistance connected to the (n-1) row conductor connected to the column conductor 19 which is zero volts;
[0041]
R_act19Indicates the resistance connected to one starting row conductor connecting to the column conductor 19;
n is the number of column conductors of the FED 10.
For example, returning to the description of the operation of the sub-pixel 50, the capacitance 51 and C_act17Form a capacitance voltage divider network. Capacitance C_act17Is much greater than the capacitance value of capacitance 51, the voltage at node 101 remains substantially zero volts, and almost all of the voltage from row conductor drive circuit 37 exceeds capacitance 51. Appear. The voltage of the column conductor is changed to the electron emission structure 24._{(27, 17)}If the electron emission structure 24 is higher than the threshold voltage of_{(27, 17)}Emits electrons and thereby discharges the capacitance 51, resulting in an effective capacitance C_eff17To
[0042]
To charge. Accordingly, the voltage at node 101 increases and the electron emission structure 24_{(27, 17)}The voltage beyond is reduced. Electron emission structure 24_{(27, 17)}When the voltage exceeding the threshold voltage becomes lower than the threshold voltage, the electron emission structure 24_{(27, 17)}Stops electron emission and turns off.
[0043]
The comparator circuit 81 (shown in FIG. 3), in conjunction with the output terminal 91, monitors the voltage on the column conductor when the column conductor drive circuit is in a high impedance state and the electron emitting structure is emitting current. . The change in voltage measured on the column conductor is proportional to the charge emitted by the electron emitting structure. For example, the column conductor driving circuit 47 compares the measured value of the voltage change of the column conductor 17 with a voltage proportional to the desired intensity of the sub-pixel 50. The proportional voltage is predetermined by the method described with reference to FIG. The column conductor drive circuit 47 shuts off the sub-pixel 50 after an appropriate amount of charge is released.
[0044]
In the sub-pixel 50, the electron emission structure 24_{(27, 17)}Is discharging a current, the electric charge charged at the node 101 is expressed by the following relational expression.
[0045]
(Equation 4)

q is the electron emission structure 24_{(27, 17)}Is the total charge released by
C_act17Is the capacitance connected to the starting row conductor connected to the column conductor 17.
[0046]
ΔV₁₀₁Is the charge in the voltage at node 101.
The column conductor drive circuit 47 includes an amplitude modulation section 93, and the capacitance 51 is discharged to a voltage selected in advance, not to zero volts. Therefore, a column conductor having a strong sub-pixel, that is, a column emission structure having a strong electron emission structure is discharged to a positive voltage, and the emission current is reduced as compared with the discharge amount when the capacitance 51 is a discharge voltage of zero volt. Column conductors with weak sub-pixels or weak electron emission structures are discharged to zero volts.
[0047]
The determination of which electron emission structure is strong or weak when the FED 10 is driven is determined, for example, by displaying a completely white single frame and which electron emission structure turns on and off the comparison circuit. Is done. What does it is a strong electron-emitting structure, and what does not is a weak electron-emitting structure. The locations of the strong and weak electron emitting structures are stored in memory.
[0048]
Electron emission structure 24_{(27, 17)}Emits the desired current, the electron emission structure 24_{(27, 17)}Is turned off by the column conductor drive circuit 47 by switching from the high impedance state to the high voltage state. This corresponds to t in FIG.₃Indicated by At this time, when the output voltage of the column conductor drive circuit 47 switches to the high voltage state, the capacitance C_eff17Starts charging, the voltage at node 101 increases.
[0049]
t₄Thus, the output voltage of the column conductor driving circuit 37 switches from a high voltage, for example, 80 volts, to a low voltage, for example, zero volts, whereby the capacitances 51, 53, Discharge 55.
[0050]
t₅Thus, the column conductor drive circuit 47 is placed in a high impedance state, and the output voltage of the column conductor drive circuit 38 changes from a low voltage, for example, zero volts, to a high voltage, for example, 80 volts. The column conductor drive circuit 47 monitors the voltage on the column conductor 17 and_{(28, 17)}Emits current. The column conductor driving circuit 47 compares a voltage change value on the column conductor 17 with a voltage proportional to a desired intensity of the sub-pixel 57. The voltage proportional to the desired intensity is predetermined as described with reference to FIG. The column conductor drive circuit 48 disconnects the sub-pixel 57 after an appropriate amount of charge is released. For the sub-pixel 57, the electron emission structure 24_{(28, 17)}Is emitting current, the charge charged at the node is given by:
[0051]
(Equation 5)

q is the total charge emitted by the electron emission structure 24 (28, 17), Cact 17 is the capacitance connected to the activated column conductor connected to the column conductor 17, and ΔV104 is the voltage change at the node 104. is there.
[0052]
After emitting the desired current, the electron emission structure 24 (28, 17) is turned off by switching the column conductor drive circuit 47 from the high impedance state to the high voltage state. This is indicated by t6 in FIG.
[0053]
At t7, the output voltage of the column conductor drive circuit 38 switches from a high voltage, eg, 80 volts, to a low voltage, eg, zero volts, thereby causing the capacitances 51, 53, 55 connected to the column conductor 17 to be switched. To discharge.
[0054]
At t8, the column conductor drive circuit 47 is placed in a high impedance state, and the output voltage of the column conductor drive circuit 38 changes from a low voltage, for example, zero volts, to a high voltage, for example, 80 volts. The column conductor drive circuit 47 monitors the voltage on the column conductor 17, and the electron emission structure 24 (28, 17) emits current. The column conductor driving circuit 47 compares a voltage change value on the column conductor 17 with a voltage proportional to a desired intensity of the sub-pixel 58. The voltage proportional to the desired intensity is predetermined as described above. The column conductor drive circuit 47 disconnects the sub-pixel 58 after an appropriate amount of charge is released. For the sub-pixel 58, when the electron emission structure 24 (29, 17) is emitting current, the charge charged at the node 107 is expressed by the following equation.
[0055]
(Equation 6)

q is the total charge emitted by the electron emission structure 24 (29, 17), Cact17 is the capacitance connected to the activated column conductor connected to the column conductor 17, and ΔV107 is the voltage change at the node 107. is there.
[0056]
After emitting the desired current, the electron emission structure 24 (29, 17) is turned off by switching the column conductor drive circuit 47 from the high impedance state to the high voltage state. This is indicated by t9 in FIG.
[0057]
At t9, the output voltage of the column conductor drive circuit 39 switches from a high voltage, for example 80 volts, to a low voltage, for example zero volts, whereby the capacitances 51, 53, 55 connected to the column conductor 17 To discharge.
[0058]
As shown in the timing diagram 100, another advantage of the present invention is that, in addition to using amplitude modulation to control emission current, the pulse width modulator 94 of each column conductor drive circuit has a pulse width Perform modulation. For example, assume the timing and variable pulse width shown in timing diagram 100, and further assume that the desired intensities of sub-pixels 50, 57, 58 are the same. The amount of time that the column conductor drive circuit 47 is in the high impedance state is a minimum time between t5 and t6, and a maximum time between t8 and t9. Therefore, the electron emission structure 24 (28, 17) is a stronger emission structure than the electron emission structure 24 (29, 17). That is, the sub-pixel 57 is a sub-pixel which emits more powerful radiation than the sub-pixel 58. The emission intensity of the sub-pixel 51 is intermediate between the sub-pixels 57 and 58. Accordingly, the column conductor drive operates in a pulse width modulation mode to promote uniformity of light emission of the FED 10.
[0059]
Although only the operation of the sub-pixels 50, 57, 58 has been described, the voltage changes at other sub-pixel emitter nodes of the FED 10, such as nodes 104, 105, 106, 107, 108, 109, may vary at particular nodes, such as 24 (28, 17), 24 (28, 17), 24 (28, 17), 24 (28, 17), 24 (28, 17), emitted by the electron emitting structure connected to 24 (28, 17) Is directly proportional to the total charge that is applied. The operation is the same as that described for the sub-pixels 60, 67, 68, 70, 77, 78.
[0060]
Thus far, an FED using amplitude modulation and pulse width modulation for controlling light emission has been provided. The FED included a control circuit consisting of a three-phase drive that monitored the voltage on the column conductors, and used pulse width modulation to control the current emitted from the electron emission structure. Further, the control circuit includes an amplitude modulator for controlling a charge level of a capacitance connected to the column conductor.
[0061]
While specific embodiments of the present invention have been shown and described, further modifications and improvements will occur to those skilled in the art. The present invention is not limited to the specific forms shown herein, but covers all modifications that do not depart from the spirit and scope of the present invention. For example, column and row conductor drive circuits can be implemented using a microprocessor. Further, the column conductor drive circuit can be designed to use the rate of voltage change to control the uniformity of the emission.
[Brief description of the drawings]
FIG. 1 is an isometric view and a schematic circuit diagram of an FED according to an embodiment of the present invention, in which a part of the FED is cut.
FIG. 2 is an equivalent circuit diagram of the FED in FIG. 1;
FIG. 3 is a circuit diagram of the column conductor driving circuit of FIG. 1 according to an embodiment of the present invention.
FIG. 4 is a timing diagram of the operation of the FEM of FIG. 1;

Claims (3)

A plurality of column conductors on which the electron emission structure is installed, and a plurality of row conductors having openings; a column conductor driving circuit connected to a first one of the plurality of column conductors; A method of operating a field emission display (FED), wherein a column conductor and a plurality of row conductors together form a sub-pixel,
Forming an emission current by an electron emission structure for emitting electrons;
Measuring a signal change on at least one column conductor of the plurality of column conductors to define the measured voltage change;
Comparing the measured voltage change with the intensity voltage value to clarify the adjustment voltage value;
Adjusting the operating state of the electron emission structure that emits electrons based on the adjustment voltage value;
Method consisting of. A first conductor connected to the second conductor via the first capacitance, and connected to the third conductor via the second capacitance, wherein the first conductor drive circuit includes the first conductor; A method of operating an FED connected to one conductor, wherein a plurality of electron emitting structures are disposed on the first conductor, and a second conductor drive circuit operates the FED connected to the second conductor.
Forming an emission current by a plurality of electron emission structures for emitting electrons;
Stopping emission of electrons from the plurality of electron emission structures when a predetermined amount of current is emitted. A first conductor;
A first conductor drive circuit connected to the first conductor and capable of operating in a high impedance state;
A second conductor connected to the first conductor via a first capacitance;
A second conductor drive circuit connected to the second conductor;
A third conductor connected to the first conductor via a second capacitance;
A third conductor drive circuit connected to the third conductor;
A plurality of electron-emitting structures disposed on the first conductor;
FED consisting of

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