TW517303B - Method for cleaning mono-crystal silicon-semiconductor wafer and for processing a semiconductor-component - Google Patents

Method for cleaning mono-crystal silicon-semiconductor wafer and for processing a semiconductor-component Download PDF

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Publication number
TW517303B
TW517303B TW089121787A TW89121787A TW517303B TW 517303 B TW517303 B TW 517303B TW 089121787 A TW089121787 A TW 089121787A TW 89121787 A TW89121787 A TW 89121787A TW 517303 B TW517303 B TW 517303B
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item
patent application
processing
ions
semiconductor wafer
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TW089121787A
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Chinese (zh)
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Joachim Hopfner
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Infineon Technologies Ag
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
    • H01L21/3221—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
    • H10B53/30—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the memory core region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/223—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a gaseous phase
    • H01L21/2236—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a gaseous phase from or into a plasma phase
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Memories (AREA)

Abstract

In a cleaning-method of a mono-crystal silicon-semiconductor wafer (1) for removing platinum-contaminant or other meal-and/or rate-earth-metal substances, on a main surface is generated a getter-layer (15) by introducing pre-determined ions, in a temperature-processing step the undesired substances together with the introduced ions are removed on the crystal-dislocations under the formation of complexes, and in the next wet chemical etching step the getter-layer (15) is removed from the main surface.

Description

經濟部智慧財產局員工消費合作社印製 517303 A7 ___ B7 五、發明說明（f ) 本發明係關於一種由單晶矽半導體晶圓中去除金屬及 /或稀土金屬物質之淨化方法，其係依據申請專利範圍 第1項前言而得。 傳統之微子gH丨思兀件（D R A M s )大多使用氧化層或氮化 層（其介電常數最大是8)作爲記憶體介電質。爲了減少 此gB憶電谷器之尺寸以及製成永久性記憶體（ρ r a M s ), 則需要介電常數大很多之"新式"電容器材料（介電質或 鐵電質）。這在此類之刊物"N e u e D i e U k t r i k a f u r Gbit-Speicherchips von W: Hon 1e i n, Phys. Bl. 55 (1999)，Page 51-53中已知之電容器材料是 Pb(Zr， Ti)〇3[PZT]， SrBi2Ta2〇9[SBT]， SrTi〇3[ST]和 (Ba，Sr)Ti〇3[BST]。 使用此種新式之高ε -介電質/鐵電質由於各種原因 而會造成一些問題。首先，這些新式材料不可與傳統之 電子材料（多晶）矽相組合。因此必須使用鈍性之電子材 料（例如P t )或導電性之氧化物（例如，Ru〇2)。此外，在 電子材料和此種至電晶體之導電性連接結構（插栓）之間 須加入一種擴散位障（例如由TiN，TaN，Ir，Ir〇2和 MoS i 2所構成）。 最後，此種結構之形成過程中需要在氧氣中沈積新式 之高ε介電質/鐵電質以及已部份處理之矽-半導體晶 圓需要在大於550 °C時進（通常是很多次）退火。 使用新式之材料（金屬和稀土金屬）作爲高e介電質/ 鐵電質，電極和位障層時須使用此種對擴散過程有助益 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ----*--1---------------訂---------線 (請先閱讀背面之注意事項再填寫本頁) 517303 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明（> ) 之製程溫度，這在實際上是表示：此製程中該矽半導體 晶圓會受到嚴重污染之危險性。 在此種情況下一種很大之問題是晶體會受到鉑所污染 。鉑在矽中造成之較小污染可使電荷載體之壽命減小數 個數量級。在特定之組件（例如，SIPMOS組件）中，適當 地形成一種鉛污染可適當地使少數（m i no r i t y )電荷載體 之壽命減低。但在其它組件中所產生之不期望之高的鉑 污染（即，大於1〇12原子/ cm2)會使這些組件完全失效。 外部之與製程有關之污染亦會由於裝置（真空鉗子，貯 存盤，卡盤）本身而產生橫向染，因此亦使晶圓背面受 到污染。 由於鉛在溫度大於55CTC時即較快速地經由中間柵格 空間而擴散至矽中，則在該組件製程（其使用較高之溫 度）中之溫度處理步驟會使這些存在於晶圓周圍之鉑污 染物入侵至晶體中或使存在於晶體中之鉑污染物擴散至 該組件之區域中而使此組件不可使用。對已污染之矽晶 圓之昂貴之淨化硏究（自旋spin on)解法）已顯示整個單 獨之鉑不能完全由矽表面去除。會產生一種再沈積方式 ，其中在已污染之砂晶圓上在剝飩5 μ m之砂之後仍然 可測得相同之3 X 1 0 12原子/ c m2之鉑污染。混合至蝕刻溶 液所用之複合物（例如，TEF0)目前並未帶來所期望之結 果。 長久以來去除半導體晶體中不期望之物質已爲人所知 ，即，在所產生之干擾位置（例如，已植入之外來原子 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 517303 A7 ___ B7 V. Description of the Invention (f) The present invention relates to a purification method for removing metals and / or rare earth metal substances from single crystal silicon semiconductor wafers, which is based on the application The first scope of the patent is derived from the preface. Most of the traditional neutrino gH 丨 thinking elements (DRA Ms) use an oxide layer or a nitride layer (with a dielectric constant of up to 8) as the memory dielectric. In order to reduce the size of this gB memory valley device and make it into a permanent memory (ρ r a M s), a "new type" capacitor material (dielectric or ferroelectric) with a much larger dielectric constant is required. This is known in such publications as "N eue Die U ktrikafur Gbit-Speicherchips von W: Hon 1e in, Phys. Bl. 55 (1999), Page 51-53. The capacitor material is known as Pb (Zr, Ti). 3 [PZT], SrBi2Ta2O9 [SBT], SrTi03 [ST] and (Ba, Sr) Ti03 [BST]. The use of this new type of high ε-dielectric / ferroelectricity causes problems for various reasons. First, these new materials cannot be combined with traditional electronic materials (polycrystalline) silicon. It is therefore necessary to use passive electronic materials (such as Pt) or conductive oxides (such as RuO2). In addition, a diffusion barrier (such as TiN, TaN, Ir, Ir02, and MoS i 2) must be added between the electronic material and the conductive connection structure (plug) to the transistor. Finally, during the formation of this structure, new high-ε dielectric / ferroelectric materials and partially processed silicon-semiconductor wafers need to be deposited in oxygen (typically many times) at temperatures greater than 550 ° C. annealing. New materials (metals and rare earth metals) are used as high-e dielectrics / ferroelectrics. The electrodes and barrier layers must be used to facilitate the diffusion process. This paper is sized to Chinese National Standard (CNS) A4 specifications ( 210 X 297 mm) ---- *-1 --------------- Order --------- line (Please read the notes on the back before filling (This page) 517303 A7 B7 printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. The process temperature of the invention description (>), which actually means that the silicon semiconductor wafer will be seriously polluted during this process. . A big problem in this case is that the crystals are contaminated with platinum. The minor contamination of platinum in silicon can reduce the life of charge carriers by orders of magnitude. In a specific component (for example, a SIPMOS component), the proper formation of a lead contamination can appropriately reduce the life of a few (m i no r i t y) charge carriers. However, the undesirably high platinum contamination (ie, greater than 1012 atoms / cm2) generated in other components can render these components completely ineffective. External process-related contamination will also cause lateral staining due to the device (vacuum pliers, storage disks, chucks) itself, which will contaminate the back of the wafer. Since lead diffuses into the silicon more quickly through the intermediate grid space when the temperature is greater than 55CTC, the temperature processing steps in the component manufacturing process (which uses a higher temperature) will cause these platinum existing around the wafer Contaminants intrude into the crystal or cause platinum contamination present in the crystal to diffuse into the area of the component making the component unusable. The expensive spin-on solution of contaminated silicon crystals has shown that the entire platinum alone cannot be completely removed from the silicon surface. There will be a redeposition method in which the same 3 x 1 0 12 atoms / c m2 of platinum contamination can still be measured on a contaminated sand wafer after stripping 5 μm of sand. Compounds (e.g., TEF0) used to mix into the etching solution have not produced the desired results. It has been known for a long time to remove undesired substances from semiconductor crystals, that is, at the location of the interference (for example, implanted foreign atoms, the paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) %)

線· (請先閱讀背面之注意事項再填寫本頁) 517303 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明ο ) 或離子）上沈積由這些原子相互間所形成及/或以寄生 閘之原子所形成之複合物，晶體偏位或其它晶體缺陷或 遠離組件區之類似物。 由US-A-5-223 734中已知一種去除過程，其中在組件 形成於半導體晶圓之前側之後施加一種由BPSG或PSG 所構成之保護且在使用一種化學機械式整平方法之情況 下使晶圓之背面粗糙化，且在背面上施加一種去除物質 (例如，磷）使其侵入此晶圓之背面。然後使此晶圓受到 一種溫度處理，以便使此去除物質更深地進入晶圓中且 在磷去除中心上沈積一些移動式污染物。由於在此種方 法中可產生二種去除中心，即一種是由化學機械式整平 所產生之偏位（offset),另一種是由擴散所引入乏磷平 擾中心，則不期望之物質即可有效地去除。 此外，由SU-A-5840590中已知一種去除技術，其中 在矽晶圓中植入氦離子，氨離子可在晶體中聚集成較大 之複合物。隨後之溫度處理步驟可由晶體中使氨雜質之 氣體被去除，以便在晶體中保留較大之空位或雜質，在 其內部表面上保留空的矽連結（dangling bonds)，其用 作有效之去除中心。 上述二種方法之特性是：當其用在組件製造過程中時 半導體晶圓之一個區域（通常是背面）須適當地犧牲，以 便在其中沈積不期望之外來物質，而在與上述區域相遠 離之區域中製成有功能之組件。但由於各不同之原因， 則由半導體晶體中完全去除上述這些不期望之物質仍然 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ----r I--，--I----------訂--------- (請先閱讀背面之注意事項再填寫本頁) 517303 A7 ___ B7 五、發明說明（4 ) 是値得去作。一方面是這些由去除技除所捕獲之外來原 子在特定之外部作用（例如，壓力或溫度）下又可由去除 中心溶解出來且擴散至組件區中，使外來原子事後可影 響這些組件之功能。另一方面因此使晶圓之整個區域 (包括晶圓背面）可用來製造這些組件。 本發明之目的因此是提供一種單晶矽半導體晶圓之淨 化方法，其可去除金屬物質及/或稀土金屬物質，這些 不期望之物質可完全由半導體晶圓中去除。 此目的是藉由申請專利範圍第1項之特徵來達成。 此種淨化方法之特徵是： -表面附近之去除劑層是以下述方式產生：至少一種指 定元素之離子經由半導體晶圓之至少一個主表面進入 表面附近之區域中， -金屬物質及/或稀土金屬物質以及所引入之離子在溫 度處理步驟中在晶體偏位處形成複合物而去除， -在濕式化學蝕刻步驟中此去除劑層由至少一個主表面 中去除。 / 在污染物是舶且所引入之離子之元素是磷及/或硼時 此種方法特別有效。這是基於以下之認知：P +或B +離子 引入至矽晶圓中會產生偏位且所引入之P +離子或B +離子 會與鉑原子在各偏位上形成各複合物，這些複合物在隨 後之蝕刻步驟中例如以HF/HN〇3混合物且需要時以hN〇3 來進行之再處理而半導體晶圓之主表面中去除。 離子之引入可藉由電漿摻雜或離子植入來進行。電漿 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) 訂---------線一 經濟部智慧財產局員工消費合作社印製 517303 Α7 Β7 1、發明說明（r ) 摻雜通常可達成一種較高之表面濃度。離子植入例如以 1018-102°原子/cm2之劑量來進行。 在植入入離子之後進行一種溫度處理步驟，其中存在 於半導體晶體中之鉛原子增多而進行擴散且與所引入之 離子在各個偏位處聚合成或多或少之較大之複合物。 本發明之方法一方面可作爲隔離式淨化方法而用在半 導體晶圓上，但亦可整合在半導體組件之處理方法中， 此時在矽半導體晶圓之一個主面上對一種半導體組件進 行處理且在處理過程中在另一個主面上進行本發明之淨 化方法。有利之方式是可在一適當之時間進行此種溫度 處理步驟，使其可同時形成該外來質之去除劑且達成此 半導體組件處理時所設置之功能。 本發明以下將依據dram記憶胞處理時之實施例來詳 述。圖式簡單說明： 第1圖一種形成矽半導體晶圓中之DRAM記憶胞之層序 列，其具有一個開關電晶體及一個高ε或鐵電質堆疊電 容器。 在Ρ -摻雜之矽半導體基板1上藉由一般之整平技術 (層沈積，使用微影術和蝕刻技術之層結構化方法，層 摻雜）而構成一種η-通道- MOS電晶體。 η +摻雜之汲極區2是藉由一種由基板材料所構成之通 道4而與Π +摻雜之源極區3相隔開（即，通道4介於此 二區2，3之間）。在通道4上存在一種薄的閘極氧化層 5，在閘極氧化5上施加一種多晶矽閘極電極6。 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) --------訂---------一 經濟部智慧財產局員工消費合作社印製 經濟部智慧財產局員工消費合作社印製 517303 A7 B7 五、發明說明（b ) 在上述之MOS電晶體2，3，4，5，6上方沈積一種覆 蓋氧化層7，其含有一種接觸孔8，接觸孔8中塡入一種 由多晶矽構成之電性連接結構9 (所謂’'插栓"）。 上述結構之構成及製造方式已爲人所知。若不用此處 所示之MOS晶體2，3，4，5，6，則亦可設置雙極性電 晶體或其它單石式半導體功能元件。 在覆蓋氧化層7上製成一種電容器10。 電容器10具有一個下電極11(所謂底部電極），一個 上電極1 2和一個介於此二個電極之間的高ε介電質/ 鐵電質1 3。 高ε介電質/鐵電質13(例如，PZT，SBT，ST或BST) 是藉由 MOCVD(Metal Organic Chemical Vapor D e p o s i t i ο η )過程或濺鍍過程沈積而成。 在沈積高ε介電質/鐵電質1 3之後，此介電質必須 在含氧之大氣中在溫度550-800 °C時進行多次之退火。 爲了使高ε介電質/鐵電質13不會與電極11，12發生 不期望之化學反應，則各電極應P t (或其它溫度足夠穩 定之鈍性材料所製成。 爲了製成各電極1 1，1 2，則在沈積此種高ε介電質/ 鐵電質1 3之前和之後須進行其它之沈積過程。 在上述之退火步驟中，例如Bi，Ba，Sr可由高ε介電 質/鐵電質1 3擴散至下部之P t電極1 1。此外，P t在溫 度大於5 50 °C時對矽具有一種很高之擴散能力。爲了保 護上述之連接結構9 ,則須在下部之Pt電極1 1下方設 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) -I I I I I I I 訂· —---111 *5^ 一 5173〇3 A7 B7 五、發明說明（7 ) 置一種由TiN，TaN，Ir，Ir〇2，MoSi2或其它適當材料 所構成之一般性高導電之位障層1 4。此位障層1 4藉由 一種沈積過程（和情況需要時一種隨後之退火步驟）而產 生，此種過程依據上述之層序列在P t電極1 1，1 2和高 ε介電質/鐵電質13沈積之前進行。 電容器和位障層構造所需之新式材料（金屬和稀土金 屬）之全部都可在上述之沈積過程中直接與矽半導體晶 圓之背面（通常是裸露的）相接觸且侵入此半導體基板中 。爲了使這些物質在隨後之溫度處理步驟中不會在組件 區之方向中擴散而影響該組件區，則在此種溫度處理步 驟之前須在矽半導體晶圓背面上產生一種去除劑層1 5。 此種去除劑層1 5例如以下述方式產生：使磷離子或硼 離子植入至半導體晶圓背面之表面附近之深度中。典型 之植入劑量是在1018-102()原子/ cm2之範圍中，其中此表 面濃度須高一個數量級。若不使用植入法，則亦可進行 電漿摻雜法。 藉由磷或硼之植入而在矽晶體中感應一種內部應力 (stress),此種應力會產生偏位。這些偏位是Pt-P -複 合物或Pt-B-複合物所用之胚體晶胞（cell)。這些複合 物可較容易地在濕式化學溶液中去除，而不會使鉑（P t ) 重新積聚在矽上。在此種濕式化學蝕刻步驟中例如可使 用一種HF/HN03混合物。但亦可使用其它之酸混合物。 例如，王水。可能時亦須以HNCh來進行一種再處理。 如上所述，高ε介電質/鐵電質13在一種含氧之大 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注音？事項再填寫本頁) --------^ — — — — — — — 經濟部智慧財產局員工消費合作社印製 517303 A7 B7 五、發明說明（J ) 氣中在溫度550-800 °C時進行多次之退火。可使用這些 溫度處理步驟，使其同時在本發明之淨化方法中使外來 物質擴散至去除劑中心。因此，在每一製造此種組件所 須之溫度處理之前可使離子植入至晶圓背面以便產生一 種去除劑層1 5，且在溫度處理步驟之後藉由濕式化學 蝕刻步驟來去除該去除劑層1 5或主要是去除此去除劑 層1 5中之P t - P -複合物。這些在半導體組件處理時所需 之溫度處理步驟可另外使用在去除劑-過程中。此外，若 希望時或需要時，當然亦可進行本發明其它之淨化步 驟。去除劑層1 5因此可在MOS電晶體2，3，4，5，6 製造之前，期間或之後藉由離子植入而產生且藉由濕式 化學蝕刻步驟而去除，其中總是可插入一種溫度處理步 驟。 符號之說明 1 矽半導體基板 2 汲極區 3 源極區 4 通道 5 閘極氧化層 6 閘極電極 7 覆蓋氧化層 8 接觸孔 9 連接結構 10 電容器 -10 - 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注音？事項再填寫本頁) I-----—訂11!11--· 經濟部智慧財產局員工消費合作社印製 經濟部智慧財產局員工消費合作社印製 517303 A7 _B7 五、發明說明（？） 1 1，1 2電極 13 高ε介電質/鐵電質 14 位障層 1 5 去除劑層 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁)(Please read the precautions on the back before filling this page) 517303 Printed by the Consumer Property Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. Description of the invention ο) or ions) deposited on these atoms and formed by each other Compounds formed by the atoms of parasitic gates, crystal deviations or other crystal defects or the like far from the component area. A removal process is known from US-A-5-223 734, in which a protection consisting of BPSG or PSG is applied after the component is formed on the front side of the semiconductor wafer and in the case of a chemical mechanical leveling method The back surface of the wafer is roughened, and a removal substance (for example, phosphorus) is applied to the back surface to invade the back surface of the wafer. The wafer is then subjected to a temperature treatment to allow the removed material to penetrate deeper into the wafer and deposit some mobile contaminants on the phosphorus removal center. Since two types of removal centers can be generated in this method, one is the offset caused by chemical mechanical leveling, and the other is the center of phosphorus-depleted interference introduced by diffusion. The undesired substances are Can be effectively removed. In addition, a removal technique is known from SU-A-5840590, in which helium ions are implanted in a silicon wafer, and ammonia ions can be aggregated into a larger complex in the crystal. The subsequent temperature treatment step can remove the ammonia impurity gas from the crystal in order to retain large vacancies or impurities in the crystal and leave empty dangling bonds on its internal surface, which is used as an effective removal center. . The characteristic of the above two methods is that when it is used in the module manufacturing process, an area (usually the back side) of the semiconductor wafer must be appropriately sacrificed in order to deposit undesired foreign substances therein, and away from the above areas. Functional components are made in the area. However, due to various reasons, the above-mentioned undesired substances are completely removed from the semiconductor crystal. The Chinese paper standard (CNS) A4 (210 X 297 mm) is still applicable to this paper size. ---- r I-,- -I ---------- Order --------- (Please read the notes on the back before filling out this page) 517303 A7 ___ B7 V. Description of Invention (4) Yes Make. On the one hand, these foreign atoms captured by the removal technique can be dissolved out by the removal center and diffused into the component area under specific external effects (for example, pressure or temperature), so that the foreign atoms can affect the function of these components afterwards. On the other hand, the entire area of the wafer (including the back side of the wafer) is thus available for manufacturing these components. An object of the present invention is therefore to provide a method for purifying a single crystal silicon semiconductor wafer, which can remove metal substances and / or rare earth metal substances, and these undesired substances can be completely removed from the semiconductor wafer. This objective is achieved by the features of the first scope of the patent application. The characteristics of this purification method are:-the remover layer near the surface is generated in such a way that ions of at least one specified element enter the area near the surface via at least one major surface of the semiconductor wafer,-metal substances and / or rare earths The metal species and the introduced ions are removed by forming a complex at the crystal offset in the temperature treatment step,-the remover layer is removed from at least one major surface in the wet chemical etching step. / This method is particularly effective when the contaminant is a vessel and the element of the introduced ions is phosphorus and / or boron. This is based on the recognition that the introduction of P + or B + ions into a silicon wafer will cause an offset and the introduced P + ions or B + ions will form complexes with platinum atoms at each offset. These complexes The material is reprocessed in a subsequent etching step, for example with an HF / HNO3 mixture and, if necessary, hNO3 and removed from the main surface of the semiconductor wafer. Ion introduction can be performed by plasma doping or ion implantation. The size of the paper is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) (Please read the precautions on the back before filling this page) Order --------- Line 1 Ministry of Economy Intellectual Property Printed by the Bureau's Consumer Cooperatives 517303 A7 B7 1. Description of the invention (r) Doping usually achieves a higher surface concentration. Ion implantation is performed, for example, at a dose of 1018-102 ° atoms / cm2. After implanting the ions, a temperature treatment step is performed in which the lead atoms present in the semiconductor crystal increase, diffuse, and aggregate with the introduced ions at various offsets to form more or less larger complexes. The method of the present invention can be used on a semiconductor wafer as an isolated purification method, but can also be integrated into a semiconductor component processing method. At this time, a semiconductor component is processed on a main surface of a silicon semiconductor wafer. And the purification method of the present invention is performed on the other main surface during processing. An advantageous method is that such a temperature treatment step can be performed at an appropriate time so that it can simultaneously form the foreign substance removing agent and achieve the function set during the processing of the semiconductor device. The present invention will be described in detail hereinafter with reference to an embodiment in which the memory cells are processed. Brief description of the drawing: Fig. 1 is a layer sequence forming a DRAM memory cell in a silicon semiconductor wafer, which has a switching transistor and a high epsilon or ferroelectric stacked capacitor. An η-channel-MOS transistor is formed on the p-doped silicon semiconductor substrate 1 by a general leveling technique (layer deposition, layer structuring method using lithography and etching techniques, layer doping). The η + doped drain region 2 is separated from the Π + doped source region 3 by a channel 4 made of a substrate material (ie, the channel 4 is between the two regions 2 and 3). . There is a thin gate oxide layer 5 on the channel 4, and a polycrystalline silicon gate electrode 6 is applied on the gate oxide 5. This paper size applies to China National Standard (CNS) A4 specification (210 X 297 mm) (Please read the precautions on the back before filling this page) -------- Order --------- Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs and printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs and printed by 517303 A7 B7 V. Description of the invention (b) A cover is deposited on the above MOS transistor The oxide layer 7 includes a contact hole 8. An electrical connection structure 9 (so-called “plug”) made of polycrystalline silicon is inserted into the contact hole 8. The structure and manufacturing method of the above structure are known. If the MOS crystals 2, 3, 4, 5, 6 shown here are not used, bipolar transistors or other monolithic semiconductor functional elements can also be provided. A capacitor 10 is made on the cover oxide layer 7. The capacitor 10 has a lower electrode 11 (so-called bottom electrode), an upper electrode 12 and a high ε dielectric / ferroelectric 13 between these two electrodes. High ε dielectric / ferroelectric 13 (for example, PZT, SBT, ST, or BST) is deposited by a MOCVD (Metal Organic Chemical Vapor De p s i t i ο η) process or a sputtering process. After the deposition of high-ε dielectric / ferroelectric 13, the dielectric must be annealed several times in an oxygen-containing atmosphere at a temperature of 550-800 ° C. In order that the high ε dielectric / ferroelectric 13 does not cause undesired chemical reactions with the electrodes 11, 12, each electrode should be made of Pt (or other blunt material with sufficient temperature stability. To make each For electrodes 1 1 and 12, other deposition processes must be performed before and after depositing such a high ε dielectric / ferroelectric 13. In the above annealing step, for example, Bi, Ba, and Sr can be high ε dielectric The electric / ferroelectric material 1 3 diffuses to the lower P t electrode 11 1. In addition, P t has a high diffusivity to silicon when the temperature is greater than 5 50 ° C. In order to protect the connection structure 9 described above, it is necessary to The paper size below the Pt electrode 1 1 is set to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) (Please read the precautions on the back before filling this page) -IIIIIII Order · —--- 111 * 5 ^ 5173〇3 A7 B7 V. Description of the invention (7) A general highly conductive barrier layer 14 composed of TiN, TaN, Ir, IrO2, MoSi2 or other appropriate materials is provided. The barrier layer 1 4 is produced by a deposition process (and a subsequent annealing step if necessary). The layer sequence according to the above is performed before the deposition of the P t electrodes 11, 12 and the high ε dielectric / ferroelectric 13. All new materials (metals and rare earth metals) required for capacitor and barrier layer construction are available. During the above-mentioned deposition process, the silicon semiconductor wafer is directly in contact with the backside of the silicon semiconductor wafer (usually bare) and penetrates into the semiconductor substrate. In order to prevent these substances from diffusing in the direction of the component area during the subsequent temperature processing step, Affecting the component area, a remover layer 15 must be generated on the back of the silicon semiconductor wafer before such a temperature processing step. Such a remover layer 15 is produced, for example, in the following manner: implantation of phosphorus ions or boron ions To the depth near the surface of the back of the semiconductor wafer. The typical implantation dose is in the range of 1018-102 () atoms / cm2, where the surface concentration must be an order of magnitude higher. If implantation is not used, it can also be performed Plasma doping method. An internal stress is induced in the silicon crystal by implantation of phosphorus or boron, and this kind of stress will generate offsets. These offsets are Pt-P-composite or Pt-B- Complex Institute Embryo cell. These complexes can be easily removed in a wet chemical solution without re-accumulating platinum (Pt) on the silicon. In this wet chemical etching step, for example, A HF / HN03 mixture is used. However, other acid mixtures can also be used. For example, aqua regia. HNCh must also be used for a reprocessing. As mentioned above, the high ε dielectric / ferroelectric 13 is contained in a The size of oxygen paper is in accordance with Chinese National Standard (CNS) A4 (210 X 297 mm) (Please read the note on the back? Please fill in this page for matters) -------- ^ — — — — — — — Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 517303 A7 B7 V. Description of the invention (J) The temperature of the gas is 550-800 ° At C, multiple annealings are performed. These temperature treatment steps can be used to simultaneously diffuse foreign materials to the center of the remover in the purification method of the present invention. Therefore, the ions can be implanted on the back of the wafer to produce a remover layer 15 before each temperature treatment required to manufacture such a component, and the removal is removed by a wet chemical etching step after the temperature treatment step. The agent layer 15 or mainly removes the P t-P-complex in the remover layer 15. These temperature processing steps required during semiconductor device processing can be additionally used in the remover-process. In addition, if desired or necessary, other purification steps of the present invention can of course be performed. The remover layer 15 can therefore be generated by ion implantation before, during or after the manufacture of MOS transistors 2, 3, 4, 5, 6 and removed by a wet chemical etching step, of which one can always be inserted Temperature processing steps. Explanation of symbols 1 Silicon semiconductor substrate 2 Drain region 3 Source region 4 Channel 5 Gate oxide layer 6 Gate electrode 7 Covering oxide layer 8 Contact hole 9 Connection structure 10 Capacitor -10-This paper size applies to Chinese national standards (CNS ) A4 size (210 X 297 mm) (Please read the phonetic on the back? Matters before filling out this page) I ------- Order 11! 11-- · Printed by the Ministry of Economic Affairs Intellectual Property Bureau Staff Consumer Cooperatives Printed by the Intellectual Property Bureau's Consumer Cooperative 517303 A7 _B7 V. Description of the invention (?) 1 1, 1 2 Electrode 13 High ε dielectric / ferroelectric 14 barrier layer 1 5 Remover layer This paper applies Chinese national standards (CNS) A4 size (210 X 297 mm) (Please read the precautions on the back before filling this page)

Claims (1)

517303 私年修屋丨 "|·〜一’•丨 一一^-----—f t、申請專利範圍 第89 1 2 1 787號「單晶矽半導體晶圓之淨化方法及半導體組件 之處理方法」專利案 （90年11月修正） 六申請專利範圍 1. 一種單晶矽半導體晶圓（1)之淨化方法，其是用來去除金 屬及/或稀土金屬物質，其特徵爲： -以下述方式產生一種靠近表面之去除劑層（15);至少一 種指定元素之離子經由半導體晶圓（1)之至少一個主表 面而進入表面附近之區域中， -金屬及/或稀土金屬物質及所引入之離子在溫度處理 步驟中在形成複合物時在去除劑層（15)內部之晶體偏 位處被去除， -在濕式化學蝕刻步驟中由至少一個表面中去除此去除 劑層（15)。 2. 如申請專利範圍第1項之方法，其中即將去除之物質是 鉑且已植入之離子之元素是磷及/或硼。 3. 如申請專利範圍第1或第2項之方法，其中離子是藉由 植入法而被引入。 4·如申請專利範圍第3項之方法，其中植入之劑量是1〇18-102Q 原子 /cm2。 5_如申請專利範圍第1或第2項之方法，其中離子是藉由 電漿摻雜而被引入。 6.如申請專利範圍第1項之方法，其中在濕式化學餓刻步 驟中使用一種HN/HNO3混合物且需要時須以ηΝ03進行 —種再處理。 517303 六、申請專利範圍 7. 如申請專利範圍第1項之方法，其中各步驟依順序進行 很多次。 8. —種矽半導體晶圓（1)之主表面上之半導體組件之處理方 法，其中在處理過程中在此半導體晶圓（1)之另一主表面 上進行如申請專利範圍第1至7項中任一項之方法一次 或多次。 9·如申請專利範圍第8項之方法，其中溫度處理步驟中至 少一個步驟同時達成此半導體組件處理時之一種功能。 10·如申請專利範圍第9項之方法，其中此半導體組件是一 種具有鐵電介電質之記憶元件且至少一個溫度處理步驟 是同時用來控制此鐵電介電質。517303 Private House Repair 丨 " | · ~ 一 '• 丨 one one ^ -----— ft, patent application scope 89 1 2 1 787 "Purification method of single crystal silicon semiconductor wafer and semiconductor components "Method of processing" patent case (Amended in November 1990) Six applications for patent scope 1. A method for purifying single crystal silicon semiconductor wafers (1), which is used to remove metals and / or rare earth metal substances, which are characterized by:- A remover layer (15) close to the surface is generated in the following manner; ions of at least one specified element enter at least one major surface of the semiconductor wafer (1) into a region near the surface,-a metal and / or a rare earth metal substance and The introduced ions are removed at the crystal deviations in the remover layer (15) when the composite is formed in the temperature treatment step,-the remover layer (15 is removed from at least one surface in the wet chemical etching step) ). 2. The method according to item 1 of the patent application, wherein the substance to be removed is platinum and the elements of the implanted ions are phosphorus and / or boron. 3. The method according to item 1 or 2 of the patent application, wherein the ions are introduced by implantation. 4. The method according to item 3 of the patent application range, wherein the implanted dose is 1018-102Q atoms / cm2. 5_ The method of claim 1 or 2, wherein the ions are introduced by plasma doping. 6. The method according to item 1 of the patent application scope, wherein a HN / HNO3 mixture is used in the wet chemical starvation step and if necessary, it must be treated with ηΝ03-a kind of reprocessing. 517303 VI. Application for Patent Scope 7. For the method of applying for the first item of patent scope, each step is performed many times in sequence. 8. — A method for processing a semiconductor component on the main surface of a silicon semiconductor wafer (1), wherein the processing is performed on the other main surface of the semiconductor wafer (1) during the processing as described in the patent application range 1 to 7 The method of any one item is one or more times. 9. The method according to item 8 of the scope of patent application, wherein at least one of the temperature processing steps simultaneously achieves a function in the processing of the semiconductor device. 10. The method according to item 9 of the patent application scope, wherein the semiconductor device is a memory element having a ferroelectric dielectric and at least one temperature processing step is also used to control the ferroelectric dielectric.
TW089121787A 1999-10-20 2000-10-18 Method for cleaning mono-crystal silicon-semiconductor wafer and for processing a semiconductor-component TW517303B (en)

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