TW515069B - Lead frame structure - Google Patents

Lead frame structure Download PDF

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Publication number
TW515069B
TW515069B TW90129168A TW90129168A TW515069B TW 515069 B TW515069 B TW 515069B TW 90129168 A TW90129168 A TW 90129168A TW 90129168 A TW90129168 A TW 90129168A TW 515069 B TW515069 B TW 515069B
Authority
TW
Taiwan
Prior art keywords
chip
lead frame
lead
scope
frame structure
Prior art date
Application number
TW90129168A
Other languages
Chinese (zh)
Inventor
Cheng-Jiau Wu
Original Assignee
Taiwan Electronic Packaging Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Electronic Packaging Co filed Critical Taiwan Electronic Packaging Co
Priority to TW90129168A priority Critical patent/TW515069B/en
Application granted granted Critical
Publication of TW515069B publication Critical patent/TW515069B/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Abstract

A lead frame structure is used to carry IC chip and can electrically conduct the chip to the exterior. It comprises the following parts plural conduction leads arranged aggregately, each lead is about a block shape and has a top plane that carries the chip and an opposite bottom plane. The designated site of the bottom plane is recessed with a fixed depth toward the top plane. The recessed surface can be used to electrically connect the chip and the area without recess is naturally formed a connection part. The connection part is protruded and is able to connect the exterior. Then the chip is electrically conducted to the exterior.

Description

經濟部智慧財產局員工消費合作社印製 515069 C7 D7_ 一 五、創作說明（） 本發明係與晶片封裝有關，更詳而言之是指一種晶片 封裝用之導線架結構。 按，由於一般積體電路晶片皆極為脆弱，必須在其外 部施以適當之封裝後，方能確保在使用時不易受外力之污 5 染或破壞，並且必須將該晶片之電性適度地導接於一電路 板或一載板或一導線架上，方能有效地將其電性藉由該電 路板或該載板或該導線架而傳導於外界使用者。 於此，請參閱第一圖，就現今一般之導線架（1)而言， 係由多數個具有極佳導電性之導線接腳(2)所組成，且係呈 10 左右、前後順序排列集結（第一圖係以一組左右排列之導 線接腳(2)承載一晶片（3)之剖視圖呈現），而各該導線接腳 (2)大致形成有一前段(2a)—中段(2b)及一末段(2c)，而可將 該晶片（3)固置於該等前段(2a)頂面上，並藉由多數之金屬 引線(4)將該晶片（3)與各該前段(2a)底面一一連接，該中段 15 (2b)係自該前段（2b)延伸一預定之距離而成，且係經彎折 後而與該前段（2a)形成有一預定之角度，該末段（2c)則係 自該中段(2b)延伸而成，且與該中段(2b)間形成有一預定 之角度，並使該末段(2c)與該前段（2a)間約略概成平行， 而由一保護體（5)將該晶片（3)與該導線架（1)進行包覆作 2〇 業，並使各該導線接腳(2)之末段(2c)露出該保護體（5)夕卜， 使各該末段（2c)可連接於外界之電路板（圖中未示）上，而 可藉由各該導線接腳(2)作為該晶片（3)與外界間之傳導介 面，進而將其電性傳導於外者。 -3- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） I-------11 --------t ---1---- (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 C7 ---------21 五、創作說明（） 惟，就上述之各導線接腳（2)而言，其製程係以一平直 片體沖壓二處成型該前段(2a)、中段(2b)及後段(2c)，而為 了沖壓成型之穩定性，該中段(2b)需具有特定之長度，以 維持該前段（2a)與該後段（2c)間之相對位置；換言之，用 5 以連接該晶片（3)之前段（2a)至用以連接外界之末段（2c)間 距離過長，將使得該晶片（3)在施以外部之封裝後，其整體 之體積過大，而無法因應現今晶片封裝追求輕、薄、短、 小之趨勢；且由於各該導線接腳（2)之前段(2a)與未段（2c) 間距離過長之原故，致使該晶片（3)之電性必須先傳經前段 10 (2a)及中段(2b)後，再行傳導至該末段(2c)上，最後方能由 該末段(2c)將其電性導傳於外界者，該晶片（3)之電性必須 經由如此漫長之傳導過程下（電性傳導路徑如笫一圖之P1 所示），將對晶片（3)之運用效率產生影響，進而有延遲作 用之現象發生，對該晶片（3)之運算速度將大打折扣；另， I5 由於此種導線接腳(2)之形狀複雜，將使得製造上之難度較 高，使其製造成本相對提高；換言之，即係各該導線接腳 (2)之前段(2a)與後段（2c)必須呈相互平行之狀態，將使其 加工極為不易’進而使传成品之不良率提向’而增加生產 製造之成本。 20 另外，由於此種導線接腳(2)與外界傳導之接點，僅限 於該導線接腳(2)之末段(2c)上，除使得該導線接腳(2)與外 界之接點受到局限而無法廣泛之擴張外，更使各該導線接 腳(2)因與外界間僅具有單一之接點，而極易有接觸或傳導 不良之後果產生。 -4- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） — — — — — — — — — II »111111— — — — — — — — — — . (請先閲讀背I之注意事項再填寫本頁) 515069 C7 _D7___ 五、創作說明（） 有鑑於上述之種種缺失，本案發明人乃經詳思細索， 並累積多年從事晶片封裝製造及研究開發之經驗，終而有 本發明之產生。 亦即本發明之主要目的乃在提供一種導線架結構，係 5 可用以加速晶片電性之傳導者。 本發明之另一目的乃在提供·一種導線架結構，係具有 與外界較為廣泛而靈活之傳導接點者。 本發明之又一目的乃在於提供一種導線架結構，其製 程快速簡易，可提高產品之良率者。 10 緣以，為達上述目的，本發明所提供一種導線架結 構，係用以承載晶片，且可將晶片之電性導通於外者，其 主要包含有：多數呈聚集排列之導線接腳，各該導線接腳 係分別概成塊狀，具有一頂面及一位於該頂面反側之底 面，該頂面係用以承載上述之晶片，該底面之預定位置處 15 則往該頂面凹陷一預定之深度，而可藉由凹陷後之表面與 該晶片電性連接者，並於未受凹陷之處自然形成至少一連 接部，且該連接部係相對該凹陷區呈凸出狀，而可用以與 外界連結，而將晶片之電性導通於外者。 經濟部智慧財產局員工消費合作社印製 -------------^1-裝--------訂 i (請先閱讀背面之注意事項再填寫本頁) 為使貴審查委員能更詳細暸解本發明之實際構造及特 20 點，茲列舉以下實施例並配合圖示詳細說明如后，其中： 第一圖係一種習用晶片封裝之剖視圖。 第二圖係本發明笫一較佳實施例之使用狀態剖視圖。 第三圖係笫二圖所示實施例於使用狀態之局部剖視 圖。 -5- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 經濟部智慧財產局員工消費合作社印製 515069 C7 D7_ 五、創作說明（） 笫四圖係笫二圖所示較佳實施例之底視圖。 笫五圖係本發明笫二較佳實施例之底視圖。 笫六圖係本發明笫三較佳實施例之立體圖。 笫七圖係笫六圖所示較佳實施例之底視圖。 5 請參閱第二至第四圖，係本發明導線架結構（1〇)之第 一較佳實施例，除了該導線架（10)外，圖中更揭露有一晶 片組(20)、多數之金屬引線(30)及一保護體(40)其中；· 如笫二及笫三圖所示，該導線架（10)具有複數個呈聚 集排列之導線接腳（11)(本實施例中係以多組呈左右排列之 ίο 導線接腳呈現），各該導線接腳（11)係分別概呈塊狀之型 態，其具有一頂面（111)及一位於該頂面（111)反侧之底面 (112)，且自該各導線接腳（11)中段底面（112)向外延伸之周 緣上，並經由蝕刻（或其它可達成與蝕刻相同目的之加工 方法）一預定之深度後，使其中段底面（112)之周緣處，在 15 經蝕刻後形成有一凹陷區（113)，且於經由蝕刻後之表面上 形成有一與該凹陷區（113)鄰接之連結面（114)，及一與該 連結面（114)及該底面（112)相連接之壁面（115)，而可使該 導線接腳（11)中段之周緣厚度在經由蝕刻後相對地縮減， 由於該底面（112)之中段處，係未經蝕刻之作用，而可自然 20 相對該凹陷區（113)而形成一凸出之連接部（116)，且位於 該連接部（116)上之底面（112)至該頂面（111)間之直線距離 約係為0.4丽。 上述即為本創作導線架結構（10)笫一較佳實施例之主 要結構，接著再將該導線架（10)之使用狀態介紹如后： -6- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ------I------------訂 -------- (請先閱讀背面之注意事項再填寫本頁) 515069 C7 D7 五、創作說明（） 請參閱第二及笫三圖，首先，藉由環氣樹脂、矽樹 脂、低熔點之玻璃或雙面膠帶…等黏性材料（21)，將該晶 片組（20)(本實施例中該晶片組係以單一晶片表示）之一端 面黏著於各該導線接腳（11)之頂面（1Π)預定位置上，使該 5 晶片組（20)位於左右倆倆相對之導線接腳（11)中央位置 處，進而使該導線架（10)形成有一連通該頂面（111)至該底 面（112)間之通道（12)，且該晶片組(20)之中央位置處具有 多數之銲墊(22)，而該銲墊P2)係正好位於該通道（12)中， 可藉由該各金屬引線(3〇)將該晶片組(20)之銲墊(22)——連 ίο 接並導通於各該導線接腳（11)之連結面（114)上，使該晶片 組（20)之電性可藉由各該金屬引線（30)而傳導至各該導線 接腳（11)上，並再藉由一保護體(40)，該保護體(40)係可為 環氣樹脂（Epoxy)、矽樹脂（Silicone)、丙稀酸樹脂 (Aery lie)…等絕緣材料，進行熱壓模包覆作業，進而將該 15 晶片組(20)、該導線架（10)及該金屬引線(30)包覆於其中， 而僅將各該導線接腳（11)連接部（116)上之各該底面（112)露 出於該保護體（40)之外，以作為該晶片組（20)與外界電性 連接之介面者（如第四圖所示）。 於此，本實施例中所提供之導線架，其結構及造形不 20 僅簡單，而有利於製造上之方便及節省製造之成本，且由 於其凸伸之連接部凸出之厚度極小，因此可大幅減低整體 封裝後之體積；並由於該導線架之體積在相對簡化及縮小 後，可使得與該晶片組上之接點至與外界電路板間之接點 距離隨之縮減，進而使得在傳導晶片電性之速度上（其導 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閲讀背面之注意事項再填寫本頁) 裝 ----訂--- 經濟部智慧財產局員工消費合作社印製 515069 經濟部智慧財產局員X消費合作社印製 C7 D7 五、創作說明（） 電路線如笫二圖之P2所示）更加快速，以利符合現今科技 之潮流趨勢。 另外，該導線接腳之連接部，亦可依不同之封裝需 求，而形成於該導線接腳之前段、中段、末段或任一預定 5 之位置處。 請參閱笫五圖所示，係本發明導線架結構（50)笫二較 佳實施例之使用態樣；圖中更揭露有一晶片組(20)、多數 之金屬引線（30)及一保護體（4〇)，其與上述實施例之主要 差異在於，其中； 10 該導線架（50)之該各導線接腳（51)之連接部（516)，係 依序交錯形成於各導線接腳（51)之未段或中段上，而可藉 由交錯之不同位置與外界連結，可較習知結構具有與外界 更靈活而廣泛之傳導接點。 請參閱第六及笫七圖，係本發明導線架結構（6〇)之第 15三較佳實施例，除了該導線架(60)外，圖中更揭露有一晶 片組(20)、夕數金屬引線(30)及一保護體(4〇);其與上述實 施例之主要差異在； 該導線架(60)之各該導線接腳(61)之中段及末段處，分 別形成有一連接部（616)(617)，而使該中段與該末段間亦 2〇形成有/第二凹陷區（618)，使各該導線接腳（61)與外界之 〜電路板（圖中未示）連接時，乃可具有較多與該電路板（圖 中未示）接觸之接觸接點（如笫七圖所示），使該導線架（6〇) 掭有較為廣泛並可靈活運用之接觸接點；換言之，即可擁 有多數用以傳導該晶片組（2〇)電性之接點，而能夠加以確 ----^ ^------------ (請先閱讀背面之注意事項再填寫本頁) -8- 515069 C7 D7 五、創作說明（ 保傳導該晶片組（20)電性時之穩定性，以避免由單點接觸 時，會有發生接觸不良而進而影響或降低整體傳導之效果 者。 综上所述，本發明之導線架結構，確實具有其進步實 用性’且在使用上之方便’ X ’本發明μ請前並無相同 物品見於刊物或公開使用，是以.，本發明實已具備發明專 利要件’為保障發明人之苦思，爰依法提出申請。 (請先閱讀背面之注意事項再填寫本頁) 裝 ----訂--- 禮 經濟部智慧財產局員工消費合作社印製Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 515069 C7 D7_ One. V. Creative Instructions () This invention relates to chip packaging, and more specifically refers to a lead frame structure for chip packaging. According to the general integrated circuit chip is extremely fragile, it must be properly packaged outside to ensure that it is not easily contaminated or damaged by external forces during use, and the electrical properties of the chip must be moderately conducted. Only when it is connected to a circuit board or a carrier board or a lead frame can it be effectively conducted to external users through the circuit board or the carrier board or the lead frame. Here, please refer to the first picture. As far as the current lead frame (1) is concerned, it is composed of a plurality of lead pins (2) with excellent electrical conductivity, and is arranged in an order of about 10 in front and back. (The first figure is a cross-sectional view showing a set of left and right wire pins (2) carrying a chip (3)), and each of the wire pins (2) is roughly formed with a front section (2a)-a middle section (2b) and One end section (2c), the wafer (3) can be fixed on the top surface of the front sections (2a), and the wafer (3) and each of the front sections (2a) can be fixed by a majority of metal leads (4). ) The bottom faces are connected one by one. The middle section 15 (2b) is formed by extending a predetermined distance from the front section (2b), and is bent to form a predetermined angle with the front section (2a). 2c) is extended from the middle section (2b) and forms a predetermined angle with the middle section (2b), and makes the last section (2c) and the front section (2a) approximately parallel, and A protective body (5) covers the chip (3) and the lead frame (1) as a 20 industry, and exposes the protective body (5) to the last section (2c) of each of the lead pins (2). Xi Bu, make each deserve The segment (2c) can be connected to an external circuit board (not shown in the figure), and each of the lead pins (2) can be used as a conductive interface between the chip (3) and the outside, thereby electrically conducting it. Outsiders. -3- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) I ------- 11 -------- t --- 1 ---- (Please (Please read the notes on the back before filling this page) Printed C7 by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs --------- 21 V. Creation Instructions () However, the above-mentioned lead pins (2) In terms of the manufacturing process, the front section (2a), the middle section (2b), and the rear section (2c) are formed by punching two flat pieces, and the middle section (2b) needs to have a specific length for the stability of stamping. To maintain the relative position between the front section (2a) and the rear section (2c); in other words, the distance between the front section (2a) of the chip (3) and the last section (2c) used to connect to the outside is too long with 5 After the external package is applied, the overall volume of the chip (3) is too large to meet the current trend of light, thin, short and small chip packages; and because each of the lead pins (2) The reason that the distance between the segment (2a) and the segment (2c) is too long, so that the electrical properties of the chip (3) must first be transmitted through the previous segment 10 (2a) and the middle segment (2b), and then conducted to the final segment (2c). ), Most In order to be able to conduct its electrical conductance to the outside world from the last paragraph (2c), the electrical properties of the chip (3) must go through such a long conduction process (the electrical conduction path is shown as P1 in the first figure), Will affect the use efficiency of the chip (3), and then the phenomenon of delay will occur, the operation speed of the chip (3) will be greatly reduced; In addition, because of the complex shape of this wire pin (2), This makes the manufacturing difficult and the manufacturing cost relatively high; in other words, the front section (2a) and the back section (2c) of each lead pin (2) must be parallel to each other, making it extremely difficult to process 'Further improve the defect rate of the finished product' and increase the cost of production. 20 In addition, the contact between the lead pin (2) and the outside world is limited to the last section (2c) of the lead pin (2), except for the contact between the lead pin (2) and the outside world Due to the limitation that it cannot be extensively expanded, each of the lead pins (2) has only a single contact point with the outside world, and it is very easy to have the consequences of poor contact or conduction. -4- This paper size applies to China National Standard (CNS) A4 specifications (210 X 297 mm) — — — — — — — — — II »111111— — — — — — — — — — — (Please read the back first (Notes for I will fill in this page again) 515069 C7 _D7___ V. Creation Instructions () In view of the above-mentioned shortcomings, the inventor of this case has carefully considered and accumulated years of experience in chip packaging manufacturing and research and development, and finally There is the invention. That is, the main object of the present invention is to provide a lead frame structure, which can be used to accelerate the electrical conductivity of the chip. Another object of the present invention is to provide a lead frame structure which has a wide range of flexible contact points with the outside world. Another object of the present invention is to provide a lead frame structure, which can be manufactured quickly and easily, and can improve the yield of the product. For this reason, in order to achieve the above object, the present invention provides a lead frame structure, which is used to carry a chip, and can electrically conduct the chip to the outside, which mainly includes: most of the lead pins arranged in an aggregate, Each of the lead pins is roughly block-shaped, and has a top surface and a bottom surface located on the opposite side of the top surface. The top surface is used to carry the above-mentioned chip, and the predetermined position of the bottom surface is 15 toward the top surface. The depression has a predetermined depth, and the surface of the depression can be electrically connected to the chip, and at least one connection portion is naturally formed in the place not subject to the depression, and the connection portion is convex relative to the depression area. And can be used to connect with the outside world, and electrically connect the chip to the outside. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs ------------- ^ 1-Pack -------- Order i (Please read the precautions on the back before filling this page) In order to enable your reviewing committee to understand the actual structure and features of the present invention in more detail, the following examples are listed in detail with the illustrations as follows, where: The first diagram is a cross-sectional view of a conventional chip package. The second figure is a sectional view of a use state of a first preferred embodiment of the present invention. The third figure is a partial cross-sectional view of the embodiment shown in FIG. 22 in the use state. -5- This paper size is in accordance with China National Standard (CNS) A4 (210 X 297 mm) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 515069 C7 D7_ V. Creation Instructions () Figure 4 is shown in Figure 2 Bottom view of the preferred embodiment. The fifth diagram is a bottom view of the second preferred embodiment of the present invention. The twenty-sixth figure is a perspective view of the third preferred embodiment of the present invention. The seventh figure is a bottom view of the preferred embodiment shown in the sixth figure. 5 Please refer to the second to fourth figures, which are the first preferred embodiment of the lead frame structure (10) of the present invention. In addition to the lead frame (10), a chipset (20), most of which are also disclosed in the figure. Among the metal leads (30) and a protective body (40), as shown in Figures 2 and 3, the lead frame (10) has a plurality of lead pins (11) arranged in an assembly (in this embodiment, Presented by multiple sets of lead pins arranged side by side), each of the lead pins (11) is roughly block-shaped, and has a top surface (111) and an opposite side of the top surface (111) The bottom surface (112) of the lead pins (11), and the peripheral edge extending outwardly from the bottom surface (112) of the lead pins (11), and after etching (or other processing methods that can achieve the same purpose as etching) a predetermined depth, A recessed area (113) is formed at the periphery of the bottom surface (112) of the middle section after etching, and a connecting surface (114) adjacent to the recessed area (113) is formed on the etched surface, and A wall surface (115) connected to the connecting surface (114) and the bottom surface (112), so that the lead pin (11) The thickness of the peripheral edge of the middle section is relatively reduced after being etched. Since the middle section of the bottom surface (112) is not etched, it is natural to form a protruding connection portion (116) relative to the recessed area (113). ), And the linear distance between the bottom surface (112) on the connecting portion (116) and the top surface (111) is about 0.4 li. The above is the main structure of the lead frame structure (10), a preferred embodiment of the creation, and then the use state of the lead frame (10) is introduced as follows: -6- This paper size applies to Chinese National Standards (CNS) A4 specification (210 X 297 mm) ------ I ------------ Order -------- (Please read the precautions on the back before filling this page) 515069 C7 D7 V. Creation instructions () Please refer to the second and third pictures. First, the chip set is made of viscous materials (21) such as gas resin, silicone resin, low melting glass or double-sided tape ... (20) (The chipset is represented by a single chip in this embodiment) One end surface is adhered to a predetermined position on the top surface (1Π) of each of the lead pins (11), so that the 5 chipset (20) is located on the left and right. The two opposite lead pins (11) are at the central position, so that the lead frame (10) forms a channel (12) connecting the top surface (111) to the bottom surface (112), and the chipset ( 20) has a large number of pads (22) at the center position, and the pad P2) is located in the channel (12). The chip set (20) can be connected by the metal leads (30). weld Pad (22) —— connected and connected to the connecting surface (114) of each lead pin (11), so that the electrical properties of the chipset (20) can be conducted through each of the metal leads (30) To each of the lead pins (11), and then by a protective body (40), the protective body (40) can be epoxy resin, silicone resin, acrylic resin (Aery lie) ... and other insulating materials to perform the hot stamping coating operation, and then cover the 15 chipset (20), the lead frame (10), and the metal lead (30), and only connect each of the wires Each of the bottom surfaces (112) on the connecting portion (116) of the leg (11) is exposed outside the protective body (40), and serves as an interface for electrically connecting the chipset (20) to the outside (as shown in the fourth figure). Show). Here, the lead frame provided in this embodiment is not only simple in structure and shape, but also facilitates manufacturing convenience and saves manufacturing cost. Because the protruding thickness of the protruding connecting portion is extremely small, it can be used. Significantly reduce the volume of the overall package; and because the volume of the lead frame is relatively simplified and reduced, the distance from the contact point on the chipset to the contact point with the external circuit board will be reduced accordingly, thereby making conduction The chip's electrical speed (its guide paper size is in accordance with Chinese National Standard (CNS) A4 specification (210 X 297 mm) (Please read the precautions on the back before filling this page)) Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs and the Consumer Cooperatives 515069 Printed by the Intellectual Property Bureau of the Ministry of Economics and X by the Consumer Cooperatives C7 D7 V. Creation Instructions () The circuit lines are shown as P2 in the second figure) Faster to meet the current trend of technology trend. In addition, the connecting portion of the wire pin may be formed at the front section, the middle section, the last section or any predetermined 5 positions according to different packaging requirements. Please refer to Figure 25, which shows the use of the second preferred embodiment of the lead frame structure (50) of the present invention. The figure further discloses a chipset (20), most metal leads (30), and a protective body. (40), the main difference from the above embodiment lies in: 10; the connecting portions (516) of the lead pins (51) of the lead frame (50) are sequentially staggered and formed on the lead pins (51) can be connected to the outside by intersecting different positions, which can have more flexible and extensive conductive contact with the outside than the conventional structure. Please refer to the sixth and twenty-seventh drawings, which are the fifteenth and third preferred embodiments of the lead frame structure (60) of the present invention. In addition to the lead frame (60), the figure further discloses a chipset (20) and evening numbers. The metal lead (30) and a protective body (40); the main differences from the above embodiment are; the middle and the last section of each of the lead pins (61) of the lead frame (60) respectively form a connection (616) (617), and a second recessed area (618) is formed between the middle section and the last section, so that each of the lead pins (61) and the outside of the circuit board (not shown in the figure) (Shown) when connected, it can have more contact contacts (as shown in Figure 7) that make contact with the circuit board (not shown), so that the lead frame (60) can be widely used and can be used flexibly. In other words, you can have most of the contacts used to conduct the electrical properties of the chipset (20), and you can confirm it ^^ ------------ ( Please read the precautions on the back before filling in this page) -8- 515069 C7 D7 V. Creation instructions (to ensure the electrical stability of the chipset (20) when conducting, to avoid contact from a single point of contact Those who are unfavorable and thus affect or reduce the overall conduction effect. In summary, the lead frame structure of the present invention does have its practicability, and it is convenient to use. X The publication or public use is based on the fact that the present invention already has the elements of an invention patent. "In order to protect the inventor's hard work, apply according to law. (Please read the precautions on the back before filling this page) --- Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs

515069 C7 D7 10 經濟部智慧財產局員工消費合作社印製 五、創作說明（ 簡單圖示說明： 第一圖係一種習用晶片封裝之剖視圖。 第二圖係本發明笫一較佳實施例之使用狀態剖視圖。 第三圖係笫二圖所示實施例於使用狀態之局部剖視 圖。 笫四圖係笫二圖所示較佳實施例之底視圖。 笫五圖係本發明笫二較佳實施例之底視圖。 笫六圖係本發明笫三較佳實施例之立體圖。 笫七圖係笫六圖所示較佳實施例之底視圖。 圖號說明： 「第一較佳實施例」 1 5 20 導線架結構（10) 導線接腳（11) 頂面（111) 底面（112) 凹陷區（113) 連結面（114) 壁面（115) 連接部（116) 通道（12) 晶片組（20) 黏性材料（21) 銲墊(22) 金屬引線(30) 保護體(40) 「第二較佳實施例」 導線架結構(50) 導線接腳(51) 連接部（516) 晶片組(20) 金屬引線(30) 保護體(40) 「第三較佳實施例」 導線架結構(60) 導線接腳(61) 連接部（616)(617) 第二凹陷區（618) 晶片組(20) 金屬引線(30) 保護體(40) -10- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） --------------------^--------- (請先閱讀背面之注意事項再填寫本頁)515069 C7 D7 10 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Creative instructions (simple illustration: the first picture is a cross-sectional view of a conventional chip package. The second picture is the state of use of the first preferred embodiment of the present invention Sectional view. Figure 3 is a partial sectional view of the embodiment shown in Figure 2 in use. Figure 4 is a bottom view of the preferred embodiment shown in Figure 2. Figure 5 is a preferred embodiment of the second embodiment of the present invention. Bottom view. Fig. 6 is a perspective view of the third preferred embodiment of the present invention. Fig. 7 is a bottom view of the preferred embodiment shown in Fig. 6. Fig. Number description: "First Preferred Embodiment" 1 5 20 Lead frame structure (10) Lead pins (11) Top surface (111) Bottom surface (112) Depression area (113) Connection surface (114) Wall surface (115) Connection portion (116) Channel (12) Chipset (20) Adhesive Material (21) pad (22) metal lead (30) protective body (40) "second preferred embodiment" lead frame structure (50) lead pin (51) connection portion (516) chip set (20) Metal lead (30) Protective body (40) "Third preferred embodiment" Lead frame structure (60) Lead pins (61) Connections (616) (617) Second recessed area (618) Chipset (20) Metal leads (30) Protective body (40) -10- This paper size applies to China National Standard (CNS) A4 Specifications (210 X 297 mm) -------------------- ^ --------- (Please read the notes on the back before filling this page )

Claims (1)

515069 ABCD 六、申請專利範圍 1 ·一種導線架結構，係用以承載晶片，且可將晶片之 電性導通於外者，其主要包含有：多數呈聚集排列之導線 接腳，各該導線接腳係分別概成塊狀，具有一頂面及一位 於該頂面反側之底面，該頂面係用以承載上述之晶片，該 5 底面之預定位置處則往該頂面凹陷一預定之深度，而可藉 由凹陷後之表面與該晶片電性連接者，並於未受凹陷之處 自然形成至少一連接部，且該連接部係相對該凹陷區呈凸 出狀，而可用以與外界連結，而將晶片之電性導通於外 者。 1〇 2 ·依據申請專利範圍笫1項所述之導線架結構，其中 該底面至該頂面之高度約為0.4匪。 3 ·依據申請專利範圍笫1項所述之導線架結構，其中 該底面凹陷處形成有至少一凹陷區，該凹陷區係以蝕刻形 成。 15 4 ·依據申請專利範圍笫1項所述之導線架結構，其中 凹陷後之表面上形成有一與該底面相連接之壁面及一與該 壁面相連之連結面，並藉由多數金屬引線將該連結面與該 晶片連接，而可將該晶片之電性分別傳導至該各導線接腳 者。 20 5 ·依據申請專利範圍笫1項所述之導線架結構，其中 該連接部係形成於該導線接腳之前段者。 6 ·依據申請專利範圍笫1項所述導線架之結構，其中 該連接部係形成於該導線接腳之中段者。 -11- 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） ^-- (請先閲讀背面之注意事項再填1!^頁) 訂 經濟部智慧財產局員工消費合作社印製 515069 A8 B8 C8 D8 申請專利範圍 7 ·依據申請專利範圍笫1項所述之導線架結構，其中 該連接部係形成於該導線接腳之末段者。 8 ·依據申請專利範圍笫1項所述之導線架結構，其中 該連接部係形成於該導線接腳之中段及末段者。 (請先閱讀背面之注意事項再填. 裝—— 頁 訂 線· 經濟部智慧財產局員工消費合作社印製 12- 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐）515069 ABCD VI. Scope of patent application1. A lead frame structure is used to carry the chip and can electrically connect the chip to the outside. It mainly includes: most of the wire pins arranged in an aggregate, and each of the wire pins is connected. The feet are generally block-shaped, with a top surface and a bottom surface located on the opposite side of the top surface. The top surface is used to carry the above-mentioned wafers. The predetermined position of the 5 bottom surfaces is recessed to the top surface by a predetermined amount. Depth, and the surface after the recess is electrically connected to the chip, and at least one connection portion is naturally formed in the unrecessed place, and the connection portion is convex with respect to the recessed area, and can be used to communicate with The outside is connected, and the chip is electrically connected to the outside. 102. The lead frame structure according to item 1 of the scope of the patent application, wherein the height from the bottom surface to the top surface is about 0.4 band. 3. The leadframe structure according to item 1 of the scope of the patent application, wherein the bottom surface is recessed with at least one recessed area, and the recessed area is formed by etching. 15 4 · According to the lead frame structure described in item 1 of the scope of the patent application, the recessed surface is formed with a wall surface connected to the bottom surface and a connection surface connected to the wall surface, and the metal surface The connecting surface is connected to the chip, and the electrical properties of the chip can be respectively conducted to the lead pins. 20 5 · According to the lead frame structure described in item 1 of the scope of patent application, wherein the connecting portion is formed before the lead pin. 6. The structure of the lead frame according to item 1 of the scope of the patent application, wherein the connecting portion is formed in the middle of the lead pin. -11- This paper size applies Chinese National Standard (CNS) A4 specification (210X297 mm) ^-(Please read the precautions on the back before filling in 1! ^ Pages) Order printed by the Intellectual Property Bureau of the Ministry of Economic Affairs Consumer Cooperatives 515069 A8 B8 C8 D8 Patent application scope 7 · According to the lead frame structure described in item 1 of the patent application scope, wherein the connecting portion is formed at the end of the wire pin. 8. The lead frame structure according to item 1 of the scope of the patent application, wherein the connecting portion is formed in the middle and last sections of the lead pins. (Please read the precautions on the back before filling. Packing-Page Ordering · Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 12- This paper size applies to the Chinese National Standard (CNS) A4 specification (210X 297 mm)
TW90129168A 2001-11-26 2001-11-26 Lead frame structure TW515069B (en)

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