514744 A7 ___ B7 五、發明說明（丨） 本發明之锯城 本發明普遍相關於用以測試半導體裝置之自動測試系 統，更特別的相關於一高解析度時差檢測系統及方法，用 於本設備上的定時校準和/或定時驗證。 發明背畺 半導體設備之製造涉及大量的處理過程，其需被小心 的控管以使生產率及設備產量達到最大。更重要的處理步 驟之一爲使用自動測試設備以驗證設備的功能。此種測試 通常表現在晶圓階段和封裝設備階段。一般而言，測試程 序包含沿著測試器通道的每個設備測試波型之應用及捕獲 ，以及決定是否捕獲的訊號符合期望値。此測試器通道使 用傳輸線以將測試器耦合至DUT接腳。 爲了成功的測試一正在測試之設備（device-under-test， DUT)，供應到設備接腳之訊號沿著每條傳輸線必須在相關 於其他每個訊號的準確時點上到達。按照測試訊號的路線 至DUT的傳輸線通常有不同的長度，爲每個訊號在傳播時 間中貢獻微小但重要的相關延遲。結果，爲了精確控制訊 號時間，每個通道的延遲通常必須在定時校準程序之前就 爲已知並被補償。 決定在測試通道之間相關訊號延遲的主要方法之一， 涉及驅動沿著每一通道傳輸線的訊號，和測量相對邊緣至 邊緣（edge-to-edge)的時間變動，或稱時差。〜旦時差爲已 知，每個信號的定時可被運用來校準需要的邊緣，以達到 4 本紙張尺度適用中國國家標準（CNS)A4規格（210x297公釐） (請先閱讀背面之注意事項ml·· 寫本頁) 經濟部智慧財產局員工消費合作社印製 514744 ___ Β7__ 五、發明說明（> ) 在DUT接腳欲得的定時準確度。 I-------- (請先閱讀背面之注意事項ml寫本頁) 許多在技藝中用以測量在遲滯測試訊號之間的相關時 差爲已知技術。例如，檢測時差較爲普及的方法之一，是 引用以D正反器爲基礎之閂鎖比較器，其一般被參照爲游 標校準技術（Vernier calibration technique)。一目標訊號輸 入至正反器之資料部分，而一參考訊號供至閃控電路部分 。使用此種技術，該參考訊號簡易地閂鎖住以兩訊號之時 差爲準的一高或低値。經由在輕微不同的頻率或時間位置 ，使用一參考震盪器，可從輸出端收集足夠之資訊，以決 定時差的相對大小。 --線. 另一個以正反器爲基礎用以檢測時差之技術，其引用 一互斥或閘(X〇R gate)與多個D正反器耦合，例如可從類 比設備公司（Analog Device Corporation)獲得模型 AD9901 的相/頻率鑑別器。此種結構產生以時差大小爲準，可變化 脈波寬度之訊號，如同訊號時差極性一樣。當與充電幫浦 結合使用時，此電路也可以供應一直流訊號，表示時差檢 測的位準。 經濟部智慧財產局員工消費合作社印制π 另一個由Feldman所提出的時差檢測系統，類似於上 述的互斥或閘充電幫浦結構，利用設定一重設（Set-Reset， SR)正反器伴隨設置在輸出端的充電幫浦。此種SR正反器 在目標訊號到SET埠時，啓動正反器的脈波。資料埠在電 路操作時皆保持在低態。此種特別的電路具有附加的好處 ，大多數依賴電壓的元件，例如電流源、開關、電容等等 ，具有相當的固定電壓供應其上。如此可使非線性問題最 5 氏張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） "~: 514744 Α7 Β7 五、發明說明（3514744 A7 ___ B7 V. Description of the invention (丨) The invention of the present invention is generally related to an automatic test system for testing semiconductor devices, and more particularly to a high-resolution time difference detection system and method for use in this device Timing calibration and / or timing verification. BACKGROUND OF THE INVENTION The manufacture of semiconductor equipment involves a large number of processes, which need to be carefully controlled to maximize productivity and equipment output. One of the more important processing steps is to use automatic test equipment to verify the functionality of the equipment. This type of testing typically occurs at the wafer stage and packaging equipment stage. Generally speaking, the test procedure involves the application and capture of test waveforms for each device along the tester channel, and determining whether the captured signal meets expectations. This tester channel uses a transmission line to couple the tester to the DUT pins. In order to successfully test a device-under-test (DUT), the signals supplied to the device pins must arrive along each transmission line at the exact time point associated with each other signal. The transmission lines to the DUT according to the route of the test signal usually have different lengths, and each signal contributes a small but significant related delay in the propagation time. As a result, in order to precisely control the signal time, the delay of each channel must usually be known and compensated before the timing calibration procedure. One of the main methods to determine the relative signal delay between test channels involves driving the signal along the transmission line along each channel and measuring the relative edge-to-edge time variation, or time difference. ~ Once the time difference is known, the timing of each signal can be used to calibrate the required edges to achieve 4 paper sizes applicable to the Chinese National Standard (CNS) A4 specification (210x297 mm) (Please read the precautions on the back first ml ·· Write this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 514744 ___ Β7__ 5. Description of the invention (&) The accuracy of the timing required at the DUT pin. I -------- (Please read the note on the back first to write this page) Many techniques used in the art to measure the correlation time difference between hysteresis test signals are known techniques. For example, one of the more popular methods for detecting time difference is to use a latch comparator based on the D flip-flop, which is generally referred to as the Vernier calibration technique. A target signal is input to the data part of the flip-flop, and a reference signal is supplied to the flash control circuit part. Using this technique, the reference signal simply latches a high or low signal based on the time difference between the two signals. By using a reference oscillator at slightly different frequencies or time locations, sufficient information can be collected from the output to determine the relative magnitude of the timing difference. --Line. Another technology based on flip-flops to detect time difference, which uses a mutual exclusion or gate (X〇R gate) coupled with multiple D flip-flops, for example from Analog Device Company (Analog Device Corporation) to obtain a phase / frequency discriminator for model AD9901. This structure produces a signal that can vary the pulse width based on the time difference, just like the signal time difference polarity. When used in conjunction with a charging pump, this circuit can also supply a DC signal, indicating the level of time difference detection. Printed by the Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs. Set the charging pump at the output. This SR flip-flop starts the pulse of the flip-flop when the target signal reaches the SET port. The data port stays low during circuit operation. This particular circuit has the added benefit that most voltage-dependent components, such as current sources, switches, capacitors, etc., have a fairly fixed voltage supply on them. In this way, the non-linear problem can be applied to the Chinese standard (CNS) A4 specification (210 X 297 mm) at the 5th Zhang scale. &Quot; ~: 514744 Α7 Β7 V. Description of the invention (3
m ，請 ^委 I PIΪ斧 'i η % η 瓜:參 化。 當上述以正反器爲基礎的時差檢測系統欲在相關應用 上使用時，皆因亞穩定，或跳動而具有受限的線性範圍。 此爲一種當正反器製造有效的上傳或下傳信號時的內部特 徵。結果，在較高頻率操作時，檢測器的解析度變差，使 得訊號與訊號間的時差變得無法檢測。 由Otsuji所提出，使用適用於實現在積體電路上的時 間-對-電壓轉換技術，以努力避免亞穩定狀態存在於以正 反器爲基礎的時差檢測器內部。此種技術引用標準轉換器， 用以接收從半導體測試器的一個通道而來的參考訊號以及 測試訊號並將其正規化。標準轉換器方塊的輸出端親合至 差動放大器的輸入端。此放大器產生一脈波，其具有正比 於在參考訊號與測試訊號之間的相關時差的振幅。當閃控 電路產生與輸入訊號的上升邊緣同步之閃頻的時候，此脈 波傳送至互補式D閂鎖。Q埠以及Q/埠的輸出位準根據時 差的極性而固定在互補式位準中。 雖然此種電路對於同相位時差可以成功的轉換至不同 電壓有所貢獻，對於非同相位卻還沒有準備。隨著差動測 試器通道在半導體測試器中的擴大實現，非同相位時差檢 測變得日趨重要。 上述的習知時差檢測結構及技術，顯示了達成定時校 準與驗證精準度的限制。然而同樣重要的是在習知定時校 準和/或驗證過程中不需要的時間持續。傳統上，一旦測試 器完成了其校準，一個獨立的驗證裝置被引進’以驗證其 (請先閱讀背面之注意事項再填寫本頁) ---!!訂---------線 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公t ) 經濟部智慧財產局員工消費合作社印製 514744 A7 B7 五、發明說明（处） 精準度。通常，爲了檢測通道對通道的時差，自動閃控近 似地被佈置在DUT分開的步驟，遍布每一個通道以便檢測 通道對通道的時差。不幸的是，隨著從三百個到六百個通 道到處都有引進近代測試器，習知上用於自動閃控的資料 獲取時間，可能需要達到十四個小時或更多。如此造成用 於製造目的的損失測試器時間，以及對應的較低全部生產 率。 迄今爲止，所需要而未獲得的是高解析度時差檢測電 路及方法，用於半導體測試器中，其可精確的檢測非常小 的時差，以及提供一輸出訊號其可允許快速的定時校準驗 證。本發明的此種高解析度時差檢測電路及方法滿足這些 需求。 本發明之槪要 本發明之高解析度時差檢測電路及方法，提供一種同 相位以及非同相位訊號時差二者的精確檢測，而其不具有 亞穩定跳動之多餘效應。另外，本發明使得經由在並聯之 多重通道及設備上直接測量的此種製造環境下具有高生產 率。爲實現上述優點，本發明一方面形成一種包含多相位 輸入電路之高解析度時差檢測電路。此輸入電路具有參考 信號輸入，時差信號輸入，並且可以適應用來接受同相位 及/或非同相位之時差信號。此輸入電路爲了回應控制信號 ，係作用使時差信號通過或將其反向。此檢測器也包含時 間至電壓轉換電路，其具有用於接收已時差化信號及參考 7 本紙張尺度適用中國國家標準（CNS)A4規格（21〇 X 297公爱) "" "" --------------裝--- (請先閱讀背面之注意事項βι寫本頁) 訂· · -丨線· 514744 A7 B7 五、發明說明（<) --------------裝--- (請先閱讀背面之注意事項H寫本頁) ，線· 信號之個別的第一輸入和第二輸入；以及包含用於產生一 相對時差信號之差動放大器，此相對時差信號表示出在參 考信號及時差信號之間的相對時差。捕獲電路係耦合到時 間至電壓轉換電路，用以檢測相對時差信號。在另一方面 ，本發明包含一種用於量測在複數個傳播信號與參考信號 之間的相對時差。此種時差檢測電路包含一選擇器電路， 其具有複數個被調適用來接收傳播信號的輸入端，以及一 個用以選擇性地讓用來與參考信號比較的複數個信號其中 之一通過。此種時差檢測電路使用包含多相位輸入電路的 高解析度時差檢測器。此種輸入電路具有一參考信號輸入 端，以及一時差信號輸入端，且其被調適用以接收同相位 和/或非同相位時差信號。爲回應控制信號，此輸入電路係 操作用來通過或反向此時差信號。此種檢測器亦包含了時 間至電壓轉換電路，其具有分別的第一輸入端與第二輸入 端，用以接收已時差化信號以及參考信號；以及具有產生 相對時差信號之差動放大器。此相對時差信號表示在參考 信號和時差信號之間的相對時差。捕獲電路係耦合到時間 至電壓轉換電路之輸入端，用以檢測該時差信號。 經濟部智慧財產局員工消費合作社印製 .但在另一個方面，本發明包含一種方法，用於決定在 複數個測試器通道之間的相對時差，以補償信號傳播的延 遲。本方法包含下列之步驟：在複數個通道之間產生測試 信號；將通道耦合至高解析度時差檢測電路；提供一參考 信號至時差檢測電路·，以及選擇用以比較在時差檢測電路 上的參考信號之測試信號的其中一個。此種比較步驟包括 8 本^張尺度適用中國國家標準（CNS)A4規格（210 x 297公釐了m, please ^ Committee I PI Ϊaxe 'i η% η melon: parameterization. When the above-mentioned time difference detection system based on the flip-flop is intended to be used in related applications, they all have a limited linear range due to metastability or jitter. This is an internal feature when the flip-flop is making an effective upload or download signal. As a result, when operating at higher frequencies, the resolution of the detector becomes worse, making the time difference between the signal and the signal undetectable. Proposed by Otsuji, the time-to-voltage conversion technology suitable for implementation on integrated circuits is used in an effort to prevent metastable states from existing inside the time difference detector based on the flip-flop. This technology uses a standard converter to receive and normalize reference signals and test signals from one channel of a semiconductor tester. The output of the standard converter block is coupled to the input of the differential amplifier. This amplifier generates a pulse wave having an amplitude proportional to the correlation time difference between the reference signal and the test signal. When the flash control circuit generates a flash frequency synchronized with the rising edge of the input signal, this pulse is transmitted to the complementary D latch. The output levels of Q port and Q / port are fixed in the complementary level according to the polarity of the time difference. Although this circuit contributes to the successful transition of the same-phase time difference to different voltages, it is not ready for non-in-phase. With the expansion and implementation of differential tester channels in semiconductor testers, non-in-phase time difference detection becomes increasingly important. The above-mentioned conventional time difference detection structure and technology show the limitations of achieving timing calibration and verification accuracy. Equally important, however, is the duration of time that is not required during the timed calibration and / or verification process. Traditionally, once the tester has completed its calibration, a separate verification device has been introduced 'to verify it (please read the notes on the back before filling out this page) --- !! Order --------- The paper size of the paper is applicable to the Chinese National Standard (CNS) A4 (210 X 297 g) printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 514744 A7 B7 V. Description of the invention (where) Accuracy. Generally, in order to detect the channel-to-channel time difference, automatic flash control is similarly arranged in a separate step of the DUT, spreading over each channel in order to detect the channel-to-channel time difference. Unfortunately, with the introduction of modern testers everywhere from three hundred to six hundred channels, the acquisition time of data for automatic flash control in practice may take fourteen hours or more. This results in lost tester time for manufacturing purposes, and correspondingly lower overall productivity. What has been required until now to obtain a high-resolution time difference detection circuit and method for use in a semiconductor tester can accurately detect very small time differences, and provide an output signal that allows fast timing calibration verification. The high-resolution time difference detection circuit and method of the present invention satisfy these needs. Summary of the invention The high-resolution time difference detection circuit and method of the present invention provide an accurate detection of both in-phase and non-in-phase signal time differences without the redundant effect of metastable beats. In addition, the present invention enables high productivity in such a manufacturing environment through direct measurement on multiple parallel channels and equipment. To achieve the above-mentioned advantages, one aspect of the present invention is to form a high-resolution time difference detection circuit including a multi-phase input circuit. This input circuit has a reference signal input, a time difference signal input, and can be adapted to accept in-phase and / or non-in-phase time difference signals. In order to respond to the control signal, this input circuit acts to make the time difference signal pass or reverse it. This detector also contains a time-to-voltage conversion circuit, which has the function of receiving the time-lapsed signal and reference 7 This paper standard applies to China National Standard (CNS) A4 specification (21〇X 297 public love) " " " " -------------- Install --- (Please read the precautions on the back βι to write this page) Order · ·-丨 Line 514744 A7 B7 V. Description of the invention (<) -------------- install --- (please read the note on the back to write this page first), the individual first input and second input of the line and signal; A differential amplifier that generates a relative time difference signal. The relative time difference signal represents a relative time difference between the reference signal and the time difference signal. The capture circuit is coupled to a time-to-voltage conversion circuit to detect a relative time difference signal. In another aspect, the present invention includes a method for measuring a relative time difference between a plurality of propagation signals and a reference signal. Such a time difference detection circuit includes a selector circuit having a plurality of input terminals adapted to receive a propagated signal, and a one of a plurality of signals for selectively passing a comparison signal with a reference signal. This type of time difference detection circuit uses a high-resolution time difference detector including a multi-phase input circuit. This input circuit has a reference signal input terminal and a time difference signal input terminal, and is adapted to receive in-phase and / or non-in-phase time difference signals. In response to the control signal, this input circuit is operated to pass or reverse the time difference signal. Such a detector also includes a time-to-voltage conversion circuit, which has a first input terminal and a second input terminal, respectively, for receiving a time difference signal and a reference signal; and a differential amplifier for generating a relative time difference signal. This relative time difference signal represents the relative time difference between the reference signal and the time difference signal. The capture circuit is coupled to the input of the time-to-voltage conversion circuit to detect the time difference signal. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. However, in another aspect, the present invention includes a method for determining the relative time difference between a plurality of tester channels to compensate for the delay in signal propagation. The method includes the following steps: generating test signals between a plurality of channels; coupling the channels to a high-resolution time difference detection circuit; providing a reference signal to the time difference detection circuit; and selecting a reference signal for comparison on the time difference detection circuit One of the test signals. This comparison step includes 8 standard sheets that are in accordance with Chinese National Standard (CNS) A4 (210 x 297 mm
五、發明說明（石） (請先閱讀背面之注意事項再填寫本頁) 下列步驟=將參考信號緣與已通過之測試信號緣之間的相 對時差轉換成電壓，以及提供在輸出端之電壓，作爲測量 在測試信號與參考信號之間的相對時差之用。 本發明之其他特徵與優點將會經由以下結合伴隨圖式 閱讀之詳細描述而彰顯出來。 fa式簡單說明 經由參考下列較詳細之描述與伴隨圖式，將可更加明 瞭本發明，其中： 圖一爲使用本發明其中一個實施例之半導體測試器的 部分方塊圖； 圖二爲顯示於圖一之時差檢測電路的高位準方塊圖； 圖三爲圖二中時差檢測電路之選擇器電路之一實施例 的部分圖解， 圖四爲根據本發明之一實施例的高解析度時差檢測器 之圖解； 圖五爲圖四中高解析度時差檢測器之時序圖。 元件符號說明 10 半導體測試器 14 設備介面板 15 接腳電子通道卡 d 20 通道 22 插座 --- 9 ___ 本紙張尺度適周中國國家標準（CNS)A4規格（210 X 297公釐） '之 ^ n A7 B7 五、發明說明（ ο 2 3 3 3 3 6 3V. Description of the Invention (Stone) (Please read the notes on the back before filling this page) The following steps = Convert the relative time difference between the reference signal edge and the passed test signal edge into a voltage, and provide the voltage at the output , Used to measure the relative time difference between the test signal and the reference signal. Other features and advantages of the present invention will become apparent through the following detailed description in conjunction with the accompanying drawings. The fa formula is briefly explained by referring to the following more detailed description and accompanying drawings, in which the present invention will be more clearly understood, in which: FIG. 1 is a partial block diagram of a semiconductor tester using one embodiment of the present invention; FIG. 2 is shown in the figure A high-level block diagram of a time difference detection circuit; FIG. 3 is a partial diagram of an embodiment of a selector circuit of the time difference detection circuit in FIG. 2; FIG. 4 is a diagram of a high-resolution time difference detector according to an embodiment of the present invention; Diagram; Figure 5 is the timing diagram of the high-resolution time difference detector in Figure 4. Description of component symbols 10 Semiconductor tester 14 Device interface panel 15-pin electronic channel card d 20 channel 22 Socket --- 9 ___ This paper is suitable for Chinese National Standard (CNS) A4 specification (210 X 297 mm) 'of ^ n A7 B7 V. Description of the invention (ο 2 3 3 3 3 6 3
7023902460460240 3444455556667778 高解析度時差檢測電路系統 偏壓輸入端 偏壓輸入端 第一參考信號輸入端 第二參考信號輸入端 選擇器電路 類比多工器 類比多工器 位址解碼器 高解析度時差檢測器 第一信號路徑 第二信號路徑 多相位輸入電路系統 時間至電壓轉換電路 延遲元件 差動放大器 捕獲電路系統 閂鎖方塊 閃控電路 低通濾波器 本發明之詳細說明 現在參考圖一，其係顯示出一個半 親合至包含設備介面板（device interfac Β 器D 獄d， 沏ar 曲一a ο 其 (請先閱讀背面之注意事項再填寫本頁) 訂---------線丨 β ίο ‘所幸、纸張尺度適用中@ 0家標準（CNS)A4規格（210 x 297 ) I提 D之 44 ^2¾18 A7 B7 iu Β . 内—丨 容 VI r- X：八: 否 :沒 五、發明說明（$ ) 此測試器包含測試頭（其未被顯示出），其容納複數個接腳 電子通道卡18，用以沿著複數個通道20產生測試器波形。 這些通道將波形導向一或多個DUT的輸入接腳（其未被顯 示出），以及接收DUT的輸出波形。此DIB包含一或多個 插座22，用以將DUT的接腳電耦合至測試器通道，因此 提供方便的測試器至DUT信號之介面。 爲確保沿著通道傳播的定時信號以預先設定的精準度 到達DUT的接腳，編號爲30的複數個高解析度時差檢測 電路系統係被引用。此時差檢測電路精確的量測通道至通 道之間同相位及非同相位的時差，用作定時校準或驗證的 目的。 更特別的參考圖二，每一個時差檢測電路30係採取 特殊應用積體電路（application specific integrated circuit， ASIC )之形式。此種ASIC包含用以接收Vdd及Gnd信號 的偏壓輸入端32及34,以及用以接收參考時脈信號VREFl 和VREF2的第一參考信號輸入端與第二參考信號輸入端36 和37。選擇器電路40係設置在ASIC上，其輸入端耦合至 複數個測試器通道，而其輸出端接至高解析度時差檢測器 50，用以在lpko秒中依序測量信號對信號的時差。 更進一步參考圖2，選擇器電路40包含了一對N比1 類比多工器42和43，其具有耦合至N (最佳爲24)測試器 通道傳輸線輸出。位址解碼器49回應至多位元DC位址信 :號，供應個別控制信號至多工器。此種類比多工器允許單 一 ASIC處理數個測試器通道，（在此範例爲24個)以便在 ____u_ _ (請先閱讀背面之注意事項再填寫本頁) -· -n n n n 一一OJt n n n n n I— n I ϋ t— n 个本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 5M74491..2. 13 A7 B7 煩凊#員^示 年月 q 修丑氺有無變更實質内容是否准文 五、發明說明（ 校準及/或驗證過程中將測試器生產率最大化。 本發明的發明人已發現，在維持可接受之信號品質上， 將用於HRSD的可選擇性輸入端數目成功地最大化，類比 多工器之結構扮演著重要的角色。然而習知的，N個M0S 閘之並聯陣列可能被用來實現其多工功能，如此之組合通 常會約束並聯閘輸出端只能產生單一的輸出，因此造成N:1 的結構。不幸的是，爲了高精確度的應用，習知結構中的 全部閘輸出能力通常造成不需要之瞬變電流，其會影響輸 出信號的完整性。 特別伴隨圖3的參考，爲努力讓上述瞬變電流效應最 小化，類比多工器42和43中每一個包括24個MOS傳輸 閘輸入端VI至V24，其以如此的方式分布以使得耦合至輸 入一輸出端的瞬變電流電容性地最小化。輸入閘分成四 組並聯陣列A1〜A4，以及每個陣列具有單一輸出〇1〜〇4。 每個輸出係供應至串聯連結的輸出傳輸閘0G1〜0G4，爲了 將不需要之瞬變電流饋通信號導向接地，個別接地的饋通 傳輸閘FT1〜FT4將信號輸出路徑分流。輸出傳輸閘的輸出 端係被束縛住，並提供一高保真度之輸出信號至 HRSD50的輸入端。 回頭參考圖一 ’筒解析度時差檢測器(HRSD)50 —般使 用用以接收測試信號與參考信號的多相位輸入電路系統 56，以及用以產生在測試信號與參考信號之間，代表相對 時差的輸出信號。捕獲電路系統70係設置在時間至電壓轉 換電路的輸出端，將產生的輸出信號檢測致能。此輸入電 療所本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 〇之 (請先閱讀背面之注意事項再填寫本頁) I - -線 A7 B7 1fJl^fvvv;.K」i ：.：，： ui:m复λ| 、w容是否准予修V义。 五、發明說明qo) 路系統以及時間至電壓轉換電路系統，爲輸入信號分別定 義第一信號路徑和第二信號路徑52和54。爲了淸晰的目 的’以下將只詳細敘述第一路徑。 現在更特別的參考圖四，用於第一信號路徑52的此多 相位輸入電路系統56包含一位準電壓轉換器LVC1 (圖二）， 其用以接收輸入信號IN1(從一通道傳出的測試傳輸線輸出 信號），並且降低輸入信號電壓襬幅，到達更適合高速處理 之位準(例如450mv)。此位準轉換器包含差動對Q1和Q2， 其係被電流源II驅動^Q2的集電器輸出端接至射極隨耦 器Q3，其產生一已降低之信號位準，以及供應一輸入至 Gilbert 反向器 INV1。 Gilbert反向器INV 1包含差動控制輸入(FLIP，FLIP/)， 其傳送至個別的第一和第二差動對Q7，Q8以及Q9，Q10。 第三差動對Qll，Q12耦合至第一差動對和第二差動對的 射極，並且從位準電壓轉換器LVC1的輸出端接收已轉換 位準的測試信號，以及接收偏壓信號VBIAS。電流源13分 布在第三差動對的射極結點。個別的電阻R5和R6建立反 向器的DC偏壓狀況，其在技術中已廣爲人知。電晶體Q7 和Q9的集極係束縛在傳送至時間至電壓轉換電路系統60 的輸出結點。此電路的輸出係反應至差動控制信號FLIP， FLIP/，以便讓已轉換位準的測試輸入信號INI通過或反 向。如此可方便的供應同相位以及非同相位之測量。 更進一步參考圖四，時間至電壓轉換電路60，包含延 遲元件64，其耦合至Gilbert反向器INV1的輸出端，以及 二 ______Π............... 適 度 尺 張 纸 標 規格（210 x 297公釐） (請先閱讀背面之注意事項再填寫本頁) 訂---------線！ 514744 A7 _B7___ 五、發明說明（/ / ) 一差動放大器。 上述所提到的，第二信號路徑54包含位準轉換電路 LVC2，（電晶體Q4至Q6，以及電阻R3至R4)，以及Gilbert 反向器INV2(電晶體Q13至Q18,電流源14,以及電阻R7， R8)，而其結構組成近似於第一路徑52，而不需要更進一 步之說明。但是，第二信號路徑係被捕獲電路系統70所採 樣至62，以供應自我定時系統，其可去除額外定時電路的 需要。 差動放大器66包含另一個電晶體差動對Q19以及 Q20，其被電流源15所驅動，接收已轉換且經Gilbert反向 器反向之輸入，以產生具有正比於在輸入信號IN1和IN2 之間的相對時差。差動信號輸出端係供應至捕獲電路7〇的 輸入端。 更進一步參考圖二和圖四，捕獲電路7〇包含一閂鎖方 塊72，其由閃控電路74所產生的閃控脈衝定時之。此種 閂鎖方塊包含輸入差動對Q21，Q22，其輸入端耦合至差動 放大器66的輸出端。第二差動對Q24，Q25包含交叉耦合 至輸入差動對輸出端的個別輸入端，以便有效的建造D型 閂鎖。一對射極隨耦器Q27和Q28供給一差動緩衝輸出 OUT+以及OUT-。第三差動對Q23，Q26驅動(或提供電流 源)第一以及第二差動對，以及包含一電流源Ϊ6。第三差動 對對應於從閃控電路74出來的差動輸入信號而反應。 繼續參考圖四，閃控電路74包含一反向器模組’其傳 送至AND/NAND閘的第二輸入端。 14 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） --------------------訂·-------- (請先閱讀背面之注意事項再填寫本頁) 514744 A7 p—___ B7 _ 五、發明說明（/» 此種AND/NAND閘76的結構係爲習知的ECL設計， 並已廣爲熟悉此技術者所知悉。 回頭參考圖二，閂鎖方塊72的輸出端係最好經由輸出 緩衝器79傳送至充電幫浦，或是低通濾波器8〇。此充電 幫浦或是低通濾波器產生直流輸出，反應至閂鎖信號。以 此種方式，停止晶片直流電壓的產生並且使其被快速的導 向定時校準或驗證控制器（未被顯示出），而其需要時差資 料以用作分析。 根據先前所記述的，爲了擷取由DIB所供應的方便介 面之優點，並且除去對昂貴又慢速表現的機械閃控電路之 需求，本發明的時差檢測電路30,係以積體電路形式分布， 並且以類似於DUT之封裝爲較佳。但是，對於具有多於16 個I/O接腳的裝置，本發明可視額外輸入的需要而模組化。 舉例而言，既然較佳的HRSD電路30經由24個通道(對應 於24個DUT的I/O接腳)前進，對於具有64個I/O的DUT， 可將3個HRSD電路實現在單一的ASIC通道中。因此， 爲了設定用於定時校準或驗證的測試器，ASIC封裝僅不過 插入插座內，以提供完整的外在定時校準或驗證，用於裝 置的並聯陣列，其位置高於並包括插座軌道。 本發明之操作係最好參照圖一，圖二，圖四以及圖五 的時序圖。如前所述，爲安裝進入DUT負載板的插座，時 差檢測電路30以ASIC的形式實現。在平行記憶測試應用 中，負載版可能包含用以高出產率平行測試中32至128個 設備位置的任何一處，而此單一 _15 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公爱1 " "" --------------------訂---------線 (請先閱讀背面之注意事項再填寫本頁) 514744 Α7 Β7 五 Λ- -Λ ： \ J V ，，、，，· >1 -十· 、發明說明（I〉） ASIC實現方式可安裝32至128的HRSD ASIC，以執 行測試定時校準及/或定時驗證。 爲了淸晰的目的，下述運作的說明將集中在定時驗證· 應用中’隨著對所描述之方法的了解，其可相同的應用在 執行初始的校準上。定時驗證僅爲測試信號定時的一種獨 立結構’或是驗證’以確保先前執行的校準定時在要求的 容忍度內。 一旦HRSD的ASIC安裝在負載板14中，測試器產生 一預先決定的測試波形圖樣，模擬實際的測試器運作。此 包含了沿著測試通道20至每一個ASIC信號輸入端傳送測 試信號。 以經由16在通道1和通道2之間爲例，爲了檢測並測 量通道至通道時差，測試信號沿著通道1係當作信號參考 IN2 ’而其他的通道係依序的通過選擇器4〇至hrSD 50。 經由類比多工器42及43的序列被4位元直流定址信號所 規整’（以驗證控制器所控制之，其未顯示出）而其直流定 址信號具體指明多工器應讓哪一個通道的信號通過。 選擇號IN1，以及參考信號(從通道1而出)IN2， 係被位準電壓轉換電路系統LVC1和LVC2所調整爲接近 於450mV的信號。如此減少了邏輯襬幅的位準，將電路性 能變得更快速。 用於IN1以及IN2之個別已轉換過位準的信號，必須 經過Gilbert反向器INV1以及INV2處理，使得非同相位 時差能如同同相位時差一樣被偵測，並且當作差動放大器 16 (請先閱讀背面之注意事項再填寫本頁) · ' 線· 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 五、發明說明（（屮） 66的差動輸入信號。如同圖五的顯示，差動放大器產生一 輸出信號脈波DATA，其振幅正比於ΙΝ1與ΙΝ2之間的相 對時差。特別的重點是輸出的產生（至少在輸出信號上升時 間的持I買時間中），即使是在1微微秒上的相對時差位準。 如此提供了極強大的優點，即能夠成功的檢測並測量如此 微小的時間參數。 爲了維持已檢查過之放大器的輸出（表示相對的時 差）’（表示相對時差），閃控電路74產生一擊時脈信號（閃 控脈衝)CLK(圖五），其被參考信號輸入IN2之上升邊緣所 觸發。在62採樣此參考信號，以及將此信號與其反向信號 一起AND/NAND，造成自我定時之特徵（圖四）。此閃控時 脈CLK在延長的持續時間中使閂鎖電路72維持或「閂鎖」 此資料信號DATA，因此輕易地產生可偵測之輸出信號 OUT+以及 OUTj 輸出信號脈衝係更進一步經由充電幫浦或低通濾波器 80處理以提取直流信號成分，並且建立無困難之可處理關 閉晶片時差信號，以作爲定時校準控制器分析之用。以上 的全面化程序與所有的HRSD ASIC同時發生，並且在參考 通道信號與所有其他通道比較之後重複。然後新的通道取 代先前的參考通道，並且重複此程序。一旦校準過程係完 整的’此測試器將可與半導體設備的產品測試繼續進行。 本發明所提供的許多利益與優點將會助益熟悉此技藝 ； 者。特別的重點係檢測同相位及非同相位二者之時差的高 ：解析度時差檢測能力。如此提供了實質上改進了測量檢測 L---—- —_π___ T、紙張尺度適用中國國家標準（Cns)A4規格（210 X 297公爱） -T— n i _ (請先閱讀背面之注意事項再填寫本頁) 訂· •線 A7 B7 五、發明說明（丨5") 定時校準的精確度。對於現代使用大量差動通道結構的半 導體測試器而言，這是極端重要的。此外，經由實現單一 檢測器電路使得校準的時間明顯地減至最少，將在產品運 作上測試器的可利用性最大化，使得成本實質的減少，並 且相對的增加生產率。 當本發明以參考較佳實施例而詳細的顯示並說明之 後，習知技藝者將會了解，其中的形式與細節上的各種變 化不會背離本發明之精神和範圍。 (請先閱讀背面之注意事項再填寫本頁) 18 訂： --線· 本纸張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）7023902460460240 3444455556667778 high-resolution time difference detection circuit system bias input terminal bias input terminal first reference signal input second reference signal input selector circuit analog multiplexer analog multiplexer address decoder high resolution time difference detector First signal path Second signal path Multi-phase input circuit system time-to-voltage conversion circuit delay element differential amplifier capture circuit system latch block flash control circuit low-pass filter A detailed description of the present invention is now referred to FIG. 1, which shows A semi-affinity to the device interface panel (device interfac Β 器 D prison d, brew ar song a a ο its (Please read the precautions on the back before filling this page) Order --------- line 丨β ίο 'Fortunately, paper standards are applicable @ 0 house standards (CNS) A4 specifications (210 x 297) I mention D of 44 ^ 2¾18 A7 B7 iu Β. Contents-Content VI r- X: eight: no: no 5. Description of the invention ($) This tester includes a test head (which is not shown), which contains a plurality of pin electronic channel cards 18 for generating tester waveforms along the plurality of channels 20. This The channel directs the waveform to one or more DUT's input pins (which are not shown) and receives the DUT's output waveform. This DIB contains one or more sockets 22 for electrically coupling the DUT's pins to the tester Channel, so it provides a convenient interface from the tester to the DUT signal. In order to ensure that the timing signals propagating along the channel reach the pins of the DUT with a preset accuracy, a number of 30 high-resolution time difference detection circuit systems are used. Quote. At this time, the time difference detection circuit accurately measures the in-phase and non-in-phase time difference between the channels for the purpose of timing calibration or verification. More specifically, referring to Figure 2, each time difference detection circuit 30 adopts a special application. In the form of an application specific integrated circuit (ASIC), this ASIC includes bias input terminals 32 and 34 for receiving Vdd and Gnd signals, and a first reference signal for receiving reference clock signals VREF1 and VREF2. The input terminal and the second reference signal input terminals 36 and 37. The selector circuit 40 is provided on the ASIC, and its input terminal is coupled to a plurality of tester channels, and its output Terminated to a high-resolution time difference detector 50 to sequentially measure the signal-to-signal time difference in lpko seconds. Further referring to FIG. 2, the selector circuit 40 includes a pair of N to 1 analog multiplexers 42 and 43. It has a transmission line output coupled to the N (optimally 24) tester channel. The address decoder 49 responds to a multi-bit DC address signal: to supply individual control signals to the multiplexer. This type allows a single ASIC than the multiplexer Handle several tester channels (in this example, 24) so that ____u_ _ (please read the precautions on the back before filling this page)-· -nnnn one by one OJt nnnnn I— n I ϋ t— n This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 5M74491..2. 13 A7 B7 凊 # 员 ^ 示 年月 q Is there any change in substance? Whether it is allowed to be written (Maximize tester productivity during calibration and / or verification. The inventors of the present invention have found that the analog multiplexer structure plays an important role in successfully maximizing the number of selectable inputs for HRSD while maintaining acceptable signal quality. However, it is customary that a parallel array of N M0S gates may be used to achieve its multiplexing function. Such a combination will usually restrict the output of the parallel gates to produce only a single output, thus resulting in an N: 1 structure. Unfortunately, for high accuracy applications, the full gate output capability of conventional structures often results in unwanted transient currents, which can affect the integrity of the output signal. With particular reference to FIG. 3, in an effort to minimize the above-mentioned transient current effects, each of the analog multiplexers 42 and 43 includes 24 MOS transmission gate inputs VI to V24, which are distributed in such a way as to couple to The input-output transient current is minimized capacitively. The input gate is divided into four groups of parallel arrays A1 ~ A4, and each array has a single output 〇1 ～ 〇4. Each output is supplied to the output transmission gates 0G1 to 0G4 connected in series. In order to guide the unwanted transient current feedthrough signals to ground, the individually grounded feedthrough transmission gates FT1 to FT4 shunt the signal output path. The output terminal of the output transmission gate is tied and provides a high-fidelity output signal to the input of the HRSD50. Referring back to FIG. 1, the tube resolution time difference detector (HRSD) 50-generally uses a multi-phase input circuit system 56 for receiving a test signal and a reference signal, and is used to generate a relative time difference between the test signal and the reference signal. Output signal. The capture circuit system 70 is provided at the output end of the time-to-voltage conversion circuit, and detects and enables the output signal generated. The paper size of this input electrotherapy room applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 〇 (Please read the precautions on the back before filling this page) I--line A7 B7 1fJl ^ fvvv; .K "I:.: ,,: Whether ui: m complex λ |, w is allowed to repair V. V. Description of the invention qo) circuit system and time-to-voltage conversion circuit system, define a first signal path and a second signal path 52 and 54 respectively for an input signal. For the sake of clarity, only the first path will be described in detail below. Referring now more specifically to FIG. 4, the multi-phase input circuit system 56 for the first signal path 52 includes a one-bit quasi-voltage converter LVC1 (FIG. 2), which is used to receive an input signal IN1 (which is transmitted from a channel Test the transmission line output signal), and reduce the voltage swing of the input signal to reach a level more suitable for high-speed processing (such as 450mv). This level converter contains differential pairs Q1 and Q2, which are driven by the current source II ^ 2, the current collector output is connected to the emitter follower Q3, which generates a reduced signal level and supplies an input To Gilbert inverter INV1. The Gilbert inverter INV 1 contains differential control inputs (FLIP, FLIP /), which are transmitted to the individual first and second differential pairs Q7, Q8 and Q9, Q10. The third differential pair Q11, Q12 is coupled to the emitters of the first differential pair and the second differential pair, and receives the converted level test signal from the output terminal of the level voltage converter LVC1, and receives the bias signal VBIAS. The current source 13 is distributed at the emitter node of the third differential pair. Individual resistors R5 and R6 establish the DC bias condition of the inverter, which is widely known in the art. The collectors of the transistors Q7 and Q9 are tied to the output node of the time-to-time voltage conversion circuit system 60. The output of this circuit reacts to the differential control signals FLIP, FLIP /, so as to pass or reverse the test input signal INI of the converted level. This makes it easy to supply in-phase and non-phase measurements. Further referring to FIG. 4, the time-to-voltage conversion circuit 60 includes a delay element 64, which is coupled to the output terminal of the Gilbert inverter INV1, and two ______ Π ......... moderate Rule paper label specifications (210 x 297 mm) (Please read the precautions on the back before filling this page) Order --------- Line! 514744 A7 _B7___ 5. Description of the Invention (//) A differential amplifier. As mentioned above, the second signal path 54 includes a level conversion circuit LVC2 (transistors Q4 to Q6, and resistors R3 to R4), and a Gilbert inverter INV2 (transistors Q13 to Q18, current source 14, and Resistors R7, R8), and their structural composition is similar to the first path 52, without further explanation. However, the second signal path is sampled to 62 by the capture circuit system 70 to supply a self-timing system, which eliminates the need for additional timing circuits. The differential amplifier 66 includes another transistor differential pair Q19 and Q20, which are driven by a current source 15 and receive a converted input that is inverted by a Gilbert inverter to produce a signal having a ratio proportional to the input signals IN1 and IN2. Relative time difference. The differential signal output terminal is supplied to the input terminal of the capture circuit 70. With further reference to Figures 2 and 4, the capture circuit 70 includes a latch block 72 which is timed by the flash control pulses generated by the flash control circuit 74. This latch block includes input differential pairs Q21, Q22, whose inputs are coupled to the output of a differential amplifier 66. The second differential pair Q24, Q25 contains individual inputs that are cross-coupled to the output of the input differential pair to effectively construct a D-type latch. A pair of emitter followers Q27 and Q28 provide a differential buffered output OUT + and OUT-. The third differential pair Q23, Q26 drives (or provides a current source) the first and second differential pairs, and includes a current source Ϊ6. The third differential reacts to a differential input signal from the flash circuit 74. With continued reference to Figure 4, the flash control circuit 74 includes an inverter module 'which is transmitted to the second input terminal of the AND / NAND gate. 14 This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) -------------------- Order · -------- (Please read the notes on the back before filling out this page) 514744 A7 p —___ B7 _ V. Description of the invention (/ »The structure of this AND / NAND gate 76 is a conventional ECL design and has been widely familiar with this The skilled person knows. Referring back to FIG. 2, the output end of the latch block 72 is preferably transmitted to the charging pump or the low-pass filter 80 through the output buffer 79. This charging pump is a low-pass filter. Generates a DC output in response to a latch-up signal. In this way, the generation of the chip's DC voltage is stopped and it is quickly guided to a timing calibration or verification controller (not shown), which requires time difference data for analysis According to the previous description, in order to capture the advantages of the convenient interface provided by the DIB and eliminate the need for expensive and slow-moving mechanical flash control circuits, the time difference detection circuit 30 of the present invention is in the form of a integrated circuit Distribution, and a DUT-like package is preferred. However, for more than 16 I / O pin device, the present invention can be modularized according to the needs of additional inputs. For example, since the better HRSD circuit 30 advances through 24 channels (corresponding to the I / O pins of the 24 DUTs), For a DUT with 64 I / Os, 3 HRSD circuits can be implemented in a single ASIC channel. Therefore, to set up a tester for timing calibration or verification, the ASIC package is simply plugged into a socket to provide a complete External timing calibration or verification, used for the parallel array of the device, its position is higher than and including the socket track. The operation system of the present invention is best referred to the timing diagrams of Figures 1, 2, 4, and 5. As described above To install the socket into the DUT load board, the time difference detection circuit 30 is implemented in the form of ASIC. In the parallel memory test application, the load version may contain any one of 32 to 128 device locations in parallel tests for higher productivity. And this single _15 This paper size is applicable to China National Standard (CNS) A4 specifications (210 X 297 Public Love 1 " " " -------------------- Order --------- Line (Please read the precautions on the back before filling this page) 514744 Α 7 Β7 Five Λ- -Λ: \ JV ,,,,,, > 1-ten, invention description (I>) ASIC implementation can be installed with 32 to 128 HRSD ASIC to perform test timing calibration and / or timing Verification. For the sake of clarity, the description of the operation below will focus on the timing verification application. With the understanding of the method described, it can be used the same for performing the initial calibration. The timing verification is only a test signal A separate structure for timing, or verification, to ensure that previously performed calibration timings are within required tolerances. Once the HRSD ASIC is installed in the load board 14, the tester generates a predetermined test waveform pattern that simulates the actual tester operation. This involves transmitting test signals along the test channel 20 to each ASIC signal input. Taking channel 16 between channel 1 and channel 2 as an example, in order to detect and measure the channel-to-channel time difference, the test signal is taken along channel 1 as the signal reference IN2 ', and the other channels are sequentially passed through the selector 4 to hrSD 50. The sequences via analog multiplexers 42 and 43 are normalized by 4-bit DC addressing signals (to verify that the controller controls them, which is not shown), and their DC addressing signals specify which channel the multiplexer should allow. The signal passed. The selection number IN1 and the reference signal (from channel 1) IN2 are signals adjusted by the level voltage conversion circuit systems LVC1 and LVC2 to approximately 450mV. This reduces the level of logic swing and makes circuit performance faster. The individually converted signals for IN1 and IN2 must be processed by Gilbert inverters INV1 and INV2, so that non-in-phase time difference can be detected as the same-phase time difference and used as a differential amplifier 16 (please (Please read the notes on the back before filling in this page) · 'Thread · This paper size applies the Chinese National Standard (CNS) A4 (210 X 297 mm) 5. Description of the invention ((屮) 66 differential input signal. As Figure 5 shows that the differential amplifier generates an output signal pulse DATA, whose amplitude is proportional to the relative time difference between IN1 and IN2. The special emphasis is on the generation of the output (at least during the holding time of the output signal rise time) , Even at a relative time difference level of 1 picosecond. This provides a very powerful advantage that it can successfully detect and measure such small time parameters. In order to maintain the output of the checked amplifier (representing the relative time difference) ) '(Indicating relative time difference), the flash control circuit 74 generates a one-shot clock signal (flash control pulse) CLK (Figure 5), which is caused by the rising edge of the reference signal input IN2 Sampling this reference signal at 62 and AND / NAND this signal with its reverse signal, resulting in self-timing characteristics (Figure 4). This flash control clock CLK maintains the latch circuit 72 for an extended duration Or "latch" this data signal DATA, so it can easily generate detectable output signals OUT + and OUTj. The output signal pulse is further processed by the charging pump or low-pass filter 80 to extract the DC signal component, and it is established without difficulty. It can process the off-chip time difference signal for timing calibration controller analysis. The above comprehensive process occurs simultaneously with all HRSD ASICs and is repeated after the reference channel signal is compared with all other channels. Then the new channel replaces the previous one And repeat this procedure. Once the calibration process is complete, this tester will continue to perform product testing with semiconductor devices. Many of the benefits and advantages provided by the present invention will help familiarize yourself with this technology; especially. The focus is on detecting the high time difference between in-phase and non-in-phase: resolution time difference detection capability .This provides substantially improved measurement and detection L ------ —_π ___ T, paper size applies Chinese National Standard (Cns) A4 specifications (210 X 297 public love) -T- ni _ (Please read the note on the back first Please fill in this page again) Order · • Line A7 B7 V. Description of the invention (丨 5 &) The accuracy of timing calibration. This is extremely important for modern semiconductor testers using a large number of differential channel structures. In addition, By implementing a single detector circuit, the time for calibration is significantly minimized, the availability of the tester is maximized in the operation of the product, the cost is substantially reduced, and the productivity is relatively increased. When the present invention is implemented by reference, After detailed examples are shown and explained, those skilled in the art will understand that various changes in form and details will not depart from the spirit and scope of the present invention. (Please read the precautions on the back before filling out this page) 18 Orders: --Line · This paper size applies to China National Standard (CNS) A4 (210 X 297 mm)