JP2003028928A - Semiconductor device and testing method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problem of a method for measuring the function and timing of a high-speed I/O interface in a semiconductor device requiring, which does not use a high-performance ATE or LSI tester. SOLUTION: This method includes a test data generator which is provided in an output part and generates a test data, a delay circuit which adjust a time difference to set the test data transmitted in the inside of a chip as an expected value, a comparator which is provided in an input part and compares and verifies the test data transmitted in the outside of the chip, and an external wiring, in which an output pin connected with the test data generator is connected with an input pin connected with the comparator.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a test method thereof, and more particularly to a test circuit for an input / output (I / O) interface of the semiconductor device.

[0002]

2. Description of the Related Art In a semiconductor device (LSI) test, a semiconductor tester (hereinafter referred to as an LSI tester) is used to perform operation verification. In order to perform the test at the same speed as the system operation, an LSI tester having the same operation speed as the I / O interface of the LSI is required.

Here, a conventional LSI test will be briefly described. FIG. 6 is a block diagram showing a conventional semiconductor device test method. In the figure, 1001 is an LS.
I tester, 1002 is DUT board, 1003 is LS
I, 1004 are pin cards, and 1005 are circuit elements such as comparators and drivers. This LSI tester 10
01 creates an environment close to the actual operating environment of the LSI 1003 by computer control,
LS has a timing generator, a test pattern generator, a formatter, a power supply, etc.
This is to apply an input signal to I1003 and compare the output response with an expected value prepared in advance. Also, the pin card 100
4 is a final output stage that outputs a predetermined waveform, and LS
It has a circuit element such as a comparator for comparing the data output from I1003 with an expected value.

Regarding the operation, in the case of the function test of the LSI 1003, a test vector generated by the LSI tester 1001 is applied to the LSI 1003 and its output response is compared with an expected value to verify the operation of the core logic including the input / output section. .

[0005]

Since the conventional semiconductor device test system has the circuit configuration as described above, a high-speed LSI tester is expensive, especially for a multi-pin LSI having Gbps class I / O. Therefore, there is a problem that it is not economical to apply it to mass production.

Further, in the conventional semiconductor device and the test method thereof, the speed of the LSI operation up to 1 Gbps class is increased, and the I / O timing (Setup, Hol) of several tens to several hundreds ps.
d, CLK_to_Q) has reached the test operation limit and timing limit, and there is a problem that it is becoming difficult to realize a highly reliable test.

As a countermeasure, there is a method of connecting the output terminal and the input terminal of the LSI externally and performing an operation test of the I / O interface at an actual operation speed (a loop (Loop) or a chip-to-chip connection test method). For example, Japanese Patent Application No. 2000-95552 discloses a semiconductor device including a test pattern generator and a data compressor.

On the other hand, Japanese Patent Laid-Open No. 3-117214 discloses LS
I / O pins can be connected in a loop or multiple LS
The I / O pin is connected in a loop to perform a communication test of the actual I / O interface, but the output unit uses a test data generator for testing at the actual operating speed and external data at the input unit. It does not include a successive comparator with the expected value data from the test data generator, a delay circuit for adjusting the comparison timing, and a strobe function.

The present invention has been made to solve the above problems, and an object of the present invention is to obtain a semiconductor device and a test method thereof that enable an actual operation test of a high-speed I / O interface of the semiconductor device. .

[0010]

A semiconductor device according to the present invention comprises a test data generating means for generating test data and a data adjustment for adjusting a time difference between the test data passing through the inside of the chip to be expected value data. Means and
The comparison unit is provided in the input unit for comparing and verifying the test data propagated outside the chip and the expected value data.

In the semiconductor device according to the present invention, the test data generating means is provided in the output section, the test data is outputted from this, and the test data is transmitted to the comparing means as expected value data via the data adjusting means. It is a thing.

In the semiconductor device according to the present invention, the test data generating means includes a first test data generating means provided in the output section for generating test data propagating outside the chip, and a data adjusting means provided in the input section. And second test data generating means for generating test data which is expected value data via the test data.

In the semiconductor device according to the present invention, the test data generating means has an LFSR which operates at an actual operating speed.

In the semiconductor device according to the present invention, the comparison means is composed of a comparator for comparing and verifying the test data input from the outside and the expected value data passing through the inside of the chip at the actual operating speed. .

In the semiconductor device according to the present invention, the data adjusting means is constituted by a delay circuit which delays the test data passing through the inside of the chip to obtain expected value data.

A semiconductor device test method according to the present invention comprises a test data generating means for generating test data,
A data adjusting means for adjusting the time difference so that the test data passing through the inside of the chip becomes the expected value data, and a comparing means for comparing and verifying the test data propagated outside the chip and provided in the input section with the expected value data. And a semiconductor device including: an external wiring for connecting an output of the test data generating means and an input of the comparing means.

In the semiconductor device test method according to the present invention, the test data generating means is provided in the output section, the test data is output from the output portion, and the test data is passed through the data adjusting means to be the expected value data and the comparing means. Is to be sent to.

In the test method of the semiconductor device according to the present invention, the test data generating means includes the first test data generating means provided in the output portion for generating the test data propagating outside the chip, and the data provided in the input portion. Second generation of test data that is expected value data via adjustment means
And the test data generating means.

The semiconductor device testing method according to the present invention is such that the semiconductor device is composed of a plurality of semiconductor devices, and the output pins and input pins of the respective semiconductor devices are connected by external wiring.

In the semiconductor device testing method according to the present invention, the test data generating means is operated at an actual operating speed.
It has an FSR.

In the semiconductor device test method according to the present invention, the comparison means is composed of a comparator for comparing and verifying the test data input from the outside and the expected value data passing through the inside of the chip at an actual operating speed. It is a thing.

In the semiconductor device testing method according to the present invention, the data adjusting means is constituted by a delay circuit which delays the test data passing through the inside of the chip to obtain expected value data.

In the semiconductor device according to the present invention, the circuit under test for inputting external data from the data input pin, the strobe signal set to a predetermined standard by the strobe pin, and the output data from the circuit under test are applied. The data latch means for capturing the clock input from the external clock pin and the register means for extracting the data latched by the data latch means are provided, and the wiring from the data input pin to the data latch means and the circuit under test are provided. The wiring to the data latch means and the wiring from the external clock pin to the circuit under test have the same length.

In the semiconductor device according to the present invention, the data latch means includes a plurality of strobe flip-flops, and the wirings from the strobe pin to the plurality of strobe flip-flops are of equal length.

In the semiconductor device according to the present invention, the circuit under test comprises an internal flip-flop, and wiring from the output to the input of the corresponding strobe flip-flop,
The wiring from the data input of the internal flip-flop to the data input of the corresponding strobe flip-flop,
Each of them has the same length as the wiring from the external clock pin to the internal flip-flop.

In the semiconductor device according to the present invention, a scan shift register is connected to the output of the strobe flip-flop, and the output is extracted outside the chip by the JTAG pin.

[0027]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described below. Embodiment 1. 1 is a block diagram showing a test method for a semiconductor device according to a first embodiment of the present invention. In FIG. 1, 5 is an LSI (semiconductor device), 8 is expected value data as comparison data, and 9 is pseudo random data. Test data, 10 is a test data generator (test data generating means, output unit), 11 is a clock, 12 is an output buffer (output unit), 13 is external wiring, 14 is an input buffer (input unit), and 15 is a comparator. (Comparing means), 16 a delay circuit (data adjusting means), 17 a test access port (TAP), 18 PLL, 19 JTAG pin, 20
Is the TCK pin for the test clock input (TCK), 21
Is TMS pin for test mode select input (TMS), 2
2 is a TDI pin for serial data input (TDI), 5
1 is a TDO pin for serial data output (TDO), 7
Reference numeral 0 is an external clock, and 40 and 45 are a SET pin and a RESET pin, respectively.

The circuit structure of the test data generator 10 is an LFS composed of a plurality of flip-flops (F / F).
R, and the external clock 70 is PL to this LFSR
By applying the clock 11 obtained via L18, pseudo random data expected as test data can be generated. If the clock 11 can be given at the same speed as the system operation, the pseudo random data can also be given as the test data 9 at the actual operation speed. The test data 9 is transmitted to the output buffer 12, and is output from the output buffer 12 at the actual operating speed. The test data output from the output buffer 12 is transmitted to the input buffer 14 connected via the external wiring 13.

Then, the test data that has reached the input buffer 14 is taken in by the F / F contained therein, and is output from the LFSR of the test data generator 10 in the comparator 15 provided at the subsequent stage of this F / F. The test data 9 and the same expected value data 8 are compared and verified in the LSI 5. At this time, there is a time difference between the test data 9 transmitted from the outside and the comparison data, that is, the expected value data 8 passing through the inside of the LSI 5, so the delay circuit 16 adjusts this and delays the timing of the expected value data 8. To do.

The activation of the LFSR incorporated in the test data generator 10, the activation of the comparator 15, the delay amount setting of the delay circuit 16, the SET pin 40 and R of the test data 9 are set.
The set and reset signals are applied to the ESET pin 45, and the clock 11 of the PLL 18 is applied by JTAG control from the TCK pin 20, the TMS pin 21, and the TDI pin 22 of the signal pins forming the JTAG pin 19. It should be noted that JTAG was introduced in IEEE Std 11 in 1990.
It is standardized as 49.1.

Next, FIG. 2 is a block diagram of the test system of the semiconductor device of FIG.
Is shown. In the figure, reference numeral 30 is a flip-flop (F / F), and 60 is a user logic. The same reference numerals as those used above denote the same or corresponding portions, and the description thereof will be omitted to avoid duplication and the same applies hereinafter.

The operation of FIG. 2 will be described. First, the expected value data 8 of pseudo random data generated by the LFSR of the test data generator 10 is output from the output buffer 12, propagates through the external wiring 13, and is transmitted to the input buffer 14. The test data 9 transmitted from outside the chip is F /
It is once captured in F30 and compared with expected value data 8 which is exactly the same data as the pseudo random data generated from the LFSR.

Next, FIG. 3 is a circuit diagram showing the configuration of the comparator 15. In the figure, I1 and I2 are inverters, and 40
Is a SET pin, 42 is a DIN pin, 43 is an EXP pin,
44 is a CLK pin, 45 is a RESET pin, 41 is a flip-flop (F / F), 46 is an OR gate, and 47 is N.
AND gate, 49 is a NOR gate, 48, 50
Respectively correspond to the output QC and the output Q of the F / F 41. Thus, the comparator 15 has one F / F, two inverters, two OR gates, one NAND gate,
It consists of one NOR gate.

The meaning of each terminal will be described below. First, the signal from the SET pin 40 is set to “1” in the F / F 41, the input data from the input buffer 14 is input into the DIN pin 42, and the EXP pin 43 is generated from the LFSR of the test data generator 10. The expected value data 8 is input. Further, the CLK pin 44 has a P
The clock 11 sent from the LL 18 is applied, and R
The signal of the ESET pin 45 sets "0" to the F / F41.

Next, the operation will be described. First, SET
"1" is set in the F / F 41 by the signal of the pin 40. The test data 9 received by the input buffer 14 and propagated outside the chip is applied to the DIN pin 42, and at the same time, the expected value data 8 is applied to the EXP pin 43. If the test data 9 and the expected value data 8 are the same data, the outputs from the two OR gates 46 are both "1". Then, the output of the NAND gate 47 becomes "0". Here, since the output QC48 of the F / F 41 is "0", NO
The output of the R gate 49 becomes "1". Therefore, if the data is the same, Q50 of the F / F 41 remains "1".

If the DIN pin 42 and the EXP pin 43 have different data, one of the outputs of the two OR gates 46 becomes "0", and therefore the output of the NAND gate 47 becomes "1". Then, output QC4
NOR by 8 "0" and NAND gate 47 "1"
The output of the gate 49 becomes "0". As a result, F / F4
The data "1" of 1 is rewritten to "0", and then the output QC48 becomes an output of "1" and is input to the NOR gate 49.

Since "1" is input to the NOR gate 49, the output of the NOR gate 49 is always "0".
Therefore, it is never rewritten to "1". Therefore,
Once a mismatch occurs between the test data 9 from the outside of the chip and the expected value data 8 inside, the output Q50 value of the F / F 41 is rewritten from "1" to "0". Function tests can be performed at the actual operating speed of the interface.

After the output of a series of test data 9 from the LFSR is completed, the contents of the F / F 41 of the comparator 15 are scan-shifted out from the TDO pin 51 constituting the JTAG pin 19, and if the data is "1". , Test result is PA
Judged as SS. If "0" exists, it is a defective product.

Although not shown, for example, the output unit, the input unit, the expected value storage unit, and the comparison unit are, for example,
Twelve F / Fs are prepared to support both edges of the clock 11, and one F / F is provided for each rising edge and falling edge of each data.
A 6-bit test circuit configuration when two F / Fs are prepared for 1 bit will be considered below based on the configuration of FIG.

First, the expected value data 8 is latched in the expected value register of the expected value storage section via the delay circuit 16, and the test data 9 propagated through the external wiring 13 and the expected value data 8 are compared by the comparator 15. It Because of the 6-bit LFSR, the data sequence of the pseudo random data makes one cycle with a clock of 2 ⁶ -1 times (63 times). If the number of times can be set externally, it is not necessary to apply a long clock cycle. For example, the stop cycle can be arbitrarily set by setting the number of stops in the counter and controlling the comparator 15.

When this test circuit is used, an external LSI
What is a tester? JTAG pin 19 4 pin (TCK pin 2
0, TMS pin 21, TDI pin 22, TDO pin 5
It is sufficient to connect 1) to the external clock 70 applied to the PLL 18, and signals such as the SET pin 40 and the RESET pin 45, and it is not necessary to use a signal as fast as the I / O interface. Therefore, even in the low-speed tester and the small pin test, the high-speed / multi-pin LSI test can be performed at a low test cost without lowering the test quality.

On the other hand, in the above configuration, since the pseudo random data and the expected value are generated from one LFSR of the test data generator 10, it is necessary to connect the output section and the input section, and the random logic section is required. The wiring will run vertically and horizontally. The circuit configuration shown in FIG. 4 can be considered as a modification of FIG. 1 as one means for reducing the number of wirings vertically and horizontally in such a logic section. In the figure, 10a,
Reference numeral 10b denotes first and second test data generators (first and second data generating means), each of which is an LFSR.
Reference numeral 61 is a delay circuit (data adjusting means). The other components are the same as those in FIG. 1, and the only difference is that the first test data generator 10b installed in the input section is responsible for generating the test data used as the expected value data 8. . As described above, in the test method of FIG. 4, the number of circuits forming the first test data generator 10b increases,
There is an advantage in that the wiring that extends vertically and horizontally in the logic part inside the LSI 5 can be omitted.

As described above, according to the first embodiment, in the LSI 5, the test data generator 10 having the LFSR, the delay circuits 16 and 161 for generating the comparison data (expected value data), and the successive approximation function. Is provided so that the output pin of the output buffer 12 and the input pin of the input buffer 14 can be connected by external wiring, and the internal clock input to the test data generator 10 and the comparator 15 is the same as the system operation. Give things of speed,
When these circuit elements are actually operated, the entire test system operates at the actual operation speed, the actual operation test of the I / O interface of the LSI 5 can be realized, and the high-performance LSI test is not required, so the test cost can be reduced. The effect of reduction can be obtained.

Further, by providing the LFSRs 10a and 10b in the output section and the input section respectively, it is possible to obtain an effect that the wiring configuration for arranging the logic section included in the LSI 5 vertically and horizontally can be omitted.

In this embodiment, the case in which the number of test data generators is one or two has been described, but the number of test data generators may be three or more, and the comparison timing is adjusted as the data adjusting means. Although the delay circuits 16 and 161 are exemplified, they can be applied to data adjustment other than delay depending on the configuration.

Embodiment 2. In the first embodiment described above,
This is a description of the function operation test circuit at the actual operation speed of the I / O interface.
Another important element in the O interface is setup and hold timing verification.

FIG. 5 is a block diagram showing a semiconductor device according to a second embodiment of the present invention, in which 18 is P.
LL, 80 are internal flip-flops, 81a to 81d are strobe flip-flops (data latch means),
82 is a strobe pin and 83 is a TDO
Pins, 85 is a differential amplifier, 86 is a scan flip-flop, 87 is a delay circuit (data adjusting means), 60 is a user logic, and N1 to N4 are nodes. Reference numeral 86 is a scan flip-flop (SFF) that constitutes a scan shift register, and 83 is a JTAG pin that outputs the contents of the selected register to the outside, for example, at the falling edge of TCK.

In the circuit configuration of FIG. 5, in order to verify whether the setup and hold timings of the internal flip-flop 80 of the LSI 5 are in accordance with the standard, the strobe flip-flops 81a to 81a ... 81d are connected to each other, and the length L1 of the wiring from the node N1 located after the delay circuit 87 to the input T of the internal flip-flop 80,
The wiring length L2 from the output Q of the internal flip-flop 80 to the input D of the strobe flip-flop 81a via the node N4 and the strobe flip-flop 81b from the input D of the internal flip-flop 80 to the node N3. Wiring length L3 up to input D of
The length L4 of the wiring from the A pin via the node N2 to the input D of the strobe flip-flop 81c and the length L5 of the wiring from the node N1 to the input D of the strobe flip-flop 81d are equal. It is characterized in that the lengths of wirings from the strobe pin 82 to the respective inputs D of the strobe flip-flops 81a to 81d are all equal.

The strobe is generally a value that defines the time position when the LSI output signals are compared and the quality is judged. In the actual test, the signal is output from the timing generator, and the above specified value is used. The result is extracted by judging the level of the output signal of the LSI.

Next, the operation will be described. A strobe signal is applied from the outside via the strobe pin 82, and D
It captures the data and clock input from the ATA pin and the external clock pin, respectively. When capturing, the strobe signal is set to the standard, and if the data can be latched, it is determined as a good product, and if not, it is determined as a defective product. Judgment is made by using the latched data for T judgment.
Scan out from the DO pin 83 and make a determination by an external inspection machine.

At this time, the test data applied to the DATA pin can be generated by the test circuit of the first embodiment, or a high speed tester may be used. Further, if the I / O interface is capable of operating at a low speed, only a timing correlation can be seen, so a low speed tester may be used.

As described above, according to the second embodiment, the wiring lengths L1 to L5 are equal, and the strobe pin 82 to the strobe flip-flops 81a to 81 are used.
Since the distances to the respective inputs of d are made equal and the strobe function is common, there is no skew and the timing verification of the high speed I / O interface becomes possible,
As a result, the effect that a tester having high-performance timing accuracy is unnecessary is obtained.

[0053]

As described above, according to the present invention, the test data generating means for generating the test data and the data adjusting means for adjusting the time difference so that the test data passing through the inside of the chip are the expected value data. Since the input unit and the output unit are connected by the external wiring, the test data is generated by connecting the input unit and the output unit by external wiring, which is configured to include the comparing unit for comparing and verifying the test data propagated outside the chip and the expected value data. An internal clock having the same speed as the system operation is applied to the comparison means and the comparison means, and the comparison means compares the test data propagated through the external wiring with the internal expected value data adjusted for the time difference. By verifying, the actual operation test of the I / O interface of the semiconductor device can be realized, so an expensive LSI tester becomes unnecessary and the test cost can be reduced. There is that effect.

According to the present invention, the test data generating means is provided in the output section, and the test data is outputted from this, and this test data is made to be the expected value data via the data adjusting means and transmitted to the comparing means. With this configuration, similarly, the input section and the output section are connected by the external wiring, and the internal clock having the same speed as the system operation is applied to the test data generating means and the comparing means, whereby the I / O interface of the semiconductor device is obtained. Since an actual operation test can be realized, an expensive LSI tester is not required, and the test cost can be reduced.

According to the present invention, the test data generating means passes through the first test data generating means provided in the output section for generating the test data propagating outside the chip and the data adjusting means provided in the input section. The second test data generating means for generating the test data serving as the expected value data is used, and therefore, the semiconductor is connected by the same external wiring connection as described above and the application of the internal clock having the same speed as the system operation. Not only can the actual operation test of the I / O interface of the device be realized, but also the wiring that runs vertically and horizontally in the internal circuit such as the logic portion of the semiconductor device can be reduced.

According to the present invention, the test data generating means comprises the LFSR which operates at the actual operating speed, so that the test data can be obtained as pseudo random data at the actual operating speed.

According to the present invention, since the comparison means is composed of the comparator for comparing and verifying the test data input from the outside and the expected value data passing through the inside of the chip at the actual operation speed, the semiconductor device There is an effect that an actual operation test for the I / O interface can be realized.

According to the present invention, the data adjusting means is constituted by the delay circuit which makes the expected value data by delaying the test data passing through the inside of the chip, so that the adjustment of the time difference of the expected value data is performed by the test data. There is an effect that can be realized by the timing delay of.

According to the present invention, the test data generating means for generating the test data, the data adjusting means for adjusting the time difference for making the test data passing through the inside of the chip into the expected value data, and the chip provided in the input section are provided. In a semiconductor device having a comparing means for comparing and verifying test data propagated outside and expected value data, it is configured to have an external wiring for connecting an output of the test data generating means and an input of the comparing means. Therefore, an internal clock of the same speed as the system operation is applied to the test data generation means and comparison means, and the test data propagated via the external wiring is compared with the internal expected value data adjusted for the time difference. The actual operation test of the I / O interface of the semiconductor device can be realized by comparing and verifying the means. Others there is an effect that can reduce the test cost becomes unnecessary.

According to the present invention, the test data generating means is provided in the output section, and the test data is outputted from this, and the test data is passed through the data adjusting means to be expected value data and transmitted to the comparing means. With this configuration, similarly, by applying an internal clock having the same speed as the system operation to the test data generating means and the comparing means, an actual operation test of the I / O interface of the semiconductor device can be realized. This eliminates the need for a tester and has the effect of reducing test costs.

According to the present invention, the test data generating means includes the first test data generating means provided in the output section for generating the test data propagating outside the chip and the data adjusting means provided in the input section. The second test data generating means for generating the test data serving as the expected value data is used. Therefore, similarly, by applying the internal clock having the same speed as the system operation, the I / O of the semiconductor device is changed.
Not only can the actual operation test of the O interface be realized, but also the number of wirings vertically and horizontally in the internal circuit such as the logic portion of the semiconductor device can be reduced.

According to the present invention, the semiconductor device comprises a plurality of semiconductor devices, and the output pins and the input pins of the respective semiconductor devices are connected by the external wiring.
An actual operation test of I / O interfaces of a large number of semiconductor devices can be realized at the same time, which has an effect of reducing the test time.

According to the present invention, the test data generating means comprises the LFSR which operates at the actual operating speed, so that the test data is obtained as the pseudo random data of the actual operating speed and enables the actual operating test. Has the effect of

According to the present invention, since the comparison means is composed of a comparator for comparing and verifying the test data input from the outside and the expected value data passing through the inside of the chip at the actual operating speed, There is an effect that an actual operation test for the I / O interface can be realized.

According to the present invention, the data adjusting means is constituted by the delay circuit which makes the expected value data by delaying the test data passing through the inside of the chip. There is an effect that can be realized by the timing delay.

According to the present invention, the circuit to be measured for inputting external data from the data input pin and the strobe signal set to a predetermined standard are applied from the strobe pin to output data from the circuit to be measured and the external clock. The data latch means for capturing the clock input from the pin and the register means for extracting the data latched by the data latch means are provided, and the wiring from the data input pin to the data latch means and the data latch from the circuit under test are provided. Since the wiring up to the means and the wiring from the external clock pin to the circuit under test are configured to have the same length, by inputting the strobe signal at the same timing to the circuit elements forming the data latch means, There is no skew,
Timing verification of the circuit under test can be performed, which eliminates the need for an LSI tester with high-performance timing accuracy, and has the effect of reducing test costs.

According to the present invention, the data latch means is provided with a plurality of strobe flip-flops, and the wirings from the strobe pin to the plurality of strobe flip-flops are of equal length. By inputting the strobe signal to each of the strobe flip-flops at the same timing, there is an effect that there is no skew and the timing test of the circuit under test can be performed.

According to the present invention, the circuit under test is composed of an internal flip-flop, the wiring from the output to the input of the corresponding strobe flip-flop, and the data input of the internal flip-flop to the data of the corresponding strobe flip-flop. Since the wiring to the input has the same length as the wiring from the external clock pin to the internal flip-flop, the setup and hold timing of the internal flip-flop can be verified.

According to this invention, the scan shift register is connected to the output of the strobe flip-flop.
Since the output is pulled out to the outside of the chip by the TAG pin, there is an effect that the data latched in the register is scanned out by the JTAG control and the non-defective product or the defective product can be determined by the external inspection machine.

[Brief description of drawings]

FIG. 1 is a block diagram showing a test method of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a circuit connection diagram showing a test method of the semiconductor device according to the first embodiment of the present invention.

FIG. 3 is a circuit diagram showing a comparator according to the first embodiment of the present invention.

FIG. 4 is a block diagram showing a modification of the test method for the semiconductor device according to the first embodiment of the present invention.

FIG. 5 is a block diagram showing a test method of a semiconductor device according to a second embodiment of the present invention.

FIG. 6 is a block diagram showing a conventional semiconductor device test method.

[Explanation of symbols]

5 LSI (semiconductor device), 8 expected value data, 9 test data, 10 test data generator (LFSR: test data generating means, output unit), 10a first test data generator (LFSR: first data generating means) ), 1
0b Second detester generator (LFSR: second data generating means, LFSR), 11 clock, 12 output buffer (output section), 13 external wiring, 14 input buffer (input section), 15 comparator (comparing means) , 16,
87,161 delay circuit (data adjusting means), 17 test access port (TAP), 18 PLL, 19
JTAG pin, 20 TCK pin, 21 TMS pin,
22 TDI pins, 30, 41 flip-flops (F
/ F), 40 SET pin, 42 DIN pin, 43
EXP pin, 44 CLK pin, 45 RESET pin, 46 OR gate, 47 NAND gate, 48
Output QC, 49 NOR gate, 50 Output Q, 51
TDO pin, 60 user logic, 70 external clock, 80 internal flop-flop, 81a-81d strobe flip-flop (data latch means), 8
2 Strobe pin, 83 TDO pin, 85 differential amplifier, 86 scan flip-flop (SFF).

Claims (17)

[Claims] 1. A test data generating means for generating test data, a data adjusting means for adjusting the time difference between the test data passing through the inside of the chip to obtain expected value data, and a chip provided outside the chip. A semiconductor device comprising a comparing means for comparing and verifying the propagated test data and the expected value data. 2. The test data generating means is provided in the output section, which outputs the test data, and transmits the test data as expected value data via the data adjusting means to the comparing means. Claim 1
The semiconductor device described. 3. A first test data generating means is provided in the output section, and generates test data which propagates outside the chip.
2. The semiconductor device according to claim 1, further comprising: a test data generating unit of 1), and a second test data generating unit which is provided in the input unit and generates test data to be expected value data via a data adjusting unit. apparatus. 4. The semiconductor device according to claim 1, wherein the test data generating means includes an LFSR that operates at an actual operating speed. 5. The comparison means comprises a comparator for comparing and verifying test data input from the outside and expected value data passing through the inside of the chip at an actual operating speed. Semiconductor device. 6. The semiconductor device according to claim 1, wherein the data adjusting means is constituted by a delay circuit that delays the test data passing through the inside of the chip to obtain expected value data. 7. A test data generating means for generating test data, a data adjusting means for adjusting a time difference between the test data passing through the inside of the chip to obtain expected value data, and an outside of the chip provided in the input section. A semiconductor device comprising a comparing means for comparing and verifying the propagated test data and the expected value data, a semiconductor having an external wiring connecting an output of the test data generating means and an input of the comparing means. Device test method. 8. The test data generating means is provided in the output section, which outputs the test data from the output section, and transmits the test data as expected value data via the data adjusting means to the comparing means. Claim 7
The semiconductor device test method described. 9. A first test data generating means is provided in an output section to generate test data propagating outside a chip.
8. The semiconductor device according to claim 7, further comprising: a test data generating unit of 1), and a second test data generating unit which is provided in the input unit and generates test data to be expected value data via a data adjusting unit. Device test method. 10. The semiconductor device test method according to claim 7, wherein the semiconductor device comprises a plurality of semiconductor devices, and output pins and input pins of the respective semiconductor devices are connected by external wiring. 11. The test data generating means comprises an LFSR operating at an actual operating speed.
The semiconductor device test method described. 12. The comparison means is configured by a comparator for comparing and verifying test data input from the outside and expected value data passing through the inside of the chip at an actual operating speed. Semiconductor device test method. 13. The test method for a semiconductor device according to claim 7, wherein the data adjusting means is configured by a delay circuit that delays the test data passing through the inside of the chip to obtain expected value data. 14. A circuit to be measured which inputs external data from a data input pin, and a strobe signal set to a predetermined standard is applied from a strobe pin, and output data from the circuit to be measured and input from an external clock pin. In a semiconductor device having a data latch means for capturing a clock to be generated and a register means for drawing out the data latched by the data latch means, a wiring from the data input pin to the data latch means and the measured object A semiconductor device characterized in that the wiring from the circuit to the data latch means and the wiring from the external clock pin to the circuit under test are of equal length. 15. The data latch means comprises a plurality of strobe flip-flops, and each wiring from the strobe pin to the plurality of strobe flip-flops is of equal length. Semiconductor device. 16. The circuit under test comprises an internal flip-flop, and wiring from its output to the input of the corresponding strobe flip-flop and from the data input of the internal flip-flop to the data input of the corresponding strobe flip-flop. 16. The semiconductor device according to claim 15, wherein the wiring has the same length as the wiring from the external clock pin to the internal flip-flop. 17. The semiconductor device according to claim 15, wherein a scan shift register is connected to the output of the strobe flip-flop and the output is taken out of the chip by the JTAG pin.