JPH09307433A - Pll circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a PLL(phase locked loop) circuit which can shorten the time when the phase difference gets near zero and also can increase the loop operation speed. SOLUTION: A phase/frequency detection circuit 16 decides whether the phase difference between a reference signal SREF and a comparison signal SV is included in a 1st area set between -π/2 and +π/2 or in a 2nd area getting out of the 1st area. If the phase difference is included in the 2nd area (excluding ±π/2), a phase inverting circuit 17 outputs a comparison signal SV having its inverted phase.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PLL (Ph) having a control circuit for adjusting a phase difference between a reference signal input from the outside and a comparison signal generated inside to approach zero.
and an assured locked loop circuit.

[0002]

2. Description of the Related Art FIG. 7 shows a configuration of a conventional PLL circuit.
It is a block diagram. Phase / frequency comparison circuit 1 shown in FIG.
1 has a frequency f input from the outside._{RE F} Having ginseng
Illumination signal S_REF And the internally generated frequency f_v Have
Comparison signal S _v Is entered. Phase / frequency comparison circuit 11
Are these reference signals S_REF And comparison signal S_v Frequency with
And phase and compare their frequency and phase error
No. is output. The output error signal is charge pump 1
2 is input. The charge pump 12 is
A signal having a voltage level corresponding to the difference signal is output. This signal
Is input to the low-pass filter 13. Low pass fill
The input signal is a DC level control voltage signal.
Convert to. This control voltage signal is a voltage controlled oscillator (V
oltage Controlled Oscilla
tor, hereinafter abbreviated as “VCO”)
You. The VCO 14 operates according to the input control voltage signal.
Wave number f_out Oscillation signal S_out Generate This oscillation signal
S_out Is output to the outside of this PLL circuit.
Also, it is input to the internal frequency dividing circuit 45. Divider circuit 45
Is the input oscillation signal f_out Reference signal S_REF Frequency
Divide to the same frequency as the number, which allows the comparison
Signal S_v To generate the comparison signal S_v Phase / frequency
It is input to the number comparison circuit 11. Thus, P shown in FIG.
In the LL circuit, the reference signal S_REF And comparison signal S_v Frequency with
The number and phase error signals are input to the VCO 14
By reflecting it on the control voltage signal, the reference signal S _REF When
Comparison signal S_v To match the frequency and phase with
Works. In addition, for each frequency in this PLL circuit
The relationship is f_REF = F_v = F_out / N. here
And f_REF , F_v , F_out Are respectively reference signals S
_REF , Comparison signal S_v , Oscillation signal f_out The frequency of
N represents the frequency division ratio of the frequency dividing circuit 45.

FIG. 8 is a circuit diagram of the PLL circuit shown in FIG.
3 is a circuit diagram of a phase / frequency comparison circuit 11, a charge pump 12, and a low pass filter 13. FIG. A phase / frequency comparison circuit 11 shown in FIG. 8 includes a set / reset flip-flop (hereinafter simply referred to as a flip-flop) 11a including a NAND gate for two inputs or three inputs,
11b, 11c, 11d and NAND gate 1 for 4 inputs
1e and an inverter 11f, a reference signal S _REF and a comparison signal S _v are input to the input side, and a control signal UP ^* for advancing the phase from the output side and a control signal DN for delaying the phase. And are output. here,
UP ^* Bruno ^* represents that it is a signal of the low active. Hereinafter, the same applies. The charge pump 12 has a power source V
_The P channel MOS transistor 12a and the N channel MOS transistor 12b are connected in series between _DD and the ground potential V _SS.
The control signal UP ^* and the control signal DN are input to the gates of the transistor 12a and the N-channel MOS transistor 12b. Also, the P-channel MOS transistor 12a
From the connection point between the N-channel MOS transistor 12b and the N-channel MOS transistor 12b, a signal PD based on the control signal UP ^* and the control signal DN.
Is output. This signal PD is input to the low pass filter 13. The low pass filter 13 includes resistors 13a and 1
3b and a capacitor 13c, and a resistor 13
A DC level control voltage signal VLF is output from the connection point between a and the resistor 13b. In general, a lag-lead type incomplete integral quadratic type or a perfect integral quadratic type is often used as the configuration of the low-pass filter, and the lag-lead type incomplete integral quadratic type is illustrated here.

FIG. 9 is a timing chart for explaining the operations of phase / frequency comparison circuit 11 and charge pump 12 shown in FIG. As shown in FIG. 9, when the phase of the comparison signal S _v lags behind the phase of the reference signal S _REF , the control signal UP ^* for advancing the phase output from the phase / frequency comparison circuit 11 is generated. Change to'L 'level. The control signal DN is at the'L 'level. Therefore, the P-channel MOS that constitutes the charge pump 12
The transistor 12a and the N-channel MOS transistor 12b are turned on and off, respectively, and the phase detection signal PD output from the charge pump 12 is'
It changes to the _H'level (V _DD level). On the other hand, when the phase of the comparison signal S _{v leads} the phase of the reference signal S _REF , the control signal DN for delaying the phase changes to the'H 'level. The control signal UP ^* is at the'H 'level. Therefore, the P-channel MOS transistor 12
The a and N-channel MOS transistors 12b are turned off and on, respectively, and the phase detection signal PD output from the charge pump 12 changes to _the'L 'level (V _SS level). Further, the reference signal S _REF and the comparison signal S
_{If v} and the same phase, control signal UP ^* , control signal D
N is'H 'level,' L 'level respectively,
Therefore, both the P-channel MOS transistor 12a and the N-channel MOS transistor 12b are turned off, and the output signal PD of the charge pump 12 is in a high impedance state. Such a phase detection signal PD is supplied to the low-pass filter 13 as a DC level control voltage signal VLF.
And the converted control voltage signal VLF is converted to VCO1.
4 and the control voltage signal VLF from the VCO 14
An oscillation signal S _out having a frequency corresponding to is generated.

[0005]

FIG. 10 is a diagram showing the control voltage signal VLF input to the VCO 14 of the low pass filter 13 shown in FIG. Low-pass filter 13
The amplitude of the control voltage signal VLF output from is maximum near the phase difference of −π and + π between the reference signal S _REF and the comparison signal S _v, and becomes smaller as the phase difference approaches zero. When the phase difference is in the vicinity of + π and −π, the control voltage signal V
There is a problem that the amplitude of the LF is large, the loop operation time of the PLL circuit until the phase difference approaches zero is long, and thus the speedup of the loop operation is insufficient.

In view of the above circumstances, it is an object of the present invention to provide a PLL circuit in which the time until the phase difference approaches zero can be shortened and the loop operation can be speeded up.

[0007]

A PLL circuit of the present invention which achieves the above object, is a voltage control type oscillator for generating an oscillation signal of a frequency according to an input control voltage signal, and
A PLL circuit including a control circuit that adjusts the control voltage signal such that a phase difference between a reference signal input from the outside and a comparison signal generated based on the oscillation signal approaches zero. Within the first region in which the phase of the feedback signal composed of the oscillation signal or the feedback signal obtained by dividing the oscillation signal is sandwiched between -π / 2 and + π / 2 when the reference signal is used as a reference. Phase detection circuit for detecting whether the feedback signal is in the first area or the second area outside the first area (2) The phase of the feedback signal detected by the phase detection circuit is within the first area. Depending on whether or not the feedback signal is in the second region or the feedback signal is generated by inverting the phase of the feedback signal. The inverted signal, as said comparison signal, characterized by comprising a phase inverting circuit for sending to the control circuit.

Here, a frequency dividing circuit may be provided for generating the feedback signal by dividing the frequency of the oscillation signal into a frequency of an even number.

[0009]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below. FIG. 1 is a block diagram showing the configuration of a PLL circuit according to an embodiment of the present invention. The same components as those of the PLL circuit shown in FIG. 7 are designated by the same reference numerals, and duplicate description will be omitted.

The frequency divider circuit 15 shown in FIG.
The oscillation signal S _{out from} is input. The frequency dividing circuit 15 is
And the same divided down frequency and the frequency of the reference signal S _REF the input oscillation signal S _out outputs a divided signal S _vo, frequency doubled signal having a frequency twice 2f _vo of the divided signal S _vo Output 2S _vo . Phase / frequency detection circuit 16
A reference signal S _REF , a comparison signal S _v generated by a phase inverting circuit 17 described later, and a signal S _2v ^* having a phase relationship delayed by π / 2 with respect to the comparison signal S _v are input. It The phase / frequency detection circuit 16 includes a frequency detection unit that detects whether the frequencies of the input reference signal S _REF and the comparison signal S _v are equal to each other, and the reference signal S in the frequency detection unit.
_When it is detected that the frequencies of _REF and the comparison signal S _v are equal, the first region in which the phase of the comparison signal S _v with reference to the reference signal S _REF is sandwiched between −π / 2 and + π / 2 A phase detection section (a phase detection circuit according to the present invention) that detects whether it is inside or inside a second area deviating from the first area and outputs a signal LPFD indicating the detection result. Has been done. Details of the frequency detection unit and the phase detection unit will be described later.

The phase inverting circuit 17 is provided by the frequency dividing circuit 15.
Double frequency signal 2S_vo, Divided signal S_vo, And phase / frequency
The signal LPFD from the detection circuit 16 is input, and the signal L
The reference signal S based on the PFD_REF And comparison signal S_v With
The frequencies are equal and the reference signal S_REF And comparison signal S_v With
If the phase difference is within the second region other than ± π / 2, the
Circular signal S_voThe inverted signal is generated by inverting the phase of
Inversion signal, comparison signal S _v Phase / frequency detection circuit 1
6 and the phase / frequency comparison circuit 11. on the other hand,
Reference signal S_REF And comparison signal S_v Are equal in frequency and
Reference signal S_REFAnd comparison signal S_v And the phase difference with -π / 2
If it is in the first area between + π / 2, the frequency division
No. S_voThe comparison signal S_v Phase / frequency detection as
Input to the circuit 16 and the phase / frequency comparison circuit 11.

In such a circuit configuration,
The relationship is f_REF = F_v = F_vo= 2f _vo/ 2 = f_out/ N
Is shown. Where f_REF , F_v , F_vo, 2f_vo, F
_out Are respectively reference signals S_REF , Comparison signal S_v ， Minute
Circular signal S_vo, Double frequency signal 2S_vo, Oscillation signal S_out Frequency
Represents the number, and N represents the frequency division ratio of the frequency dividing circuit 15. FIG.
Is the frequency of the phase / frequency detection circuit 16 shown in FIG.
FIG. 3 is a circuit diagram of the number detecting unit, and FIG. 3 is a circuit diagram of the frequency detecting unit shown in FIG.
It is a timing chart.

The frequency detecting section shown in FIG.
_It is to detect whether or not the frequency of _{REF and} the frequency of the comparison signal S _v are equal. The data terminal D and the clock terminal CK of the edge trigger D type flip-flop (hereinafter abbreviated as flip-flop) 21 shown in FIG. 2 are first compared with the reference signal S _REF at the “H” level and the “L” level shown in FIG. The signal S _v is input. Next, the comparison signal S _v is
When the L'level changes to the'H 'level, the flip-flop 21 outputs the'H' level signal at the rising edge thereof. Next, the reference signal S _{REF of'L} 'level is input to the data terminal D of the flip-flop 22.
Here, the flip-flop 2 is passed through the inverter 28.
The comparison signal S _v input to the second clock terminal CK
The signal S _{v _} which is the inverted signal of the signal from "L" level to "H"
When transitioning to the level, the flip-flop 22 outputs the signal of the'L 'level at the rising edge thereof. The signal output from the flip-flop 21 and the signal output from the flip-flop 22 are input to the exclusive OR gate 23. When the levels of the input signals are different from each other, the signal of the'H 'level is output from the exclusive OR gate 23. Is output. In addition, the reference signal S
Similarly, in the circuit configuration including the flip-flops 24 and 25, the inverter 29, and the exclusive OR gate 26, which is the circuit configuration in which the relationship between the _REF and the comparison signal S _v is switched, the signal output from the flip-flops 24 and 25 is also the same. When the levels are different from each other, the exclusive OR gate 26 outputs an'H 'level signal.
Exclusive OR gate 2 obtained in this way
The output signals of both 3 and 26 are input to the AND gate 27, and the AND gate 27 outputs an'H 'level signal FR.
EV is output. In this way, it can be detected that the frequencies of the reference signal S _REF and the comparison signal S _v are equal to each other.

FIG. 4 is a circuit diagram of the phase detecting section and the phase inverting circuit 17 in the phase / frequency detecting circuit 16 shown in FIG. 1, and FIG. 5 is the phase detecting section and the phase inverting circuit 17 shown in FIG.
It is a timing chart with. First, the timing chart of FIG. 5 will be described. Reference signal S _RE shown in FIG.
The'H 'level section Tp of _F is the reference signal S _REF.
On the other hand, a region where the phase of the comparison signal S _v is 0 to −π (specifically, a region where the first half of the interval Tp is 0 to −π / 2, a region T
It shows that the latter half part of p is in the region of −π / 2 to −π). The section Tn of 'L' level of the reference signal S _REF is the phase + Pai～0 region of the comparison signal S _v with respect to the reference signal S _REF (details, the first half of the interval Tn is + π~ + π / 2 area, the second half of the section Tn is + π / 2
˜0 area). Here, the first half of the section Tp (0 to −π / 2) and the second half of the section Tn (+ π / 2 to 0) represent the first region of the present invention, and the second half of the section Tp (−π /). 2 to −π) and a section Td indicating the first half (+ π to + π / 2) of the section Tn indicate the second region (region other than ± π / 2) according to the present invention.

In the PLL circuit of this embodiment, the reference signal S
_In the phase relationship between _REF and the comparison signal S _v , the phase difference is ± π
If the / 2 other regions, the rising edge of the comparison signal S _v in other words when in the field Td shown in FIG. 5, which inverts the comparison signal S _v. Here, for ease of explanation, the phase relationship between the reference signal S _REF and the comparison signal S _v will be described in the following four cases (1), (2), (3), and (4). (1) The phase of the comparison signal S _v with respect to the reference signal S _REF is
In the case of the area of 0 to -π / 2 (the first half of the section Tp).

This case is represented by the timing chart at P1 shown in FIG. In addition, in P1 of FIG.
The subscript 1 shown at the right end of each character is four cases (1)-
It is included to indicate (1) of (4). For example, S _v (comparison signal) is described as S _v1, and 2S _vo (double frequency signal) is described as 2S _v1 .
Hereinafter, also in P2, P3, and P4 of FIG. 5, the subscripts 2, 3, and 4 are similarly described corresponding to each case. Further, here, the signal S _2v1 ^* generated at the rising edge of the double-frequency signal 2S _v1 from the frequency _dividing circuit 15 of the flip-flop 37 included in the phase inversion circuit 17 shown in FIG.
_Have a phase relationship delayed by π / 2 with respect to the comparison signal S _v1 . Further, in the initial state, the flip-flops 32 and 34 forming the phase detection unit are in the clear state, and the flip-flops 32 and 34 output the signal of the “L” level. Therefore, the clock terminal CK of the flip-flop 36
A signal of'L 'level is input to the via the OR gate 35.

First, in the first half of the section Tp, the free
Data terminal D and clock terminal CK of the flip-flop 31
'H' level reference signal S_REF , 'L' level comparison
Signal S _v1Is entered. Next, the flip-flop 31
Comparison signal S input to clock terminal CK_v1But'
The transition from L'level to'H 'level
Reference signal S of'H 'level at edge_REF Is triggered,
The signal Q at the'H 'level from the flip-flop 31_va1 But
Is output. Output'Q 'level signal Q_va1Is
Clear terminal CLR of flip-flop 32^* Entered in
This clears the clear function of the flip-flop 32.
Be removed.

Next, in the latter half of the section Tp, the reference signal S _{REF of the'L} 'level is input to the data terminal D of the flip-flop 32 via the inverter 39.
Next, the signal S from the flip-flop 37 is input to the clock terminal CK of the flip-flop 32.
_2v1 ^* transits from the “L” level to the “H” level. Then, the reference signal S of'L 'level is generated at the rising edge.
_{The REF} is triggered and the flip-flop 32 outputs the signal Q _2val at the “L” level. _This'L 'level signal Q _2val is input to one of the OR _gates 35. In addition, the other side of the OR gate 35 is provided with a signal from the flip-flop 34.
Since the L'level signal is input, the OR gate 35 outputs the'L 'level signal. this'
The L'level signal is input to the clock terminal CK of the flip-flop 36. Here, the signal FREV from the frequency detection unit shown in FIG. 2 is input to the clear terminal CLR ^* of the flip-flop 36, and the reference signal S
_When the frequency of _REF is equal to the frequency of the comparison signal S _v , this signal FREV is at the “H” level, so the clear function of the flip-flop 36 is canceled. On the other hand, the reference signal S
If the frequencies of _REF and comparison signal S _v1 are different, signal F
Since REV is at'L 'level, flip-flop 3
The clear function of 6 is not released, and the flip-flop 3
A signal LPFD of'L 'level is output from 6. Here, even when the clear function of the flip-flop 36 is released, the signal from the OR gate 35 remains at the “L” level as described above, and the signal is input to the data terminal D of the flip-flop 36. Reference signal S
_{Since REF is} also at the “L” level, the flip-flop 36 outputs the “L” level signal LPFD. this'
The L'level signal LPFD is input to one side of the exclusive OR gate 38, and the _divided signal S _vo is input to the other side of the exclusive OR gate 38. Therefore, the _divided signal S _vo is not inverted by the exclusive OR gate 38, and the _divided signal S _vo is output as it is as the comparison signal S _v1 . As described above, even when the frequencies of the reference signal S _REF and the comparison signal S _v1 are equal, the phases of the reference signal S _REF and the comparison signal S _v are 0.
In the region of-? / 2, the comparison signal _Sv is not inverted but is output as it is. (2) The phase of the comparison signal S _v with respect to the reference signal S _REF is
In the case of in the region of −π / 2 to −π (the latter half of the section Tp).

This case is represented by the timing chart at P2 shown in FIG. First, in the second half of the section Tp, the data terminal D and the clock terminal CK of the flip-flop 31 are supplied with the “H” level reference signals S _REF , ′.
The L ′ level comparison signal S _v2 is input. Next, when the comparison signal S _v2 input to the clock terminal CK of the flip-flop 31 transits from the “L” level to the “H” level, the reference signal S of the “H” level is generated at the rising edge thereof.
_{The REF} is triggered and the flip-flop 31 outputs the signal _Hva level signal _Qva2 . The output “H” level signal Q _va2 is input to the clear terminal CLR ^* of the flip-flop 32, whereby the flip-flop 32
The clear function of is canceled.

Next, in the first half of the section Tn, the free
The inverter 39 is connected to the data terminal D of the flip-flop 32.
Via the reference signal S of'H 'level_REF Is entered.
Next, input to the clock terminal CK of the flip-flop 32
Signal S from the flip-flop 37
_2v2 ^*Shifts from the'L 'level to the'H' level. Do
And the reference signal S of'H 'level at the rising edge thereof.
_REF Is triggered and the'H 'level is returned from the flip-flop 32.
Bell signal Q_2va2Is output. This'H 'level belief
No. Q_2va2Is input to the OR gate 35. Then Oage
The output signal of the gate 35 changes from the "L" level to the "H" level.
Transition. This output signal is the clock of the flip-flop 36.
Input to the clock terminal CK. Where flip flops
36 clear terminals CLR^* Is the circumference shown in FIG.
The signal FREV from the wave number detector is input,
Signal S_REF And comparison signal S_v And the frequencies are equal,
Since this signal FREV is at the'H 'level, the flip
The clear function of the flop 36 is released. Where the section
In the first half of Tn, the data end of the flip-flop 36
The child D is connected to the'H 'level via the inverter 39.
Illumination signal S_REF Is input to the clock terminal CK.
The signal from the OR gate 35 being applied is at the'L 'level
Transition to the'H 'level, its rising edge
And the reference signal S of'H 'level_REF Is triggered and flickers
The high-level signal LPFD is output from the flip-flop 36.
Is done. This'H 'level signal LPFD is
Input to one of the four or gates 38.
Input to the other side of exclusive OR gate 38
Divided signal S_voAt the exclusive OR gate 38
Flipped. Inverted divided signal S_voIs the comparison signal S_v2When
And output. In this way, the reference signal S_REF And comparison signal
S_v2And the frequency is the same, and the reference signal S
_REFAnd comparison signal S_v2Area with a phase difference of -π / 2 to -π
Comparison signal S _v2Is inverted and output. (3) Reference signal S_REF For comparison signal S_v The phase of
In the case of the region of π to π / 2 (the first half of the section Tn).

This case is represented by the timing chart in P3 shown in FIG. First, in the first half of the section Tn, the reference signal S _REF of the “H” level is supplied to the data terminal D of the flip-flop 33 via the inverter 39.
And the comparison signal S _{v3 of the'L} 'level is input to the clock terminal CK of the flip-flop 33. Next, when the comparison signal S _v3 transits from the “L” level to the “H” level, the reference signal S _REF of the “H” level is triggered at the rising edge thereof, and the flip-flop 33 outputs the “H” level signal Q _vb3. Is output. The output “H” level signal Q _vb3 is _supplied to the flip-flop 34.
Is input to the clear terminal CLR ^* of the flip-flop 34, and the clear function of the flip-flop 34 is released.

Next, in the second half of the section Tn, the flip-flop is
Via the inverter 39 to the data terminal D of the rope 34
'H' level reference signal S_REF Is entered. next,
Input to the clock terminal CK of the flip-flop 34
Signal S from the flip-flop 37_2v3 ^*Is ‘L’
Transition from level to'H 'level. Then the standing
Reference signal S of'H 'level at rising edge_REF Is triggered
The flip-flop 34 outputs the signal Q at the'H 'level.
_2vb3Is output. This'H 'level signal Q_{2v b3}Ha
It is input to the agate 35. Then from OR gate 35
The output signal changes from'L 'level to'H' level
I do. This output signal is the clock of the flip-flop 36.
It is input to the terminal CK. Where the flip-flop 36
Clear terminal CLR^* Is the signal F from the frequency detector.
REV is input and the reference signal S_REF And comparison signal S
_v If the frequencies are equal to
Clears flip-flop 36 because it is at H'level
The function is canceled. Here, in the latter half of the section Tn,
The inverter 3 is connected to the data terminal D of the flip-flop 36.
'H' level reference signal S via_REF Is entered
OR gate input to clock terminal CK
Signal from 35 transits from'L 'level to'H' level
Then, the reference signal S at the'H 'level is generated at the rising edge.
_REF Is triggered, causing the flip-flop 36 to return the'H 'level.
The bell signal LPFD is output. This'H 'level
The signal LPFD is one of the exclusive OR gates 38.
Input to the exclusive OR gate 3
Divided signal S input to the other of 8_voIs that exc
It is inverted at the luscious OR gate 38. Inverted division
Signal S_voIs the comparison signal S_v3Is output as in this way
Reference signal S_REF And comparison signal S _v And the frequency is the same
And the reference signal S_REF And comparison signal S_v3Phase with
If the difference is within the region of + π to + π / 2, the comparison signal S
_v3Is inverted and output.

(4) Comparison signal S with respect to reference signal S _REF
The phase of _v is in the region of + π / 2 to 0 (the latter half of the section Tn). This case is represented by the timing chart at P4 shown in FIG. First, in the latter half of the section Tn,
The inverter 39 is connected to the data terminal D of the flip-flop 33.
The reference signal S _REF of the “H” level is input via the clock signal and the clock terminal C of the flip-flop 33.
_The'L 'level comparison signal S _v4 is input to K. next,
The comparison signal S _v4 transits from the “L” level to the “H” level. Then, the rising edge triggers the reference signal S _REF at the “H” level, and the flip-flop 33 outputs the reference signal S _REF.
The _H'level signal Q _vb4 is output. Output '
The _H′- level signal Q _vb4 is input to the clear terminal CLR ^* of the flip-flop 34, whereby the clear function of the flip-flop 34 is released.

Next, in the next section of the latter half of the section Tn.
In the first half of the section Tp, the flip-flop 34
To the data terminal D of the
Bell reference signal S_REF Is entered. Next, flip
Free input to the clock terminal CK of the lop 34
Signal S from the flip-flop 37_2v4 ^*Is the'L 'level
When it goes to'H 'level,
L'level reference signal S _REF Is triggered and flip
From the lop 34, the signal Q of'L 'level_2vb4Is output
It is. This'L 'level signal Q_2vb4Or gate 35
Is input to Therefore, from the OR gate 35, the'L 'level
Signal is output. This'L 'level signal is free
It is input to the clock terminal CK of the flip-flop 36. This
Here, the clear terminal CLR of the flip-flop 36^* To
Is the signal FREV from the frequency detector
Reference signal S_REF And comparison signal S_v4Are equal in frequency
In this case, since this signal FREV is at the'H 'level,
The clear function of the flip-flop 36 is released. Only
However, as described above, the signal from the OR gate 35 is'L '.
Level, and the data terminal of the flip-flop 36
Reference signal S input to D _REF Is also at the'L 'level,
From the flip-flop 36, the signal LPF of'L 'level
D is output. This'L 'level signal LPFD is
Input to one of the exclusive OR gates 38
Therefore, it is input to the other side of the exclusive OR gate 38.
Divided signal S_voIs not inverted, and the divided signal S_vo
Is the comparison signal S_v4Is output as in this way
Reference signal S_REF And comparison signal S_v4And the frequency is the same
Even those reference signals S_REF And comparison signal S_v4With
In the region where the phase difference is + π / 2 to 0, the comparison signal S_v4Is anti
It is output without being rotated.

As described above, in the PLL circuit of this embodiment,
The comparison signal S _v is inverted when the phase of the comparison signal S _v with reference to the reference signal S _REF is in a region other than ± π / 2. Here, the magnitude of the reduction of the phase difference due to the inversion of the comparison signal S _v will be described with reference to FIG. FIG. 6 is a timing chart for explaining the magnitude of reduction in the phase difference before and after the phase of the comparison signal S _v is inverted.

In the timing chart of P2 shown in FIG. 6, there is a case where the phase of the comparison signal S _v is in the region of −π / 2 to −π with respect to the reference signal S _REF (case (2) described above). The comparison signal S _v is shown as S _{v2 for} the initial state before the phase is inverted and as S _v2 ^* for the state after the phase is inverted. The phase difference between the reference signal S _REF and the comparison signal S _v2 before the comparison signal S _v2 was inverted was in the interval t _p2 , but after the comparison signal S _v2 was inverted by the'H 'level signal LPFD. , The phase difference between the reference signal S _REF and the comparison signal S _v2 ^* is in the interval t _a2.
Is shortened to That is, in a section T that is one cycle of the reference signal S _REF , a positive section Tp that is the “H” level and a negative section Tn that is the “L” level of the section T, Tp =
Since Tn = T / 2, tn (here, t _a2 ) = T /
2-tp (here, t _p2 ) (T / 4 <tp <T / 2) is established, and therefore, the effect of shortening the section of tn <tp can be obtained.

Further, the timing at P3 shown in FIG.
In the chart, the reference signal S_REF For comparison signal S_v of
When the phase is in the region of + π to + π / 2 ((3) above)
In the case of) is shown. In this case as well,
Comparison signal S_v3The reference signal S before_REF When
Comparison signal S_v3The phase difference between_p3Was the ratio
Comparison signal S_v3The reference signal S after the_REF And ratio
Comparison signal S_v3 ^* The phase difference between_a3Is shortened to Follow
, Tp (here t_a3) <Tn (here t _n3)
The effect of shortening the section is obtained.

[0028]

According to the present invention, the time until the phase difference between the externally input reference signal and the internally generated comparison signal approaches zero is shortened and the loop operation speed is increased.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a PLL circuit according to an embodiment of the present invention.

FIG. 2 is a circuit diagram of a frequency detection unit in the phase / frequency detection circuit 16 shown in FIG.

FIG. 3 is a timing chart of the frequency detection unit shown in FIG.

4 is a circuit diagram of a phase detection unit and a phase inversion circuit 17 in the phase / frequency detection circuit 16 shown in FIG.

5 is a timing chart of the phase detector and the phase inversion circuit 17 shown in FIG.

FIG. 6 is a graph showing the comparison signal S _v before and after the phase inversion,
6 is a timing chart for explaining the magnitude of reduction in phase difference.

FIG. 7 is a block diagram showing a configuration of a conventional PLL circuit.

8 is a circuit diagram of a phase / frequency comparison circuit 11, a charge pump 12, and a low pass filter 13 in the PLL circuit shown in FIG.

9 is a timing chart for explaining operations of the phase / frequency comparison circuit 11 and the charge pump 12 shown in FIG.

10 is a VCO of the low-pass filter 13 shown in FIG.
13 is a diagram showing a control voltage signal VLF input to FIG.

[Explanation of symbols]

11 Phase / Frequency Comparison Circuit 12 Charge Pump 13 Low Pass Filter 14 VCO 15 Frequency Division Circuit 16 Phase / Frequency Detection Circuit 17 Phase Inversion Circuit 21, 22, 24, 25, 31, 32, 33, 34, 3
6,37 Flip-flop 23,26,38 Exclusive OR gate 27 AND gate 28,29,39 Inverter 35 OR gate

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location H03L 7/10 H03L 7/10 A

Claims (2)

[Claims] 1. A voltage-controlled oscillator that generates an oscillation signal having a frequency according to an input control voltage signal, and a reference signal that is input from the outside and a comparison signal that is generated based on the oscillation signal. In a PLL circuit including a control circuit that adjusts the control voltage signal so that the phase difference approaches zero, a feedback signal composed of the oscillation signal or the oscillation signal is divided when the reference signal is used as a reference. The phase of the feedback signal is -π / 2 and + π / 2
And a feedback signal detected by the phase detection circuit, and a phase detection circuit for detecting whether the phase detection circuit is in a first region sandwiched between and or in a second region deviated from the first region. Depending on whether the phase of the feedback signal is in the first region or the second region, respectively, the feedback signal as it is or an inverted signal obtained by inverting the phase of the feedback signal is generated, and A PLL circuit comprising a phase inversion circuit that sends an inversion signal to the control circuit as the comparison signal. 2. The PLL according to claim 1, further comprising a frequency divider circuit that generates the feedback signal by dividing the oscillation signal into a frequency of an even number.
circuit.