TW514742B - Internal probe pad for failure analysis - Google Patents

Abstract

The present invention relates to an internal probe pad for failure analysis. The present invention proposes a circuit system, which comprises plural probe pads located on the last metal layer of the die. Each probe pad can be divided into plural conductive regions, and each conductive region is selectively connected to a contact in the internal circuit through the interconnect. By applying signal to at least a probe pad in plural probe pads, the mode of circuit can be set up. Signals are inputted to part of the probe pads in plural probe pads for setting up the mode of the circuit system in the die, wherein a probe pad is provided for grounding, and at least one probe pad is provided for transmitting signals into the circuit.

Description

514742 V. Description of the invention (1) 5-1 Field of the invention: The present invention is a device related to a semiconductor integrated circuit, particularly a device with an internal probe pad. 5-2 Background of the Invention: A typical 1C has many contacts as the interface between the circuit in the die and the outside world. These contacts can be used as bond pads to which bonding wires are connected. These bonding wires are also connected to a lead frame. These contacts can be used to input different signals, including address, data, power (VCC), ground (VSS), and control signals. However, these contacts are generally very small, so it is impractical and expensive to directly connect each contact to a probe for testing or repairing IC. Probe pads are much larger than the wafer contacts and have been applied to the edge of the wafer. However, the volume of the contacts will limit the number of contacts to which the probe can actually be connected. A typical fault analysis involves applying a selected voltage to the circuit input and checking the selected output voltage, which can be implemented by a functional tester (f u n c t i ο n a 1 t e s t e r) or a mechanical probe system. The mechanical probe system allows fault analysis techniques to be applied to the probe to confirm that the conductance is connected to a selected location in a chip circuit system. However, this worked

514742 V. Description of the invention (2) is difficult and takes time. This technique must use a microscope to visually find the location to be measured from thousands or even millions of transistors and four or five layers of metal, and then manually move the probe to that point. Due to mechanical space constraints, only manual probes can be applied to this system. The number of probes available is limited, which limits the types of fault analysis that can be performed with this method. The electronic devices in an integrated circuit are electrically coupled via an interconnect. The interconnect is formed by transferring a conductor layer on or on the surface of a silicon substrate through pattern transfer. One or more conductor layers can be transferred through a pattern to form one or more interconnects, and the interconnects of each layer can be separated by one or more interlayer dielectric layers. Materials commonly used as interlayer dielectric layers include silicon dioxide, silicon nitride, and polyimide. The dielectric interconnect layer allows densely patterned devices to be formed in a relatively small surface area. The interconnects of different layers are usually electrically coupled with dielectric plugs. The interconnects can be formed by layer-by-layer stacking of different conductive layers. Generally, these metal stacks typically include titanium, is, copper, crane, and alloys of these metals. In the previous method, when a mode was set, a probe pad corresponds to only one contact, so many probes were used. This is not conducive to using a microscope to observe whether a hot spot or emission spot has occurred, especially in some configurations, such as L 0 C (1 ead ο nchip). Excessive probes make the wafer more difficult. Take measurements.

Page 5 514742 V. Description of the invention (3) 5-3 Purpose and summary of the invention An object of the present invention is to reduce the number of probe pads required in the setting mode. It is an object of the present invention to complete the setting mode with fewer probes. An object of the present invention is to make it easier to observe defects during fault analysis. Therefore, according to the above purpose, the present invention proposes a circuit system for a wafer. The circuit system includes at least a plurality of probe pads and is located on the last metal layer of the wafer. Each probe pad is divided into a plurality of conductive areas, and each conductive area is selectively connected to a contact of an internal circuit of the chip via an interconnect. By applying a signal to at least one of the plurality of probe pads, the mode of the circuit can be set. In addition, the surface of the final metal layer may be covered with a protective layer, and there is an opening on the protective layer to expose the probe 塾. The present invention provides a method for setting a mode of a chip circuit with an internal probe pad. This method first forms a plurality of probe pads on the last metal layer of the wafer, where each probe pad is divided into several conductive areas, and each

514742 V. Description of the invention (4) ~ The conductive areas are selectively connected to one of the contacts of the internal circuit of the chip via an interconnect. Second, input signals to the plurality of probe pads to set the mode of the chip's circuit system. The pads are used for grounding, and at least one probe pad is used to pass signals into the electrical, probe pads on the wafer. There is no limit to the arrangement. The number of conductive areas on each probe pad is at least two, the shape of the conductive areas is not limited, and the arrangement manner is also not limited.

5-4 Detailed Description of the Invention: Preferred embodiments of the present invention will be discussed in detail later. The embodiment is used to describe a specific example of using the present invention and is not intended to limit the scope of the present invention. In the method of the present invention, as shown in the first figure, in addition to forming bond pads 201, 202 on the last metal layer of the wafer 20, internal probe pads 30, 40. Among them, the first internal probe pad 30 is divided into four conductive areas, 301 to 304, as shown in the second figure. 'Each conductive area is connected to the internal circuit via an interconnect (interc〇nnect). One contact (c 0 nact), the first conductive region 3 0 1 is connected to VCC 701, and the second conductive region 30 2 is connected to CLK (system clock

514742 V. Description of the invention (5)) 722, the third conductive region 3 0 3 is also connected to CLK 72 2, and the fourth conductive region 3 0 4 is connected to CKE (clock enable) 724, with a gap of 30 between each conductive region 5 separate. When the first probe 30 contacts the first probe pad 30, it will be connected to the four conductive areas at the same time, and a signal or voltage will be transmitted to the four conductive areas. The other second probe pad 40 is divided into two conductive areas, as shown in the third figure, in which the fifth conductive area 401 is connected to vss 702, and the sixth conductive area 402 is not connected to other circuits. . There is a distance of 405 between the two conductive areas, and the second probe 407 is used to contact the second probe pad 40 to ground the wafer 20. The Λ part Λ needle Λ shown in the above four points is via an interconnect, as shown in the figure 48 and the second probe pad 40 is in the same position. ^ Circuit-linked. The first-probe pads 30 and 5 2 are taken into the layer 520 one after the other. In this last metal layer, the interconnects / Jiu Xi, the conductive layer can be pattern transferred to form one or more partitions. For example, the fourth layer: one or more interlayer dielectric layers can be used to connect the same layer to 530, and the dielectric layer is not below the metal layer after the attack, there is a dielectric layer under the metal layer, and there is another conductive layer. Metal layer 5 4 0. And it is still possible that the first conductive electrical layer is below this metal layer 540. See FIG. 48, FIG. 54 2 and the first 逡 仏 〇1 through the first metal plug 5 332, the first internal wiring 701. Fourth conductive region. Connect the ,,, and to the VCC contact line 5 4 4 and the second line of the chip internal circuit 70 by the second metal plug 534 and the second internal connection point 724. The fifth lead 2 and 6 0 2 are connected to the internal circuit 70 of the chip; the CKE connection line 5 4 6 and the fourth field 4 0 1 are connected through the third metal plug 5 3 6 and the third inner-wire 6 0 3 To VSS contact on internal circuit 70

514742 V. Description of the invention (6) 702 ° In addition, a protective layer 51 may be covered on the metal layer 520 of the Lihou. There is a first opening 512 in the protective layer 510 to expose the first probe pad 30, and a second opening 514 to expose the second probe pad 40. The first probe 307 is in contact with the first probe pad 30 through the first opening 512, and the second probe 407 is in contact with the second probe pad 40 through the second opening 514. In this embodiment, the internal circuit 70 of the chip 20 is an example of a memory device. As shown in FIG. 4B, in addition to the above VCC () 7〇1 yssr k .round) 70 2, CKE (clock enab 1 e); y It el cl〇ck) 722, there are other commonly used contacts, such as cs (chip select) 732 > RAS (row address strobe) 734 ^ CAS address strobe) 736, And WE (write enable) etc. can also be linked in the same way. To analyze 1 field, the next day of the film = failure, failure analysis, you need to explore the oblique implementation ^ specific ^ work ^ mode, you can connect the first probe 3 0 7 to the second, flute ' The second probe 407 is connected to the second probe pad 40. The second probe pad 4 passes through the first probe pad 3. The signal is applied to the chip circuit. Probe 7 is grounded. For example: using the first probe 3G7 and the second probe = secondary voltage 5V, then VCC = 5V, CKE = 5V, CLK = 5V, and wooden pin 407 is grounded, then vss = (^. 514742 V. Description of the invention (7) In addition, the arrangement of the probe pads on the wafer 20 is aligned in this embodiment, but this is not necessary and can be arranged in any method. The number of conductive areas on each probe pad is at least There are two. In this embodiment, there are four and two respectively. The conductive areas in each probe pad can be connected to the same or different contacts of the internal circuit of the chip, depending on the design. The pin pad may also be connected to the same internal circuit contact via an internal connection. The shape of the conductive area is not limited, and it can be square, circular, regular or irregular, and the arrangement is not limited. It can be Regular or arbitrary distribution.

Page 10 514742 Brief Description of Drawings The first drawing shows a top view of a semiconductor wafer and wafer. The second figure shows a top view of an internal probe pad with four conductive areas. The third figure shows a top view of another internal probe pad with two conductive areas. Figure 4A shows a cross-sectional view of the needles and interconnects in a chip. Figure 4B shows a top view of the internal circuitry of a chip. Representative symbols of main parts: 10 wafers 2 0 wafers 2 01 pads 2 0 2 pads 3 0 first probe pads 301 first conductance area 3 0 2 second conductance area 3 0 3 third conductance area 3 0 4 Fourth conductivity region 3 0 5 first interval 3 0 7 first probe

514742 Brief description of the drawing 4 0 second probe pad 401 fifth conductivity area 4 0 2 sixth conductivity area 4 0 5 second interval 4 0 7 second probe 5 1 0 protective layer < 1 5 1 2 first Opening 5 1 4 Second opening 5 2 0 Last metal layer 5 3 0 Dielectric layer 532 First via plug 5 3 4 Second via plug 5 3 6 Third via plug 5 3 8 Fourth via Layer plug 5 4 0 metal layer 5 4 2 first interconnect 5 4 4 second interconnect 5 4 6 third interconnect 5 4 8 fourth interconnect Φ 6 01 first wire 6 0 2 Two conductors 6 0 3 Third conductor 70 Chip internal circuit 701VCC contact

Page 12 514742 Brief description of the diagram 7 0 2VSS contact 7 1 0 input and output buffer 7 2 0 timing device 72 2CLK contact 7 24CKE contact 7 3 0 instruction decoder 7 3 2CS contact 7 34RAS contact 7 3 6 CAS contact 7 38WE contact 7 4 0 Memory array 7 4 2 column decoder 7 4 4 row decoder

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Claims (1)

514742 Page 14 514742 VI. Scope of patent application A plurality of probe pads are located on a metal layer of the wafer, wherein each of the plurality of probe pads includes a plurality of conductive areas, and the plurality of conductive pads are conductive. Each conductive region in the region is selectively connected to a contact of a circuit in the chip, and a signal is provided to at least one of the plurality of probe pads to set the circuit to a Mode; and a multilayer interconnection structure for connecting the plurality of probe pads to the contacts of the circuit in the chip. 8. If the device in the scope of patent application No. 7 further includes a protective layer on the metal layer, and there are a plurality of openings in the protective layer to expose the plurality of probe pads. 9. As for the device in the scope of patent application No. 7, wherein the above-mentioned plurality of conductive areas are formed by touch-engraving. 10. The device according to item 7 of the scope of patent application, wherein the shape of the plurality of conductive regions described above is rectangular. 1 1. The device according to item 7 of the scope of patent application, wherein the plurality of conductive areas described above are connected to the same or different contacts on the circuit in the chip. 1 2. —A method of setting a circuit mode in a chip with an internal probe pad, the method at least includes: Page 15 514742 6. The scope of the patent application forms a plurality of probe pads on a metal layer of the wafer, wherein each of the plurality of probe pads includes a plurality of conductive areas, and the plurality of Each conductive area in the conductive area is selectively connected to a contact of the circuit in the chip via an interconnect; and a signal is input to a part of the probe pads of the plurality of probe pads to set the chip Mode inside the circuit. 'h 1 3. The method according to item 12 of the patent application range, wherein the signal input step described above includes at least one of the probe pads for grounding, and at least one of the probe pads for transmitting signals to the chip. Inside the circuit. Page 16