513771 A7 ____B7___ 五、發明説明（） 發明領域： (請先¾讀背面之注意事項再填寫本頁) 本發明與一種半導體製程有關，特別是一種用來 檢測半導體製程中內連線其缺陷之方法。 發明背景： ' 隨著超大型積體電路（VLSI)技術的持續發展，由於 積體電路的面積日益縮減，所製造之半導體元件如記憶體 單元等的尺寸亦大幅縮小，也由此導致晶片構裝密度有持 續增加之趨勢。並且藉著降低工業元件尺寸，也完成高整 合積集度之半導體ICs。然而在此種ICs的製造上，卻也 面臨諸多挑戰。 經濟部中央標準局員工消費合作社印製 伴隨著上述晶片積集度的持續增加，近代的積體電 路往往需在有限的晶片面積上，連結數以百萬計的元件， 以執行所需之特定功能。因此積體電路的性能，端視包含 其中元件之性能及可靠度。而對每一個元件而言，皆需要 有效的內部連線，以便交換元件間之電子訊號，特別是由 於上述構裝密度之持續上升，目前的積體電路有朝多重層 內連線結構發展之趨勢。因此往往需要在多重層間\形成:大 量的接觸孔（conduct hole)或介質孔（Via)，並形成如插塞 (plug)等內連線結構，以提供元件與多重層間連線之接觸 結構。 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 513771 經濟部中央標準局員工消費合作社印製 A7 B7 五、發明説明（） 在傳統製造內連線的相關技術中，常包括在半導體 底材上形成類似氧化物的介電層以產生隔離作用。然後， 再藉著傳統的微影製程技術，在介電層上形成接觸孔。並 且爲了達到縮小元件尺寸之要求，此接觸孔之維度往往要 做的比以前更小。然而在實磨利用相關技術與製程來形成 接觸孔時，經常會產生各式各樣之問題及困難。 請參照第一圖，該圖所顯示爲內連線製程中製造接 觸孔時，所遭遇之典型問題。其中一半導體底材100上具 有一金屬層110以及一介電層120，且該介電層120位於 該金屬層110之上表面。如同前述，爲了後續製造所需功 能之積體電路，往往需要在該介電層120上形成如第一圖 中之接觸孔125,以曝露出該金屬層110之上表面，並俾 利後續形成插塞於該接觸孔1 25中後，可達成所需傳送電 子訊號之功能。然而，實際上在進行相關的蝕刻程序時， 卻經常可能形成如圖中蝕刻未完全（under-etching)之接觸 孔130，並導致在進行後續形成插塞（plug)製程後，無法 有效導通而達成傳送電子訊號之目的。 此外，即使在進行接觸孔製程時，可有效的克服上 述之問題，然而在後續進行形成金屬插塞（Plugi之製程 時，仍需面臨諸多問題。請參照第二圖，該圖所顯示爲在 進行插塞製程時，所遭遇的典型問題。其中一半導體底材 本紙張尺度適用中國國家標準（CNS ) A4規格（210X29?公釐） (請先閲讀背面之注意事項再填寫本頁} 訂 513771 A7 B7 五、發明説明（） 200上具有一金屬層210以及一介電層220，該介電層220位 於該金屬層210之上表面，並且該介電層220上具有複數個 接觸孔。再進行相關之金屬插塞製程後，可形成圖中之金 屬插塞230，以提供所製造之積體電路良好的電子訊號傳 送路徑。然而，在實際製造過程中，卻經常會形成如圖中 未沉積完全之金屬插塞240，或是具有孔洞缺陷之金屬插 塞250，由此導致積體電路之性能大受影響。 經濟部中央標準局員工消費合作社印製 (請先閱讀背面之注意事項再填寫本頁) 是以如果可以方便有效的偵測出所製造之內連 線，如接觸孔或金屬插塞，其缺陷所在與產生原因，則可 有效的提昇對相關製程的控制能力，並可在進行後續製程 前進行修補程序，以提高所製造積體電路其性能及操作壽 命。在傳統技術中，可藉著使用光學顯微鏡（Optical Microscopy，〇M)以及電子顯微鏡（Scanning electron microscopy，SEM)來對半導體底材進行偵測，以判斷並定 位接觸孔以及插塞之缺陷位置與成因。但是隨著積體電路 尺寸的持續降低，位於接觸孔與插塞中極微細之裂縫 (seam)與空洞（void)往往無法有效的被偵測到，遑論加以 分析形成缺陷之原因。而藉著使用高能量之聚焦離子束 (Focus Ion Beam，FIB)雖能提商辨識率，然而高能量的離 子卻往往會破壞了該半導體底材之表面，造成觀察'上之因 發明目的及槪述： 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 513771 A7 B7 五、發明説明（） 本發明之目的在提供一種用以檢測半導體製程中 內連線結構其缺陷之方法。 本發明之再一目的在提供一種用以定義覆蓋金屬 層之介電層其接觸孔是否發生缺陷之方法。 本發明之又一目的在提供一種使用電鍍程序來形 成沉積物於介電層上缺陷處，以便進行觀測之方法。 本發明之另一目的在提供一種用以定義所製造插 塞其缺陷之方法。 經濟部中央標準局員工消費合作社印製 (請先閱讀背面之注意事項再填寫本頁) 本發明提供了 一種檢測半導體製程中內連線結構 其缺陷之方法。該方法可用來定義半導體底材上之接觸孔 是否具有缺陷，其中該半導體底材上具有一介電層，用以 覆蓋導體層，且該介電層上具有接觸孔。該方法之步驟首 先將該半導體底材放置於硫酸銅溶液中以進行電鍍程 序，其中該半導體底材電性耦合於一直流電源之負極，如 此一來，當該半導體底材上之接觸孔蝕刻完全時，位於接 觸孔底部之導體層可視爲進行電鍍程序之負極。接著，、·將 銅箔放置於該電鍍溶液中，且電性耦合於該直流電源之正 極。在進行電鍍程序後，可觀測該導體層表面所形成之電 鎪沉積物，如果該接觸孔中形成電鍍沉積物，則顯示該接 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公餐） 543771- 經濟部中央標準局員工消費合作社印製 A7 B7 五、發明説明（） 觸孔爲完全触刻，是以曝露出該導體層之上表面，由此可 判斷該接觸孔是否具有缺陷。 此外，上述之測試方法亦可用於檢測半導體底材上 所形成之金屬插塞是否具有缺陷。其中該半導體底材上具 有一介電層用以覆蓋導體層，而金屬插塞則位於介電層 上，該方法至少包括下列步驟。首先，放置該半導體底材 於電鍍溶液中，且電耦合於一直流.電源之負極。接著，放 置導電金屬於該電鍍溶液中，且電耦合於該直流電源之正 極。然後，觀測該半導體底材上所形成之電鍍沉積物，以 判斷該金屬插塞是否具有缺陷，其中當該金屬插塞內有空 澗、裂縫、開口等等缺陷時，皆會形成電鍍沉積物以充塡 該缺陷。由此藉著觀察該金屬插塞內之電鍍沉積物，可知 道其缺陷所在，並俾利後續進行缺陷分析。 圖式簡單說明： 藉由以下詳細之描述結合所附圖示，將可輕易的了 解上述內容及此項發明之諸多優點，其中： 第一圖爲半導體晶片之截面圖，顯示在傳繞技術中 發生於介電層上接觸孔之缺陷； 第二圖爲半導體晶片之截面圖，顯示在傳統技術中 在製造金屬插塞時常見之缺陷； 本紙張尺度適用中國國家標隼（CNS ) A4規格（210X297公釐） ---τ----礞i—— (請先閱讀背面之注意事項再填寫本頁) 訂 經濟部中央操準局員工消費合作社印製 A7 B7 五、發明説明（） 第三圖爲半導體晶片之截面圖，顯示使用本發明所 提供之方法對接觸孔進行電鍍程序之結果； 第四圖爲進行電鍍程序之電鍍溶液，用以在半導體 晶片之表面形成金屬沉積物； 第五圖爲半導體晶片之截面圖，顯示使用本發明所 提之方法對金屬插塞進行電鍍程序之結果；以及 第六圖爲進行電鍍程序之電鍍溶液，用以在半導體 晶片上形成金屬沉積沟。 發明詳細說明： 本發明提供一個新方法用以檢測半導體製程中內 連線結構之缺陷。藉著利用適當的電鍍溶液，對半導體底 材進行電鍍程序，除了可以用來檢測半導體底材上之接觸 孔是否有效貫穿並導通導體層外，更可用來檢測所製造之 金屬插塞是否具有如空洞、裂縫等缺陷，以利後續製程之 進行。有關本發明之詳細說明如下所述。 根據本發明所提供之一實施例中，可對如第三圖所 示之半導體底材300進行檢測異常接觸孔（conduct hole; via hole)之程序。其中在一較佳實施例中，該半導'體底材 300可爲一具<100>晶向之單晶矽底材。此外如同前述，在 該半導體底材300上可形成各式各樣之元件與結構，以滿 足所需之功能。値得注意的是由於本發明之重點僅在於如 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公董） (請先閲讀背面之注意事項再填寫本頁)513771 A7 ____B7___ V. Description of the invention () Field of invention: (Please read the notes on the back before filling this page) The present invention relates to a semiconductor process, especially a method for detecting defects in the interconnects in the semiconductor process . Background of the Invention: '' With the continuous development of very large scale integrated circuit (VLSI) technology, as the area of integrated circuits is shrinking, the size of manufactured semiconductor components such as memory cells has also been greatly reduced, which has also led to chip structure. The packing density has a tendency to continue to increase. And by reducing the size of industrial components, semiconductor ICs with high integration density are also completed. However, there are also many challenges in the manufacture of such ICs. Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs With the continuous increase of the above-mentioned chip accumulation, modern integrated circuits often need to connect millions of components on a limited chip area to perform the required specific Features. Therefore, the performance of the integrated circuit depends on the performance and reliability of the components. For each component, an effective internal connection is required in order to exchange electronic signals between the components. Especially due to the continuous increase of the above-mentioned structure density, the current integrated circuit has developed towards a multi-layer interconnection structure. trend. Therefore, it is often necessary to form between multiple layers: a large number of contact holes or vias, and form interconnect structures such as plugs to provide a contact structure between the components and multiple layers. This paper size applies to China National Standard (CNS) A4 (210X297 mm) 513771 Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs A7 B7 V. Description of Invention () In the related technology of traditional manufacturing interconnection, it is often included in An oxide-like dielectric layer is formed on the semiconductor substrate to provide isolation. Then, a contact hole is formed in the dielectric layer by a conventional lithography process technology. And in order to meet the requirement of reducing the component size, the dimension of this contact hole is often made smaller than before. However, in the actual grinding, when using related technologies and processes to form contact holes, various problems and difficulties often arise. Please refer to the first figure, which shows a typical problem encountered when manufacturing contact holes in an interconnect process. One of the semiconductor substrates 100 has a metal layer 110 and a dielectric layer 120, and the dielectric layer 120 is located on the upper surface of the metal layer 110. As mentioned above, in order to subsequently manufacture integrated circuits with required functions, it is often necessary to form a contact hole 125 in the dielectric layer 120 as shown in the first figure to expose the upper surface of the metal layer 110 and facilitate subsequent formation. After plugging in the contact hole 125, the function of transmitting electronic signals can be achieved. However, in fact, during the related etching process, it is often possible to form an under-etching contact hole 130 as shown in the figure, and it may not be able to conduct effectively after the subsequent plug process is performed. To achieve the purpose of transmitting electronic signals. In addition, even when the contact hole process is performed, the above problems can be effectively overcome, but in the subsequent process of forming a metal plug (Plugi process, there are still many problems to be faced. Please refer to the second figure, which is shown in the figure Typical problems encountered during the plug process. One of the semiconductor substrates is sized to the Chinese National Standard (CNS) A4 (210X29? Mm). (Please read the precautions on the back before filling out this page.} Order 513771 A7 B7 5. Description of the invention () 200 has a metal layer 210 and a dielectric layer 220, the dielectric layer 220 is located on the upper surface of the metal layer 210, and the dielectric layer 220 has a plurality of contact holes. After the related metal plug manufacturing process is performed, the metal plug 230 in the figure can be formed to provide a good electronic signal transmission path for the manufactured integrated circuit. However, in the actual manufacturing process, it is often formed as shown in the figure. Completely deposited metal plug 240, or metal plug 250 with hole defects, which greatly affects the performance of the integrated circuit. It is printed by the company (please read the precautions on the back before filling in this page). It is effective if it can easily and effectively detect the manufactured interconnects, such as contact holes or metal plugs, and their defects and causes. It can improve the control ability of related processes, and can carry out repair procedures before the subsequent processes to improve the performance and operating life of the manufactured integrated circuit. In the traditional technology, an optical microscope (Optical Microscopy, 0M) can be used. ) And electron microscope (Scanning electron microscopy (SEM)) to detect semiconductor substrates to determine and locate the defect locations and causes of contact holes and plugs. However, as the size of integrated circuits continues to decrease, Very fine seams and voids in plugs are often not effectively detected, let alone analyze the cause of the formation of defects. By using a high-energy Focus Ion Beam (FIB), though Can improve the recognition rate, but high-energy ions often damage the surface of the semiconductor substrate, resulting in the observation of the purpose of the invention and Description: This paper size is in accordance with Chinese National Standard (CNS) A4 (210X297 mm) 513771 A7 B7 5. Description of the invention () The purpose of the present invention is to provide a method for detecting defects in the interconnect structure in the semiconductor manufacturing process. Another object of the present invention is to provide a method for defining whether a defect occurs in a contact hole of a dielectric layer covering a metal layer. Another object of the present invention is to provide a method for forming a deposit on a dielectric layer by using a plating process. To facilitate observation. Another object of the present invention is to provide a method for defining the defects of the manufactured plug. Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs (please read the precautions on the back before filling in this (Page) The present invention provides a method for detecting defects in an interconnect structure in a semiconductor process. The method can be used to define whether a contact hole on a semiconductor substrate has a defect, wherein the semiconductor substrate has a dielectric layer for covering the conductor layer, and the dielectric layer has a contact hole. In the method, the semiconductor substrate is first placed in a copper sulfate solution to perform an electroplating process. The semiconductor substrate is electrically coupled to a negative electrode of a DC power source. As a result, when a contact hole on the semiconductor substrate is etched When complete, the conductor layer at the bottom of the contact hole can be considered as the negative electrode for the plating process. Then, the copper foil is placed in the plating solution and electrically coupled to the positive pole of the DC power source. After the electroplating process, the electrodeposition deposits formed on the surface of the conductor layer can be observed. If electroplated deposits are formed in the contact holes, it indicates that the size of the paper is applicable to the Chinese National Standard (CNS) A4 specification (210X297 meal) ) 543771- Printed by A7 B7, Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the invention () The contact hole is completely engraved to expose the upper surface of the conductor layer, so that it can be judged whether the contact hole has defects. In addition, the above test method can also be used to detect whether the metal plug formed on the semiconductor substrate has defects. The semiconductor substrate has a dielectric layer for covering the conductor layer, and the metal plug is located on the dielectric layer. The method includes at least the following steps. First, the semiconductor substrate is placed in a plating solution and is electrically coupled to a negative electrode of a DC power source. Next, a conductive metal is placed in the plating solution and is electrically coupled to the positive pole of the DC power source. Then, the plating deposits formed on the semiconductor substrate are observed to determine whether the metal plug has defects. When there are defects such as voids, cracks, openings, etc. in the metal plug, electroplating deposits are formed. To fill the defect. Therefore, by observing the plating deposits in the metal plug, it is possible to know the defects and facilitate subsequent defect analysis. Brief description of the drawings: The above-mentioned content and many advantages of this invention can be easily understood through the following detailed description combined with the attached drawings, where: The first figure is a cross-sectional view of a semiconductor wafer, shown in the winding technology Defects that occur in contact holes on the dielectric layer; The second figure is a cross-sectional view of a semiconductor wafer, which shows the defects commonly used in the manufacture of metal plugs in traditional technology; This paper size applies to China National Standard (CNS) A4 specifications ( 210X297 mm) --- τ ---- 礞 i—— (Please read the precautions on the back before filling this page) Order A7 B7 printed by the Consumer Cooperatives of the Central Directorate of the Ministry of Economic Affairs The third figure is a cross-sectional view of a semiconductor wafer, showing the results of a plating process on a contact hole using the method provided by the present invention; the fourth figure is a plating solution that performs a plating process to form a metal deposit on the surface of a semiconductor wafer; The fifth figure is a cross-sectional view of a semiconductor wafer, showing the results of a plating process on a metal plug using the method proposed by the present invention; A plating solution is used to form a metal deposition trench on a semiconductor wafer. Detailed description of the invention: The present invention provides a new method for detecting defects in interconnect structures in a semiconductor process. By using a suitable plating solution to perform the plating process on the semiconductor substrate, in addition to detecting whether the contact holes on the semiconductor substrate effectively penetrate and conduct the conductor layer, it can also be used to detect whether the manufactured metal plug has Defects such as voids and cracks facilitate subsequent processes. A detailed description of the present invention is as follows. According to an embodiment provided by the present invention, a procedure for detecting an abnormal contact hole (conduct hole; via hole) can be performed on the semiconductor substrate 300 as shown in the third figure. In a preferred embodiment, the semiconductor substrate 300 may be a single crystal silicon substrate with a crystal orientation of < 100 >. In addition, as mentioned above, various components and structures can be formed on the semiconductor substrate 300 to satisfy the required functions. It should be noted that the focus of the present invention is only if the paper size applies the Chinese National Standard (CNS) A4 specification (210X297 public director) (please read the precautions on the back before filling this page)
543774 A7 B7 五、發明説明（） 何快速有效的檢測出異常接觸孔，是以對於半導體底材 300上之各種元件及結構，在此不予詳加說明。仍請參照 第三圖，其中該半導體底材300上具有一可作爲內連線結 構之導體層310，並且在該導體層310之上具有一介電層 3 20。在一較佳實施例中，形成導體層3 10可藉由所熟知之 技術，如物理氣相沈積法（PVD)、濺鍍等類似製程在半導 體底材300上沈積適合之金屬材料而得，至於該導體層3 10 之材料則可選擇多晶矽、鋁、鈦、鎢、銅、金、鉑或合金 等等。至於在該導體層310之上則形成一產生絕緣作用之 介電層320,其中該介電層320在一較佳實施例中，可以爲 氧化矽或氮化矽，一般而言，使用化學氣相沈積法（CVD) 以四乙基矽酸鹽（TEOS)在溫度約600至800°C，壓力約0.1 至lOtorr間，可以形成氧化矽，或著，也可以利用熱氧化 的方式來形成氧化矽。至於氮化矽則可在大約400至450T 的爐中形成，製程中的反應氣體是SiH4，N2〇及NH3。至於 在該介電層320之上，則使用相關之微影與蝕刻製程形成 複數個接觸孔。如同上述，所形成之接觸孔可能如圖中蝕 刻完全之接觸孔330，也可能爲蝕刻未完全之接觸孔340。 經濟部中央標準局員工消費合作社印製 (請先閱讀背面之注意事項再填寫本頁) 爲了有效的檢測出介電層320上之異常接觸孔 (abnormal conduct hole)，可對該半導體底材300進‘·行電鍍 程序。請參照第四圖，在一較佳實施例中，可將該半導體 底材300放置於一電鍍溶液400內。其中，將該半導體底材 300連接於一直流電源（未顯示於圖中）之負極；接著將一導 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 5«m A7 B7 五、發明説明（） 電金屬410放置於該電鍍溶液400中，並連接於該直流電源 之正極。如此在進行電鍍程序時，位於該半導體底材300 上之導體層310可視爲進行電鍍程序之電極。至於該電鍍 溶液400可選擇合適之酸類、鹼類、以及鹽類來加以形成。 在一較佳實施例中，上述之電鍍溶液400可使用硫酸銅來 加以調配；而所使用之導電金屬410則可選擇銅箔（Cu)材 料，在直流電壓大約爲0〜20伏特的環境下，進行電鍍程序 約5〜30秒。 經濟部中央標準局員工消費合作社印製 (請先閲讀背**之注意事項再填寫本頁) 然後，觀測該半導體底材300之電鍍情況。其中値 得注意的是對介電層320上正常之接觸孔而言，由於其所 曝露之導體層310上表面，可有效的形成金屬沉積物，是 以在進行電鍍程序後，在接觸孔330中會形成如第三圖中 之金屬沉積物350。相對的，對触刻未完全（under-etching) 之接觸孔而言，由於其並未曝露導體層310之表面，是以 在進行電鍍程序時，在該接觸孔310中並不會形成任何之 金屬沉積物。如此一來，藉著觀察所形成之接觸孔，在進 行電鍍程序後 < 正否具有金屬沉積物，即可判斷所形成之 接觸孔是否可有效的貫穿介電層320,且曝露出導體層310 之表面。如同上述，在一較佳實施例中，由於所使用之電 鍍溶液400爲硫酸銅溶液，是以在接觸孔330中所形成爲銅 原子之金屬沉積物350。如此即便祇使用光學顯微鏡 (OM)，皆可很輕易的檢測出異常之接觸孔，以便於後續 進行補救之程序。 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） A7543774 A7 B7 V. Explanation of the invention () How to detect abnormal contact holes quickly and effectively is to explain the various components and structures on the semiconductor substrate 300, which will not be described in detail here. Still referring to the third figure, the semiconductor substrate 300 has a conductive layer 310 that can be used as an interconnect structure, and a dielectric layer 3 20 on the conductive layer 310. In a preferred embodiment, the formation of the conductive layer 3 10 can be obtained by depositing a suitable metal material on the semiconductor substrate 300 by a well-known technique, such as physical vapor deposition (PVD), sputtering, or the like. As for the material of the conductor layer 3 10, polycrystalline silicon, aluminum, titanium, tungsten, copper, gold, platinum, or alloy can be selected. As for forming a dielectric layer 320 that produces an insulating effect on the conductive layer 310, the dielectric layer 320 may be silicon oxide or silicon nitride in a preferred embodiment. Generally, chemical gas is used. Phase deposition (CVD) uses tetraethyl silicate (TEOS) to form silicon oxide at a temperature of about 600 to 800 ° C and a pressure of about 0.1 to 10 Torr, or it can be formed by thermal oxidation. Silicon. As for silicon nitride, it can be formed in a furnace of about 400 to 450T, and the reaction gases in the process are SiH4, N2O and NH3. As for the dielectric layer 320, a plurality of contact holes are formed using a related lithography and etching process. As described above, the formed contact hole may be the contact hole 330 that is completely etched as shown in the figure, or the contact hole 340 that is not completely etched. Printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs (please read the precautions on the back before filling this page). In order to effectively detect abnormal conduct holes in the dielectric layer 320, the semiconductor substrate 300 can be tested. Go to the ·· plating process. Referring to the fourth figure, in a preferred embodiment, the semiconductor substrate 300 can be placed in a plating solution 400. Among them, the semiconductor substrate 300 is connected to the negative electrode of a direct current power supply (not shown in the figure); then a paper size of this guide is applied to the Chinese National Standard (CNS) A4 specification (210X297 mm) 5 «m A7 B7 5 Explanation of the invention () The electric metal 410 is placed in the plating solution 400 and connected to the positive electrode of the DC power source. Thus, when the plating process is performed, the conductive layer 310 on the semiconductor substrate 300 can be regarded as an electrode for the plating process. As for the plating solution 400, suitable acids, bases, and salts can be selected to be formed. In a preferred embodiment, the above electroplating solution 400 can be prepared by using copper sulfate; and the conductive metal 410 used can be selected from copper foil (Cu) material under an environment where the DC voltage is about 0-20 volts , The plating process is performed for about 5 to 30 seconds. Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs (please read the precautions on the back of the page before filling out this page), and then observe the plating of the semiconductor substrate 300. It should be noted that, for the normal contact holes on the dielectric layer 320, due to the exposed upper surface of the conductor layer 310, metal deposits can be effectively formed. Therefore, after the plating process is performed, the contact holes 330 are formed. A metal deposit 350 is formed as shown in the third figure. In contrast, for an under-etching contact hole, since the surface of the conductor layer 310 is not exposed, no electro-mechanical layer is formed in the contact hole 310 during the plating process. Metal deposits. In this way, by observing the formed contact holes, after performing the plating process < whether there are metal deposits, it can be judged whether the formed contact holes can effectively penetrate the dielectric layer 320 and expose the conductive layer 310 The surface. As described above, in a preferred embodiment, since the electroplating solution 400 used is a copper sulfate solution, the metal deposit 350 formed as a copper atom in the contact hole 330 is used. In this way, even if only using an optical microscope (OM), abnormal contact holes can be easily detected to facilitate subsequent remedial procedures. This paper size applies to China National Standard (CNS) A4 (210X297 mm) A7
經濟部中央標準局員工消費合作社印製 接著請參照第五圖，該圖所顯示爲本發明所提供之 另一實施例。其中如同前述，提供一具<1〇〇>晶向之單晶 矽底材作爲半導體底材500。此外如同前述，在該半導體 底材500上具有一可作爲內連線結構之導體層5 1 0，並且在 該導體層510之上具有一作爲絕緣之用的介電層5 20。至於 在該介電層520之上，則使用相關之微影與蝕刻製程形成 複數個接觸孔，隨後並使用相關技術沉積金屬於該複數個 接觸孔中，再經由適當的回蝕程序或化學機械硏磨程序， 形成複數個金屬插塞。如同前述，所形成之金屬插塞可能 如第五圖中正常之金屬插塞5 30，亦可能爲未沉積完全之 金屬插塞540,或是具有孔洞缺陷之金屬插塞550。 然後，爲了有效的檢測出異常金屬插塞（abnormal plug)，可對該半導體底材500進行電鍍程序。請參照第六 圖，在一較佳實施例中，可將該半導體底材500放置於一 電鍍溶液600內。其中，將該半導體底材500連接於一直流 電源（未顯示於圖中）之負極；接著將一導電金屬610放置於 該電鍍溶液600中，並連接於該直流電源之正極。如此在 進行電鍍程序時，位於該半導體底材500上之導體層510 可視爲進行電鍍程序之電極。至於該電鍍溶液600可選擇 .* 合適之酸類、鹼類、以及鹽類來加以形成。在一較佳實施 例中，上述之電鍍溶液600可使用硫酸銅來加以調配；而所 使用之導電金屬610則可選擇銅箔（Cu)材料，在直流電壓 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） (請先閲讀背面之注意事項再填寫本頁) C· 513771 A7 B7 五、發明説明（ 大約爲0〜20伏特的環境下，進行電鍍程序約5〜30秒 (請先閱讀背面之注意事項再填寫本頁 然後，觀測該半導體底材500之電鍍情況。其中由 於所形成之金屬插塞皆可視爲進行電鍍程序之電極，是以 於進行電鍍程序後，在所製造之金屬插塞的上表面，會形 成如第五圖中之金屬沉積物560。値得注意的是如第五圖 中之金屬插塞550其中之孔洞亦會被金屬沉積物560所塡 滿。同理如未沉積完全而具有開口之金屬插塞540，其開 口亦會被金屬沉積物560所塡充。如同上述，在一較佳實 施例中，由於所使用之電鍍溶液600爲硫酸銅溶液，是以 所形成之金屬沉積物560爲銅原子沉積物。如此一來，藉 著觀察金屬插塞內是否具有銅原子沉積物，即可判斷所形 成之金屬插塞是否具有孔洞（voids)、裂縫（seams)等缺陷。 例如當所形成之金屬插塞爲鎢插塞（Tungsten plug)時，由 於鎢插塞之顏色較暗，而銅沉積物之顏色較亮，是以在使 用光學顯微鏡（0M)或電子顯微鏡（SEM)進行觀察時，可以 很輕易的檢測出異常之鎢插塞，並判斷出其造成異常之原 因。 經濟部中央標準局員工消費合作社印¾ 本發明具有極多的優點，例如藉著對該半導體底材 進行電鑛程序，除了可直接由所形成之電鍍沉積g來判斷 接觸孔或金屬插塞是否具有缺陷外；更可藉著觀察電鍍沉 積物，硏判產生缺陷之原因爲何，是以對後續進行相關製 程可產生極大之俾益。例如在金屬插塞上形成電鍍沉積 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公;^ )Printed by the Staff Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs Please refer to the fifth figure, which shows another embodiment provided by the present invention. Among them, as described above, a single crystal silicon substrate with < 100 > crystal orientation is provided as the semiconductor substrate 500. In addition, as described above, the semiconductor substrate 500 has a conductive layer 5 1 0 which can be used as an interconnect structure, and a dielectric layer 5 20 is provided on the conductive layer 510 for insulation. As for the dielectric layer 520, a plurality of contact holes are formed by using a related lithography and etching process, and then a related technology is used to deposit metal in the plurality of contact holes, and then an appropriate etch-back process or chemical machinery is used. Honing process to form a plurality of metal plugs. As mentioned above, the formed metal plug may be the normal metal plug 5 30 in the fifth figure, or the metal plug 540 that is not completely deposited, or the metal plug 550 with hole defects. Then, in order to effectively detect an abnormal metal plug, a plating process may be performed on the semiconductor substrate 500. Referring to FIG. 6, in a preferred embodiment, the semiconductor substrate 500 can be placed in a plating solution 600. The semiconductor substrate 500 is connected to a negative electrode of a direct current power source (not shown in the figure); then, a conductive metal 610 is placed in the plating solution 600 and connected to a positive electrode of the direct current power source. Thus, when the plating process is performed, the conductive layer 510 on the semiconductor substrate 500 can be regarded as an electrode for the plating process. As for the plating solution 600, suitable acids, bases, and salts can be selected to form. In a preferred embodiment, the above-mentioned plating solution 600 can be prepared by using copper sulfate; and the conductive metal 610 used can be selected from copper foil (Cu) material, and the Chinese national standard (CNS) ) A4 size (210X297 mm) (Please read the precautions on the back before filling out this page) C. 513771 A7 B7 V. Description of the invention (approximately 5 to 30 seconds in an environment of approximately 0 to 20 volts ( Please read the precautions on the back before filling in this page, and then observe the plating of the semiconductor substrate 500. The metal plugs formed can be regarded as electrodes for the plating process, so after the plating process, The upper surface of the manufactured metal plug will form a metal deposit 560 as shown in the fifth figure. It should be noted that the holes in the metal plug 550 as shown in the fifth figure will also be filled with the metal deposit 560. Similarly, if the metal plug 540 with an opening is not completely deposited, its opening will also be filled with the metal deposit 560. As mentioned above, in a preferred embodiment, since the plating solution 60 is used, 0 is a copper sulfate solution, and the formed metal deposit 560 is a copper atomic deposit. In this way, by observing whether there is a copper atomic deposit in the metal plug, it can be judged whether the formed metal plug has Defects such as voids and seams. For example, when the formed metal plug is a tungsten plug, the color of the tungsten plug is darker, and the color of the copper deposit is brighter. When using an optical microscope (0M) or an electron microscope (SEM) for observation, the abnormal tungsten plug can be easily detected and the cause of the abnormality can be determined. Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economics ¾ The present invention It has many advantages. For example, by performing an electric ore process on the semiconductor substrate, in addition to directly determining whether the contact hole or metal plug has defects by the electroplated deposition g formed, it can also observe the electroplated deposits. What is the reason for the defect? It is of great benefit to the subsequent related processes. For example, the formation of electroplated deposits on metal plugs National Standard (CNS) A4 specification (210X 297 male; ^)
51377X ΑΊ ____Β7 五、發明説明（） 物，不但可用以判斷產生空洞、裂縫或開口之位置，特別 是再進行聚焦離子束（FIB)偵測時，由於所產生之電鍍沉 積物（如第五圖中之5 60)可作爲該半導體底材500之遮蓋 層（cap layer)，是以可降低高能量的離子束對半導體底材 表面所造成之損壞，而俾利於後續進行分析程序。另外， 由於銅原子沉積物之顏色較鎢插塞之顏色光亮，是以在進 行缺陷判斷時，即使使用光學顯微鏡（OM)，亦可快速的 找到缺陷並分析其所形成之原因。 本發明雖以一較佳實例闡明如上，然其並非用以限 定本發明精神與發明實體，僅止於此一實施例爾。對熟悉 此領域技藝者，在不脫離本發明之精神與範圍內所作之修 改，均應包含在下述之申請專利範圍內。 (請先閱讀背面之注意事項再填寫本頁) 經濟部中央標準局負工消费合作社印¾ 本纸張尺度適用中國國家標準·（ CNS ) Λ4規格（210 X 297公楚）51377X ΑΊ ____ Β7 V. Description of the invention () The object can not only be used to determine the location of voids, cracks or openings, especially when the focused ion beam (FIB) detection is performed again, due to the plating deposits (such as the fifth figure) 5 of 60) can be used as the cap layer of the semiconductor substrate 500, which can reduce the damage to the surface of the semiconductor substrate caused by a high-energy ion beam, which is conducive to subsequent analysis procedures. In addition, because the color of copper atomic deposits is brighter than that of tungsten plugs, even when using an optical microscope (OM) to determine defects, you can quickly find the defects and analyze the cause of their formation. Although the present invention is explained as above with a preferred example, it is not intended to limit the spirit and the inventive entity of the present invention, but only to this embodiment. Modifications made by those skilled in the art without departing from the spirit and scope of the present invention should be included in the scope of patent application described below. (Please read the notes on the back before filling out this page) Printed by the Consumers' Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs ¾ This paper size applies to Chinese National Standards · (CNS) Λ4 specifications (210 X 297)