TW512441B - Silicon-germanium mesa transistor - Google Patents

Abstract

A method in the fabrication of a silicon-germanium mesa transistor in a semiconductor process flow comprises the steps of providing a p-type doped silicon bulk substrate (10) having an n<SP>+</SP>-type doped surface region (31) being a subcollector; depositing epitaxially thereon a silicon layer (41) comprising n-type dopant; depositing epitaxially thereon a silicon layer (174) comprising germanium and p-type dopant; forming in the epitaxial layers (41, 174) field isolation areas (81) around, in a horizontal plane, a portion of the epitaxial layers (41, 174) to simultaneously define an n-type doped collector region (41) on the subcollector (31); a p-type doped base region (174) thereon; and an n-type doped collector plug on the subcollector (31), but separated from the n-type doped collector region (41) and the p-type doped base region (174); and forming in the p-type doped base region (174) an n-type doped emitter region.

Description

512441 A7 B7 V. Description of the Invention (1) Technical Field of the Invention The present invention relates generally to the field of silicon IC technology, and more specifically, the present invention relates to the formation of a SiGe high-power transistor crystal in a semiconductor manufacturing process, which is specially designed Give bipolar RF-1C; about the formed SiGe high-stage power crystal; and about the integrated circuit containing this SiGe high-stage power crystal. Description of the Related Art and Background of the Invention Today's advanced silicon bipolar, CMOS or BiCMOS circuits have been used for high-speed applications in the 1-5 GHz frequency range, and they have replaced circuits that previously could only be implemented using III-V-based technologies . Its main application lies in the latest telecommunications systems. This circuit is mostly used for analog functions, such as switching current and voltage, and for high-frequency wireless functions, such as mixing, amplification, and detection functions. To obtain a transistor that is well-suited for applications such as telecommunications, it requires not only a low transition time (high fT), but also a high maximum oscillation frequency (fmax), and good linear behavior. Current silicon bipolar function transistor (BJT) technology can provide fT up to 50 GHz but has reached its physical limit due to the counterbalance between the thickness of the base layer and the impedance. By adding some germanium (basically 10-20%) to the positivity of a conventional BJT, this high frequency characteristic can be substantially improved. The new device has a SiGe (silicon-germanium) HBT (heterojunction bipolar transistor) structure. The base layer structure is usually grown by MBE (Molecular Beam Epitaxial) or CVD (Chemical Vapor Deposition), but it is possible to implant germanium into the silicon but less control the doping profile. In recent years, SiGe-based transistors have shown recording high-frequency performance regarding fT and fmax (maximum oscillation frequency), see π reinforced SiGe -4 with a fmax of 160 GHz-This paper is in accordance with Chinese national standards (CNS ) A4 specification (210X 297 mm) 512441 A7 B7 V. Description of the invention (2) "Enhanced SiGe Heterojunction Bipolar Transistors with 160 GHz-fmax", by A. Schappen et al. References, IEEE IEDM Tech Dig., P. 743, 1995. For high frequency applications, such as wireless communications, this SiGe HBT can be used to enhance the performance of existing dual-repeated silicon RF-1C and BiCMOS technologies. A large review The thesis of SiGe epitaxial basic technology is "Si-Ge german HBT technology: a new competitor for Si-based RF and microwave circuit applications" ("SiGe HBT Technology: A New Contender for Si-Based RF and Microwave Circuit Applications"), Proposed by JD Cressler, IEEE TED-46, page 572, May 1998.

SiGe can be added to the existing IC process flow in different ways. Some typical examples of SiGe-based transistors to expand the BiCMOS process can be found in "BiCMOS6G: High-performance 0.35 μιη SiGe BiCMOS technology for wireless applications" (&quot; BiCMOS6G ·· A high performance 0.35 μιη SiGe BiCMOS technology for wireless applications ") Proposed by A. Monroy et al., IEEE BCTM 1999, p. 121, and "0.24 μm SiGe BiCMOS mixed-signal RF production technology is characterized by 47 GHz Ft HBT and 0.18 μm Leff CMOS" (, A 0 · 24 μm SiGe BiCMOS "Mixed-Signal RF Production Technology Featuring a 47 GHz Ft HBT and 0.18 μm Leff CMOS", proposed by SA St. Onge et al., IEEE BCTM99, p. 117, 1999. There is another simpler but practical method for manufacturing high performance The SiGe HBT transistor is epitaxially deposited using the device layer, and then the device structure is formed by etching from a high-level transistor, which is similar to the manufacture of a compound semiconductor device (for example, this paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm)

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512441 A7 B7 V. Description of the invention (3)

GaAlAs HBT). This high-level structure has been widely used to quickly verify concepts and characteristics of detection devices because of its simplicity and ease of manufacturing. See nSi / SiGe HBTs for low-power integrated circuits "(" Si / SiGe HBTs for Applications in Lower " Power ICsn)? Proposed by D. Behammer et al., Solid-State Electronics, Vol. 39, No. 4, p. 471, 1996 0 The circuit length of an IC form requires a more complex structure than some transistors. The aforementioned concept of a grandstand does not generally apply here. Examples of improved manufacturing methods, such as U.S. Patent 5,587,327 by U. Kdnig et al., And U.S. Patent 5,821,149 by A. Schttppen et al., Can avoid some disadvantages. However, there are still some key process steps, such as differential insect crystals (simultaneous crystal growth on the dream substrate opening and deposition of non-anamorphic materials on field effect areas and other structures), and critical removal The part of the emitter layer on the base region makes it difficult to apply the concept to high-volume semiconductor production. Therefore, a simpler method is needed to implement and integrate a high-level SiGe HBT transistor into a semiconductor process flow suitable for high-volume production. SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a method for integrating a SiGe transistor structure in the form of a high plateau into a conventional process flow, such as a silicon bipolar double repetitive silicon silicon process flow. Another object of the present invention is to provide such a method, wherein the epitaxial growth of the mesa layer is relatively simple and easy. Another object of the present invention is to provide such a method, which requires minimization of process steps. This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 512441 A7 B7 V. Description of the invention () For this purpose, the present invention includes a method for manufacturing a silicon in a semiconductor process according to the first aspect- The method of germanium high-level transistor, especially in the process flow of the bipolar integrated circuit designed for radio frequency applications, includes the following steps:-Providing a p-type doped silicon block substrate with an n + -type secondary collector region Used for high-level crystals in its surface;-depositing a fragmentary layer containing n-type dopants on the n + -type sub-collector region;-growing a fragmentary layer on the worm crystal, including Chu and ρ -Type impurities; device-forming a field isolation region in the epitaxial layer, preferably a shallow trench surrounding a horizontal plane, a part of the worm crystal layer, preferably by etching, at the same time Define an n-type doped collector region on the secondary collector; a p-type doped high- terrace base region on the collector region; and an n-type doped collector plug on the secondary collector, but with The n-type doped collector region and the p-type doped base region are isolated; - forming a crystal of the high-TPC η-type doped emitter region of the ρ-doped base regions.

The threads are preferably &apos; comprising the staggered and p-type inclusions provided in a multi-layered structure comprising a plurality of stacked layers. Some stacks may contain only the original stone eve. Carbon can be added to the broken layer containing germanium and the P-type dopant to retard the diffusion of the P-type dopant. This temperature budget will be kept to a minimum during the fabrication of the silicon-germanium high-stage transistor. Preferably, after a subsequent step of depositing a silicon layer containing germanium and a p-type dopant, which may be independent of an emitter activation and drive-in step, the temperature may be in accordance with the Chinese National Standard (CNS) A4 specification at this paper scale. (210 X 297 mm) 512441 A7 _B7 1. Description of the invention (5 "Keep below or about 800 ° C. This emitter activation and driving step can use a RTA (rapid thermal annealing) to a higher temperature It is performed at a temperature of 50 ° C. to electrically activate the dopants and to set the final doping profile of the emitter-base junction of the SiGe high-terrestrial crystal. Basically, the steps of activation and driving of the emitter are at It is performed at a high temperature, for example, at about 1050 ° C., but within a short time of about 5 to 20 seconds. Furthermore, the present invention includes a SiGe high-level power transistor manufactured according to the second aspect and according to the first aspect of the present invention. In addition, the invention includes a integrated circuit according to a third aspect, which includes at least one SiGe high-level transistor according to the second aspect of the invention. The base layer is deposited on a wafer by a planar silicon layer. Overlay, which provides a simpler Crystal growth requires less than the previous technology. Forming a surrounding field isolation region in a horizontal plane, a part of the epitaxial layer (base and η well), preferably by STI ( Shallow trench isolation) etching, while simultaneously defining the collector region; the high platform base region; and the collector plug of the SiOe high platform transistor. Preferably, the STI surname is performed to the next set Using the conventional RF-1C bipolar process flow with shallow trench isolation, the base SiGe crystal layer can be deposited directly after the collector ’s essential crystal layer. The etching of the shallow trench simultaneously forms the Nantai transistor. The structure does not require further additional steps. Further features and benefits of the present invention will be better understood by the following detailed description of the preferred embodiments of the present invention and the attached drawings i_4, -8 -This paper size is in accordance with the Chinese National Standard (CNS) A4 (210 X 297 mm) 512441 A7 B7 V. Description of the invention (6) It is for illustration only, and not a limitation of the present invention. 1-4 is a preferred embodiment according to the present invention A highly enlarged cross-sectional view of a part of a semiconductor structure during the manufacturing process of the embodiment. Reference number table 10 Substrate 11 Height p + doped wafer 12 Low-doped silicon layer 3 1 Embedded n-doped region 3 3 buried p-doped regions 4 1 Worm crystal fragment 42 Oxidation layer 43 Hard nitrided layer 7 1 Thin growth oxide and deposited oxide 72 Polycrystalline cut 8 1 Shallow trench oxide 111 Thermal oxide 141 Nitrogen Silicon layer 151 External base layer 152 Oxide layer 171 Secondary implanted collector 172 Base oxide 173 P-type base contact path 174 Epitaxial SiGe base layer

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Line-9- This paper size applies to Chinese National Standard (CNS) A4 (210 X 297 mm) 512441 A7 B7 V. Description of the invention (7) 181 Side wall gap 191 Emitter contact area 192 Collector contact area 200 Oxide 201 Nitride 202 Detailed description of the specific embodiment of the emitter A preferred method for manufacturing a SiGe high-level transistor is described below with reference to FIGS. 1-4. A substrate 10 including a highly P + doped wafer 11 is provided, on which a p-type low-doped silicon layer 12 is grown. In addition, the p-type wafer may be a uniform and low impurity p-type wafer (not shown). In the stack 12, the embedded n-type 31 and p-type 33 regions are formed, which (i) forms a thin protective layer of pulverized dioxide on the stack 12; (丨 丨) by lithography A mask is formed thereon to define the area of the Si Ge high-level transistor; (iii) the n-type doped region defined by the mask; (jv) remove the mask; (v) obtained by heat treatment (Vi) p-type doping the structure as needed; and (vii) exposing the upper surfaces of the regions 31 and 33. This region 31 is also referred to as a buried n + -type doped secondary collector. Then 'a epitaxial silicon layer 41, preferably 0 6_07 μm thick, grows on the surface', and its stack is doped in selected regions to obtain η 堑 and ρ-type regions (η wells And ρ well). The stack is preferably deposited using RP-CVD (reduced pressure chemical vapor deposition) using crushed formazan or two-gas sintering. In FIG. 1, the completed stack 41 is n-type doped. -10- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm)

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Now according to the process of the present invention, it will form the SiGe high Taipower, and continue to deposit another epitaxial layer 174.

Fragmented-stratified epitaxially deposited and doped with P in the most optimized version

Si / SiGe / Si contour. It contains multiple stacks as listed in Table 丨 for deposition. The base structure can use different methods uW /: &amp; to several products: RP — CVD, UHV · CVD or MBE. In each example, the φ-dioxane is called Zhuo Ning, and the basal multiple layer 174 is best grown in a deposition sequence or stroke. It will be understood that the base layer 174 may include less than or more than 5 4 layers with other thicknesses and compositions, as long as the multi-layer 174 mainly contains Chu and p-type dopants. The germanium and P Type dopants can be added during epitaxial growth, but one or both of them can be added alternately after epitaxial growth of a pure silicon layer. When RP-CVD is used, the stacks 41 and 174 can be grown in a deposition sequence using the same deposition equipment. In the remaining processes, it is basically necessary to maintain a strict temperature budget, that is, the combination of time and temperature, otherwise the sharp boron doping profile in the base will be widened by thermally activated diffusion, and The high-frequency characteristics (for example, fT) of the obtained SiGe high-power transistor will be deteriorated. Therefore, in all possible steps, the 'thermal oxidation' will be performed at a low range of temperatures commonly used in such process steps, preferably no higher than about 800 ° C. Table 1. The deposited layer of the base structure is used for deposition (Layer 1 is closest to the collector 'Layer 5 is the upper surface layer). In the table, Ai (A) represents individual stacks -11-This paper size applies Chinese National Standard (CNS) A4 specifications (210 χ 297 public directors) 512441 A7 _ B7 V: Description of the invention (9) ~ ^ ' The thickness' i-S i represents undoped (original) silicon, the percentage 値 represents the average germanium concentration (Si ^ xGex) in atomic percentage, and b represents the base doped with the boron concentration, and its unit is cm · 3. For the third layer, a gradient profile can be reached, and its germanium content changes from 12 to 0%, which changes from bottom to top. Stacking number material 1 200 A i-Si 2 400 A i-SiGe, 12% 3 250 A SiGe, 12-0%, β 5E18 4 250 A Si, B 5E18 5 400 A i-Si The electrode is widened, and carbon may be added to the base layer 174 during or after its epitaxial deposition. This supply will delay boron diffusion and maintain a narrow doping profile after heat treatment. For further details' on this, reference can be made to DE 19652423 (B. Heinemann, G. Lippert, and!!! Osten, 1998), which is incorporated herein by reference. The thickness of the $ layer 174 is shown as woo a in the example in Table 1. This must be taken into account in the subsequent lithography and doping steps. Therefore, the implantation energy and etch depth must be slightly increased compared to the conventional process, and the base layer 174 is not added at this point in the process. Reference is made here to Swedish Patent Application No. 0101567-6, which is hereby incorporated by reference. However, the thickness of the base layer 174 is small, so it is not necessary to change the implantation energy and the etching depth. In order to define the active areas in the stacks 41 and 174 and isolate these areas, that is, -12- this paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 public love)

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512441 A7 B7 V. Description of the invention (1 () ~) _ &quot; ~ Form a shallow trench. First, an oxide layer 42 is formed on the base layer 174, and a silicon nitride layer 43 is deposited thereon. The resulting structure is shown in Figure j. A hard mask is then formed by patterning and etching away the silicon nitride 4 3 and oxide 42 layers in the area where the trench is to be formed. The shallow trench is then defined using the remaining portions of the stacks 42 and 43 as a hard mask to etch the structure. At the same time, 'an n-type doped collector region (well 11) 41 above the sub-collector 31' is defined. A p-type doped base region 174 on which the SiGe Nantai transistor is located; An n-type doped collector plug 41 is disposed on the electrode 31, but is isolated from the n-type doped collector region 41 and the p-type doped base region 174 by the shallow trench. This shallow trench will be filled later with oxide 81 during the process flow, for example, refer to Figure 3. It will be understood that the shallow trench can be formed such that it extends vertically from the upper silicon surface, ie, the upper surface of the stack 174, and down to the secondary collector 3 (not shown in Figures 1-4) . Next, a deep trench is formed around the SiGe high-level transistor as an element isolation. However, deep trenches can be formed as needed. The deep trench is formed by the following steps: (i) forming a hard cover of the deep trench by a sinker-dioxide hard layer; and patterning and etching the fragmented oxide layer to define the opening of the deep trench; ( ii) etching the deep trench; (iii) removing the remaining portion of the oxide layer; (iv) growing a thin oxide over the structure; (v) filling the deep trench with the deposited oxide (the thin The growth oxide and the deposited oxide are collectively designated 71) and polycrystalline silicon 72; (vi) planarize the polycrystalline silicon as needed; and (vii) etch back the structure to remove all of the shallow trench area Polycrystalline silicon. The resulting structure is shown in FIG. 2. -13- This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 512441 A7 B7 V. Description of the invention () Next, the shallow trench is filled with oxide 8 1 and the nitrogen is removed A layer of compound 4 3 and an oxide 42, and the deposited oxide on the nitride layer 43. This isolation method is further described in International Patent Application No. WO 0120664, which is incorporated herein by reference. As a result, a thermal oxide is grown on the exposed silicon surface (a portion can be seen in oxide 111 in Fig. 3). For the formation of the SiGe high-level transistor, an n-type doped low-impedance path from the surface of the wafer to the sub-collector 31 is required. This path is formed by lithographic patterning after n-type doping to define a low impedance collector plug 4 1,174 from the upper surface of the structure down to the secondary collector 31. Details of this energy and dosage selection are discussed in WO 9853489, which is incorporated herein by reference. Please note that on the n-type doped collector plug 41, the remaining portion of the stack 1 74 obtained during the etching of the shallow trench (Fig. 2) can reach a net doping. Collector plugs are labeled 41,174 in FIG. The oxide layer existing on the collector plugs 41, 174 is removed. Then, a thin silicon nitride layer is deposited (the remainder is labeled 141 in FIG. 3), the purpose of which is to add to the insulating layer U1 $ deposited in the emitter / base region of the .SiGe high-level transistor. , Resulting in low parasitic capacitance of the base-collector interface; and serves as an anti-oxidation mask for the collector plugs 41,174. Next, after some conventional process steps for manufacturing a kSiGe Nantai transistor, it includes: (i) forming an emitter / base opening; (ii) forming an external base layer 151; (iii) forming an oxide layer 152; (iv) forming an emitter opening in the emitter / collector opening; (v) forming a primary implanted collector 171 as needed; (v0 forming a p-type base contact path 173; (νΗ) Shaped in the emitter opening

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512441 A7 _______B7 V. Description of the invention (12 ~) — '&quot; Formation of base oxide 1 72, for example by depositing a TEOS after short compression in an oxidizing environment of 800 π (usable here) A lower temperature budget); and (viii) forming nitride sidewall spacers 18m. In this last step, the thin silicon nitride layer 141 is removed, except that it contributes to the spacer wall 丨 8 丨 and below the external base layer 151. The resulting structure is shown in FIG. 3. The inter-wall spacer can be formed in a two-step process, in which the nitride 181 is first selectively transferred to the oxide in the emitter opening, and can be removed in the collector plug if necessary. Plug the exposed silicon (the remainder of the upper base). The emitter is protected by the oxide layer 182 during this etching. The remaining oxide 1 72 in the emitter opening is then removed. Then, an n-type doped polycrystalline silicon layer is formed and subsequently etched to define the contact regions 191 and 192 to the emitter and collector of the SiGe high-level transistor. Note that the oxide layer 152 above the p-type polycrystalline silicon layer 151 is removed, except under the emitter contact region 191. Next, a double layer 200,201 composed of an oxide and a nitride is deposited on the structure. The structure is then exposed to high temperatures to activate and drive the previously implanted dopants. In a preferred embodiment, the heat treatment is performed using a RTA (rapid thermal annealing) in nitrogen at about 1050 ° C for 5-20 seconds. The purpose of this annealing is to electrically activate the implanted species, and to set the final doping of the emitter-base junction of the SiGe high-level transistor crystal. Note that the previously deposited layers of silicon oxide 200 and silicon nitride 201 remain on the wafer. The purpose is to stop the implanted dopants from diffusing out to the surrounding environment during the heat treatment. -15- This paper size is in accordance with Chinese National Standard (CNS) A4 specification (210 X 297 mm) 512441 A7 _____ B7 V. Description of the invention (13) Please also note that this heat treatment is the high platform base in the process flow The only process after the deposition of the layer 174 is performed above a temperature of about 800i. The n-type dopant in the emitter contact 191 will penetrate into the base 174 by diffusion. And the emitter electrode 202 is formed. At the same time, the p-type dopant of the stack 151 will diffuse into the base contact path 173. The resulting structure is shown in FIG. 4. Finally, the structure is anisotropically etched, so an outer barrier wall is formed; the exposed silicon surface provides silicide as needed to reduce the resistance; and a protective layer and a metal layer are formed. Therefore, the process flow for manufacturing SiGe high-level transistor has some advantages. The key deposition of the epitaxial base layer (see Figure i) is to form a cover layer on the wafer with a flat top layer of silicon. Other known processes require selective epitaxial deposition with a small process margin (only on the exposed broken areas on the structure covered by the mask portion), which has high demand for the epitaxial growth, or differential Deposition (on silicon and oxide regions), where the growth parameters on different regions can be different. Because this step is combined with the STI etch, it does not require a separate elevated etch. At the same time, the high trench base 174 is etched to form the shallow trench, and the n-type doped collector region (n-well) and the n-type doped collector plug are defined. Etching the η + layer under the STI can completely isolate the last mesa structure. The proposed process flow can be easily integrated into an existing dual copy process flow. It is clear that the invention can be modified in different ways. These -16- This paper size applies to China National Standard (CNS) A4 size (210 X 297 mm) binding

512441 A7 B7 V. Description of the invention (14) Changes should not be regarded as departing from the scope of the present invention. All of these amendments will be understood by those skilled in the art to be included in the scope of the attached patent application.

-17- This paper size applies to China National Standard (CNS) A4 (21 × 297 mm)

Claims (1)

Chuan 441 A8 B8 C8 ------ D8____ "'Scope of Patent Application ^' 1 A method for manufacturing a silicon-germanium high-level power crystal in a semiconductor manufacturing process, especially designed for RF applications The manufacturing process of a bipolar integrated circuit is characterized by the following steps:-Providing a p-type doped silicon block substrate (10), which has an n + -type secondary collector region (31) as the south A primary collector of a Taipower crystal;-epitaxially deposited thereon a silicon layer containing n-type dopants (41);-epitaxially deposited thereon a silicon layer containing germanium and p-type dopants (174) -In the epitaxial layer (41, 174), a field isolation region (81) is formed on a horizontal plane and surrounds a part of the epitaxial layer (41, 174) to define the secondary An n-type doped collector region (41) of the high-terrestrial crystal on the collector (31); a p-type miscellaneous base region (174) on the collector region; An 11-type doped collector plug (41) above, but is isolated from the n-type doped collector region (41) and the p-type doped base region (174); and p-type doped base region ( 174) to form an n-type doped emitter region (202) of the high-terrestrial crystal. 2 · As in the method of the first patent application, wherein the field isolation region (81) is a shallow trench (STI), And forming the shallow trench (81), the n-type doped collector region (41), the p-type doped base region (174), and the n-type doped collector plug are formed by a single etching The steps are defined simultaneously. 3. The method according to item 2 of the scope of patent application, wherein the etching in the single etching step is performed at least down to the secondary collector (31) in a vertical direction. The method of the third item, wherein the germanium and p-type dopants are added to the silicon layer (174) in situ during the epitaxial deposition. -18- This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 512441 ABC D 6. Scope of patent application 5 · The method of the third scope of patent application, wherein the silicon layer (174) containing germanium and P-type dopants has a multi-layer structure. 6 The method of claim 5 in which the multi-layer structure includes at least one intrinsic silicon layer. For example, the method of claim 6 of the patent scope, wherein the multi-layer structure includes at least one fracture-different layer between two essential fragments. 8. The method of the scope of claim 1, which includes germanium and p-type dopants The silicon layer (174) of the impurity is deposited by any one of RP-CVD, UHV-CVD, and MBE technologies. 9 · The method according to item 8 of the patent application scope, which includes the silicon layer of an n-type dopant (41) and the silicon layer (174) containing germanium and p-type dopants are grown by RP-CVD using the same deposition equipment in a single deposition process. 1 0. The method of claim 1 in which carbon is added to the silicon layer (174) containing germanium and a p-type dopant to delay the diffusion of the p-type dopant. 1 1. The method according to item 1 of the scope of patent application, wherein the temperature during the manufacture of the silicon-staggered high-level Tai crystal is deposited independently of the emitter activation and drive-in during the deposition of the silicon layer containing germanium and p-type dopants (174) is then kept below or at about 80 CTC. 1 2 · The method according to item 11 of the scope of patent application, wherein the emitter activation and driving steps are performed using an RT A (rapid thermal annealing) to electrically activate the dopants and to set the SiGe The emitter-base interface of the high-stage transistor will eventually support the hybrid corridor. 1 3 · The method according to item 11 of the patent application range, wherein the steps of activating and driving the emitter are performed at a high temperature, but within a short time of about 5 to 20 seconds. -19- The size of this paper applies to China National Standard (CNS) A4 (210 X 297 mm) D8 VI. Application scope of patent 14. 15. 16. 17. If you apply for the method of item No. 丨, one of them is at a level A deep trench (72) is formed on the plane to surround the n-doped collector region (41); the mouth-doped base region (174); and the n-doped collector plug is used to isolate the silicon- Germanium high Tailing crystal. A kind of "chopped-wrong two transistors" is characterized by-a P-type doped silicon block substrate (10), which has a type sub-collector region (31) as a primary collector of the Nantai transistor;-in its A silicon layer (41) containing an n-type dopant is formed thereon;-a silicon layer (174) containing a p-type dopant is formed thereon;-in the epitaxial layer (4 1,174) A field isolation region (si) is formed on a horizontal plane, which surrounds one of the crystal layers (41,174), and is used to define an n-type of the high-level transistor on the sub-collector (31). Hetero-collector region (41); a p-type hetero-base region (174) on the collector region; and an n-type doped collector plug (41) on the secondary collector (31) , But is isolated from the n-type doped collector region (41) and the p-type doped base region (174); and-forming a high-terrestrial crystal in the p-type doped base region (174) An n-type doped emitter region (202). For example, the transistor in the 15th scope of the patent application, wherein the field isolation region (81) is a shallow trench (STI). For example, the transistor of item 16 in the scope of patent application, wherein the shallow trench (81) extends at least in a vertical direction down to the secondary collector (31). -20- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm)