JP2005251888A - Horizontal hetero-bipolar transistor and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a horizontal hetero-bipolar transistor which can perform a high speed operation with a small parasitic capacity or a parasitic resistor. <P>SOLUTION: An n<SP>-</SP>-type diffusion layer 4 is formed in an SOI layer on an SOI substrate, an unnecessary part is removed, and a collector region is formed. Then, after a p<SP>+</SP>-type diffusion layer is formed on the collector region, an SiGe or SiGeC layer 10 is grown only on the one-side wall of the collector region. Then, an n<SP>+</SP>-type polysilicon layer 11 is deposited, and etched back. Then, after an insulating film layer 13 is deposited, a collector electrode 14, a base electrode 15 and an emitter electrode 16 are formed. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

The present invention relates to a lateral heterobipolar transistor and a method of manufacturing the same, and more particularly to silicon / silicon germanium (Si _1-X Ge _x ) or silicon / silicon germanium formed on an insulating substrate such as SOI (Silicon on Insulator). · relates those using carbon the _{(Si 1-XY Ge X C} Y) heterostructures like.

  In general, it is said that by forming a CMOS or bipolar transistor on an SOI substrate, excellent characteristics such as a lower operating voltage, complete isolation between elements, and a small parasitic capacitance can be realized. In particular, in a transmission / reception unit of a communication device, crosstalk between an analog circuit and a digital circuit becomes a problem. By using an SOI substrate, it is possible to expect a significant reduction in crosstalk as compared with the conventional technology.

  In addition, a hetero bipolar transistor (HBT) using a heterostructure such as Si / SiGe has been put to practical use as an element that can operate in a high frequency range, which has been considered difficult by a technology using a conventional silicon process. By using a heterostructure in which the base band gap is smaller than the emitter band gap, the reverse impurity injection of carriers from the base to the emitter can be suppressed, so that the base impurity concentration is increased and the base resistance is increased. There is an advantage over the conventional silicon bipolar transistor, for example, it can be made smaller.

  Furthermore, in BiCMOS technology accompanying the recent system-on-chip requirement, it is required to form a CMOS and a bipolar transistor on the same chip.

  However, when the bipolar transistor is formed on the SOI substrate, it is necessary to increase the thickness of the SOI layer to some extent in the conventional vertical structure. On the other hand, for the CMOS, reducing the SOI layer reduces high-speed operation and leakage current. It is necessary to suppress.

  Therefore, if a bipolar transistor can be formed using a thin SOI layer, the process can be greatly simplified, and a lateral bipolar transistor is promising as a method for realizing it. There is a report that the use of a lateral structure is advantageous in terms of high-speed operation because of reduced parasitic resistance. Examples of such attempts have been reported in research and will be described with reference to the drawings (for example, see Non-Patent Document 1).

  FIG. 4 shows a conventional lateral bipolar transistor. In FIG. 4, 1000 is a silicon layer, 1001 is a BOX layer, 1002 is a collector, 1004 is an internal base, 1005 is an emitter, 1006 is an external base, and 1099 is an SOI layer. The lateral bipolar transistor is formed on an SOI substrate including a BOX layer 1001 made of a silicon oxide film and an SOI layer 1099 made of silicon. By using the SOI substrate, the parasitic capacitance of the substrate can be reduced. The thickness of the SOI layer 1099 is 0.1 μm. The internal base 1004 is doped P-type with boron, and is connected to two external bases 1006 that are further boron-doped. The emitter 1005 and the collector 1002 are formed in contact with the internal base 1004 in a direction perpendicular to a line connecting the two external bases 1006. The emitter 1005 is doped with arsenic to a high concentration and N-type. The collector is doped with arsenic in the N-type, but the portion near the base 1006 has a retrograde structure in which the concentration is lowered to increase the breakdown voltage and the concentration becomes higher as the distance increases. Also, the overall planar shape is a cross shape so that the parasitic capacitance between the electrodes is reduced. With such a lateral bipolar transistor, the maximum oscillation frequency fmax was 31 GHz.

FIG. 5 is a diagram showing a conventional method for manufacturing a lateral bipolar transistor. In FIG. 5, 1102 is a collector, 1104 is an internal base, 1105 is an emitter, 1106 is an external base, 1107 is an N ^- diffusion region, 1110 is a Si ₃ N ₄ mask, and 1111 is a TEOS mask.

First, as shown in FIG. 5A, after forming an N-type layer in which phosphorus is implanted in an SOI layer provided on an SOI substrate composed of a silicon layer and a BOX layer, and an oxide film and an SiN film thereon, Boron 1109 is implanted 4E15 cm ^{-2 through the} array type resist mask 1108 to form a P ⁺ diffusion region.

Next, as shown in FIG. 5B, an Si ₃ N ₄ mask 1110 is formed with an offset of about 0.2 μm from the end of the resist mask 1108 by etching the nitride film and performing side etching.

Next, as shown in FIG. 5C, after removing the resist mask 1108, a TEOS mask 1111 is formed so as to cross the Si ₃ N ₄ mask 1110, and the dose of boron is further locally increased. Implantation is performed at 1E14 cm ⁻² and an acceleration energy of 25 keV. Here, as shown in FIG. 5D, the width of the internal base is determined by the diffusion distance of the TEOS mask 1111 for the implanted boron.

Finally, as shown in FIG. 5E, after the mesa etching is performed on the emitter and collector portions, arsenic is implanted under the implantation conditions 1E15 cm ⁻² , 120 keV, 1E16 cm ⁻² , and 65 keV, respectively. Since silicon is amorphized by this implantation, it is recrystallized by RTA at 1050 ° C. for 20 sec and annealing at 850 ° C. for 60 min.

Through the steps as described above, a bipolar transistor having a small parasitic capacitance, a high fmax, and a high speed operation can be formed.
T.Shino et al, "A 31 GHz fmax Lateral BJT on SOI Using Self-Aligned External Base Formation Technology", IEEE International Electron Devices Meeting Technical Digest 1998 p953-956

  However, such a conventional example has the following problems.

  First, since the width of the internal base 1104 is determined by boron diffusion, it is difficult to obtain a desired impurity distribution. Further, since the boundaries of the emitter 1105 and the collector 1102 are also defined by diffusion, it is difficult to form a steep junction.

  Secondly, although the structure is such that the parasitic capacitance of the element is minimized, the material of the emitter 1105, the internal base 1104, and the collector 1102 is the same as that of the conventional silicon, and there is a limit to the operation speed. That is, if the impurity concentration of the internal base 1104 is increased to lower the base resistance, holes are back-injected from the internal base 1104 to the emitter 1105 side to lower the gain, while reducing the impurity concentration increases the parasitic resistance of the base. There is a problem that the operation speed is lowered.

  In view of the above problems, an object of the present invention is to provide a lateral heterobipolar transistor that can operate at high speed with small parasitic capacitance and parasitic resistance.

  In order to achieve the above object, a lateral heterobipolar transistor according to the present invention includes a first semiconductor layer of a first conductivity type serving as a collector region formed in an island shape on an insulating layer provided on a substrate, A diffusion layer of a second conductivity type which is an external base formed on one side of the surface of one semiconductor layer, and a second conductivity type second layer which is an internal base formed on the side of the first semiconductor layer on one side. A semiconductor layer; a protective film formed on the first semiconductor layer and the second semiconductor layer; and a third semiconductor of the first conductivity type serving as a collector formed on the sidewall of the first semiconductor layer. And a fourth semiconductor layer of the first conductivity type serving as an emitter formed on the sidewall of the second semiconductor layer.

  According to the above configuration, high speed operation can be realized by arranging each electrode in the lateral direction on the SOI substrate to reduce the parasitic capacitance.

  In the lateral heterobipolar transistor, the second semiconductor layer is made of a mixed crystal of silicon and germanium or a mixed crystal of silicon and germanium containing carbon, and the third semiconductor layer and the fourth semiconductor layer are made of polycrystalline silicon. It is characterized by becoming.

  According to the above configuration, by forming a heterojunction using SiGe or SiGeC as the internal base, the reverse injection of carriers from the base to the emitter is suppressed to increase the current amplification factor, and the impurity concentration of the internal base To increase the base resistance.

  The method of manufacturing a lateral heterobipolar transistor according to the present invention includes a step of forming a first semiconductor layer of a first conductivity type formed in an island shape on an insulating layer provided on a substrate and serving as a collector region; A step of selectively forming a diffusion layer of a second conductivity type serving as an external base on one side of the surface of the first semiconductor layer, a step of selectively etching the side wall of the first semiconductor layer on one side, and etching A step of selectively forming a second semiconductor layer of the second conductivity type serving as an internal base on the sidewall of the first semiconductor layer; and a step of forming on the sidewall of the first semiconductor layer and the second semiconductor layer. And a step of forming a third semiconductor layer and a fourth semiconductor layer of the first conductivity type, each of which serves as a collector and an emitter.

  According to the above configuration, high speed operation can be realized by arranging each electrode in the lateral direction on the SOI substrate to reduce the parasitic capacitance.

  In the method for manufacturing a lateral heterobipolar transistor, the step of forming the first semiconductor layer includes a step of forming a protective film on the first semiconductor layer, and the third semiconductor layer, the fourth semiconductor layer, Forming a fifth semiconductor layer of the first conductivity type so as to cover the convex portion composed of the protective film, the first semiconductor layer, and the second semiconductor layer, and then forming the fifth semiconductor layer on the convex portion. A step of selectively removing the fifth semiconductor layer; and a resist layer formed in each of the first region including the sidewall of the first semiconductor layer and the second region including the sidewall of the second semiconductor layer; And a step of etching the fifth semiconductor layer using the protective film as a mask.

  According to the above configuration, the collector and the emitter can be formed in a self-aligned manner on the basis of the collector region first patterned on the SOI substrate, so that it is not necessary to provide a margin for mask alignment, thereby reducing the element area. be able to.

  In the above method for manufacturing a lateral heterobipolar transistor, the step of forming the second semiconductor layer is preferably formed by UHV-CVD, and the step of forming the fifth semiconductor layer is preferably formed by CVD.

  According to the lateral heterobipolar transistor and the method of manufacturing the same according to the present invention, the lateral heterobipolar transistor having an SiGe or SiGeC internal base on an SOI substrate and capable of high-speed operation with small parasitic capacitance and parasitic resistance. Can be formed.

  Hereinafter, a lateral heterobipolar transistor and a manufacturing method thereof according to embodiments of the present invention will be described with reference to the drawings.

  1 to 3 are views showing a method of manufacturing the lateral heterobipolar transistor of this embodiment, and FIG. 3C is a view showing a device structure after completion.

First, as shown in FIG. 1A, an oxide film layer 2 of about 10 nm is formed on an SOI substrate having an SOI layer of about 0.1 μm thickness on a BOX layer 1 provided on the substrate, A Si ₃ N ₄ layer 3 of 200 to 300 nm is deposited. Further, phosphorus is ion-implanted with an acceleration voltage of about 300 to 800 keV and a dose of about 1E13 to 1E14 cm ⁻² to form the N ⁻ type diffusion layer 4.

  Next, as shown in FIG. 1B, island-shaped collector regions are formed using the resist layer 5 as a mask by known photolithography and etching techniques.

Then, as shown in FIG. 1 (c), an acceleration voltage of about boron resist layer 6 only in a region where the external base as mask 10～50KeV, the dose of ion implantation in order 1E15~1E16cm ^-2 P ⁺ A mold diffusion layer 7 is formed.

  Next, as shown in FIG. 1D, an oxide film layer 8 having a thickness of about 10 nm is deposited, and the oxide layer 8 and the collector region are formed by known etching using the resist layer 9 as a mask only in the region where the internal base is formed. A part is etched to form a smooth silicon surface.

  Next, as shown in FIG. 2A, an SiGe or SiGeC layer 10 is selectively grown only on one side wall portion of the collector region by UHV-CVD to form an internal base.

Next, as shown in FIG. 2B, the oxide film layer 8 is etched by a known etching, and an N ⁺ type polysilicon layer 11 having a phosphorus concentration of about 1 to 7E20 cm ⁻³ is deposited.

Next, as shown in FIG. 2C, the convex portion of the N ⁺ type polysilicon layer 11 is removed by CMP or etch back.

Next, as shown in FIG. 2D, the N ⁺ type polysilicon layer 11 is not exposed to the SiGe or SiGeC layer 10 and the N ⁻ type diffusion layer 4 by etchback, and is several hundred nm on the BOX layer 1. Etch so that it remains. At this time, the N ⁺ type polysilicon layer 11 covers the side surface of the oxide film layer 2.

Next, as shown in FIG. 3A, a resist layer 12 is formed in a region including the side wall of the collector region (left side of the convex portion) and a region including the side wall of the internal base (right side of the convex portion). Thereafter, the resist layer 12 and the Si ₃ N ₄ layer 3 are used as a mask to etch the unnecessary N ⁺ -type polysilicon layer 11 outside the element region, and the collector 11a and the emitter 11b are patterned to electrically isolate both. Secure. Further, RTA treatment is performed at 850 to 1100 ° C. for several tens of seconds to activate each impurity layer formed by ion implantation.

  In this way, the collector 11a and the emitter 11b can be formed in a self-aligned manner with reference to the first patterned collector region, so that it is not necessary to provide a mask alignment margin, and the element area can be reduced.

Next, as shown in FIG. 3B, the Si ₃ N ₄ layer 3 is removed, and an insulating film layer 13 is deposited. Incidentally, Si ₃ N ₄ layer 3 and the protective film was processed N ⁺ -type polysilicon layer 11, to be processed by the oxide film layer 2 which is formed thick without forming a Si ₃ N ₄ layer 3 on the protective film Is also possible.

  Next, as shown in FIG. 3C, contact holes are formed by a known photolithography and etching technique, and the collector electrode 14, the base electrode 15, and the emitter electrode 16 are formed. Thus, the lateral bipolar transistor of this embodiment is completed. .

  As described above, the present invention can form a lateral heterobipolar transistor having a SiGe or SiGeC base on an SOI substrate and capable of high-speed operation with a small parasitic capacitance and parasitic resistance by a simple process.

  As described above, the present invention is useful for a lateral heterobipolar transistor formed on an insulating substrate.

Sectional drawing which shows the manufacturing process of the horizontal type | mold hetero bipolar transistor which concerns on this embodiment Sectional drawing which shows the manufacturing process of the horizontal type | mold hetero bipolar transistor which concerns on this embodiment Sectional drawing which shows the manufacturing process of the horizontal type | mold hetero bipolar transistor which concerns on this embodiment Diagram showing a conventional lateral bipolar transistor Diagram showing the manufacturing process of a conventional lateral bipolar transistor

Explanation of symbols

1 BOX layer 2 oxide film layer 3 Si ₃ N ₄ layer 4 N ⁻ type diffusion layer 5 resist layer 6 resist layer 7 P ⁺ type diffusion layer 8 oxide film layer 9 resist layer 10 SiGe or SiGeC layer 11 N ⁺ type polysilicon layer 11a Collector (N ⁺ type polysilicon film)
11b Emitter (N ⁺ type polysilicon film)
12 Resist Layer 13 Insulating Film Layer 14 Collector Electrode 15 Base Electrode 16 Emitter Electrode

Claims (5)

A first semiconductor layer of a first conductivity type serving as a collector region formed in an island shape on an insulating layer provided on a substrate;
A diffusion layer of a second conductivity type serving as an external base formed on one side of the surface of the first semiconductor layer;
A second semiconductor layer of a second conductivity type, which becomes an internal base formed on a side wall of the first semiconductor layer on one side;
A protective film formed on the first semiconductor layer and the second semiconductor layer;
A third semiconductor layer of a first conductivity type serving as a collector formed on a sidewall of the first semiconductor layer;
A lateral heterobipolar transistor, comprising: a fourth semiconductor layer of a first conductivity type which is an emitter formed on a side wall of the second semiconductor layer. The second semiconductor layer is made of a mixed crystal of silicon and germanium or a mixed crystal of silicon and germanium containing carbon,
The lateral heterobipolar transistor according to claim 1, wherein the third semiconductor layer and the fourth semiconductor layer are made of polycrystalline silicon. Forming a first semiconductor layer of a first conductivity type formed in an island shape on an insulating layer provided on a substrate and serving as a collector region;
Selectively forming a second conductivity type diffusion layer serving as an external base on one side of the surface of the first semiconductor layer;
Selectively etching a sidewall of the first semiconductor layer on the one side;
Selectively forming a second semiconductor layer of the second conductivity type serving as an internal base on the etched sidewall of the first semiconductor layer;
Forming a third semiconductor layer and a fourth semiconductor layer of the first conductivity type formed on the sidewalls of the first semiconductor layer and the second semiconductor layer, which respectively serve as a collector and an emitter; A method of manufacturing a lateral heterobipolar transistor, comprising: Forming the first semiconductor layer includes forming a protective film on the first semiconductor layer;
The step of forming the third semiconductor layer and the fourth semiconductor layer includes:
After forming the fifth semiconductor layer of the first conductivity type so as to cover the convex portion formed of the protective film, the first semiconductor layer, and the second semiconductor layer, the fifth semiconductor layer on the convex portion is formed. Selectively removing the semiconductor layer;
Using the resist layer and the protective film formed in the first region including the sidewall of the first semiconductor layer and the second region including the sidewall of the second semiconductor layer, respectively, as a mask The method for manufacturing a lateral heterobipolar transistor according to claim 3, further comprising a step of etching the semiconductor layer. The step of forming the second semiconductor layer is performed by UHV-CVD,
5. The method of manufacturing a lateral heterobipolar transistor according to claim 4, wherein the step of forming the fifth semiconductor layer is performed by CVD.

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