TW511418B - Method for installing resistor and capacitor in printed circuit board - Google Patents
Method for installing resistor and capacitor in printed circuit board Download PDFInfo
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- TW511418B TW511418B TW90124469A TW90124469A TW511418B TW 511418 B TW511418 B TW 511418B TW 90124469 A TW90124469 A TW 90124469A TW 90124469 A TW90124469 A TW 90124469A TW 511418 B TW511418 B TW 511418B
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511418 ^^-- 五、發明說明(1) 【發明領域 本發明係關於一福^ Ϊ特::有關於印刷電電阻及電容設置方法, 丨/、另在印刷電路柘肉t t /專暝電阻及電容之設置方 T t i破裂之設置方法。’胺電阻受應力時,避免薄膜電 L先前技術】 傳統上印刷電路板供带 ”形成具有各種功能的=件二如積體電路元件〕焊接 ί嗜路ί由有機材料或無機:料制Ϊ印刷電路板由多層板 層、,泉路寻,以便提供電子 + =成亚設置内層線路、外 ,二在印刷電路板製造技術發二機械性支擇及電性巧 l度、減少線寬等,以便在^ ~向增加層次、增加透孔 電子元件設置的數量;2印刷電路板表面上增加 相對將電容、電阻等被動反體積縮小的需求, 將元件嵌人設置於㈣電路縮小體積,並進—% 於民國90年7月】日公告之 亀 444522號「在印刷電路板植人二丨:^利公報公告第 電阻之製程*法」S明專利荦^ ^阻及金屬薄膜 在-電路基板上形成電路以及放=包括步輝··〔a〕 端;〔b〕形成—光阻層覆於上置放且電阻Μ牛所需之電極 路基板;〔。〕於該光阻層中形:::,:與電極端之電 洞,露出預定形成電阻之區域;〔^二個以上之孔 值之高分子厚膜電阻材料填入上述孔洞,内一種或多種阻抗 分子厚膜電阻材料固化;以及〔f〕去除殘餘=將該高 C:\Logo-5\Five Continents\PK8211. Ptd $ 4頁 發明說明(2) —-- ^ ΐ ί ί板上留下高分子厚膜電阻。該第444522號僅適用於 %阻喪入設置而不適用於製造電阻及電容嵌入設 電& ί =將電阻及電容嵌入設置時,不但必然能減少印刷 路板肢積而且能減化印刷電路板之製程。 極丄本發明在印刷電路板製造方法上,將電阻電 時二S +二電極圖案設置於同I ’並利用-介電材料同 哉入ίί:之一絕、!層及電容之-介電層,使電阻及電容 整合恭Ρ且^同f,藉此不但減少印刷電路板體積,而且能 程;.;,:i : f製程及電容嵌入設置製程之間相同的製 ^ r以減化印刷電路板製程步驟。 乐1圖揭示公告第444522號之高分子 立 二;:^照第1圖所示’ 一印刷電路板10包含-電=及 口;;及分 厚度mil受電極端12屢 刺而僅剩下較薄的厚度b。 越溥時’該厚度b相對的更薄。另一方:阻二:;心越/ 分子在印刷後、在因义 面,該電阻1 1之南 流動亦導致該厚户b更广、有一定的流動,f·生,因此高分子 連接角…二度乂更f。在該厚度a及厚度b交界具有一 11之連接角:受;‘严1 應力而產生變形時,該電阻 父,抵抗應力最弱的該電叫予之連差:角弓最 而;成降低印刷電路板之產品信賴度角桎易破裂,因 之連接角。或: h電:Λ造上’若藉去除該電阻11 尽度a及b之厚度呈方法避免該電阻 1__ C:\Logo-5\Five Corninents\PK8211511418 ^^-5. Description of the invention (1) [Field of the invention The present invention relates to Yifu ^ Special :: There is a method for setting the printed electrical resistance and capacitor, 丨 /, and in the printed circuit. And the method of setting the capacitor T ti rupture. 'Previous technology to avoid thin-film electricity when amine resistors are stressed] Traditionally, printed circuit board supply tapes have been formed to have various functions = pieces of two such as integrated circuit components] Welding 嗜 The road is made of organic materials or inorganic materials: The printed circuit board consists of multiple layers and layers, so as to provide electronics + = to set up the inner circuit, the outer, and the second in the printed circuit board manufacturing technology. Two mechanical options and electrical degrees, reduce line width, etc. In order to increase the level and increase the number of through-hole electronic components in the ^ ~ direction; 2 increase the need to reduce the passive anti-volume such as capacitance and resistance on the surface of the printed circuit board, and embed the components in the ㈣ circuit to reduce the volume and advance —% On July 90, 1990] Announcement No. 444522 "Planting People on Printed Circuit Boards II: ^ Lee Gazette Announces the Process of Resistors * Method" S patents ^ ^ Resistance and metal thin film in-circuit substrate Forming a circuit and putting on it include step-hui ... [a] terminals; [b] forming-a photoresist layer is placed on top of the electrode circuit substrate required for resistance and resistance; [.] ] In the photoresist layer: ::,: and holes at the electrode end to expose the area where resistance is expected to be formed; [^ two or more polymer thick film resistor materials with a hole value filled in the above hole, one or Various resistive molecules thick film resistor materials are cured; and [f] Residual = the high C: \ Logo-5 \ Five Continents \ PK8211. Ptd $ 4 pages of invention description (2) --- ^ ΐ ί High polymer thick film resistor. The No. 444522 is only applicable to the% resistance setting and not suitable for the manufacture of resistors and capacitors. When the resistors and capacitors are embedded in the setting, not only can the printed circuit board be reduced, but the printed circuit board can also be reduced. The process. In the method for manufacturing a printed circuit board according to the present invention, two S + two electrode patterns of a resistor are arranged on the same substrate and a dielectric material is used to insert the same: a layer, a capacitor, and a dielectric. Layer, so that the resistor and capacitor are integrated and equal to f, thereby not only reducing the printed circuit board volume, but also the energy range;.; :: i: f process and capacitor embedding setting process are the same system ^ r to reduce Printed circuit board process steps. Le 1 figure reveals Polymer Lier No. 444522 ;: ^ As shown in Figure 1, a printed circuit board 10 includes-electricity = and port; and the thickness mil is repeatedly punctured by the electrode terminal 12 and only the remaining Thin thickness b. As the time passes, the thickness b is relatively thinner. The other side: resistance two :; Xinyue / molecules after printing, on the sense surface, the south of the resistance 1 1 also causes the thicker household b to have a wider and certain flow, so the polymer connection angle … The second degree is more f. At the junction of thickness a and thickness b, there is a connection angle of 11: subject to; 'strict 1' When the stress is deformed, the resistance parent, the weakest resistance to the stress, the difference between the electric call: the angle bow is the most; Product reliability corners of printed circuit boards are prone to breakage, and therefore the connection angles. Or: h electricity: Λ made on ‘if the resistance 11 is removed, the thickness of a and b is shown to avoid the resistance 1__ C: \ Logo-5 \ Five Corninents \ PK8211
Ptd 第5頁 疋、發明說明(3) 極大疒 ^^1 Ρ:電路板的薄膜電:;:::11”破裂的技術問題,使 有鑑於此,* I k升產品良率及信賴度。 ^圖案利用液能:邑C ::電路板製造方法上,將電阻電 阪之底部及;;::材料填平形成-底絕緣,層,使薄膜電 應力作用於抵^庫六三以消除該薄膜電阻之厚度差引起的 產品良率=ί力最弱的部分’因而提升印刷電路板之 【發明概要】 置方法月: ί 2 ::種印刷電路板内電阻及電容’設 並利用-介電材料;時:二【電極圖案設置於同層, 印:二使電阻及電容嵌入設置於同層,使本發明且ί —介 路板體積及減化印刷電路板製程;ί;;有減^ 之”声=膜電阻之底部及厚度一致,二=該㊁” 明呈亡坦止 < 乍用於抵抗應力表弱的部分,俊 相ii::,板之產品良率及信賴度之功效 =本m電路板内電阻及電容設置方 1步私如下·在一基板上形成數個電阻及第一電容本其包 木,將該電極圖案上塗佈形成一液 :極圖 :邑.緣:供烤硬化形成-第-絕緣層;該ϊ二絕緣層芯; :亚暴露該:極圖案;在該基板上塗佈形成-液態:: 層,將該液悲光阻層以暴光顯影方式再暴露該電阻^圖Ptd, page 5 疋, description of the invention (3) 疒 ^^ 1 P: Thin-film electric circuit board:; ::: 11 "The technical problem of cracking, in view of this, * I kL product yield and reliability ^ The pattern uses liquid energy: on the manufacturing method of the circuit board C: circuit board, the bottom of the resistance electric circuit and the ;; :: material is filled to form-bottom insulation, layer, so that the film's electrical stress can be applied to the library. Eliminate the product yield caused by the thickness difference of the thin film resistor = the weakest part of the force 'thus improve the printed circuit board [Summary of Invention] Setting method month: ί 2 :: a kind of resistance and capacitance in the printed circuit board -Dielectric material; hours: two [electrode patterns are arranged on the same layer, printing: two so that resistors and capacitors are embedded and arranged on the same layer, so that the present invention and ί — dielectric circuit board volume and reducing printed circuit board manufacturing process; ί; There is a "sound" = the bottom and thickness of the film resistor are consistent, the second = the ㊁ "Ming Cheng Tan Tan < first used to resist the weak part of the stress table, Jun Xiang ii ::, the product yield and trust of the board The effect of the degree = the resistance and capacitance settings in the m circuit board. The steps are as follows. • Forming several resistors on a substrate. And the first capacitor itself is covered with wood, and the electrode pattern is coated to form a liquid: pole figure: eup. Edge: for baking and hardening to form-the first insulation layer; the second insulation core; the sub-exposed the: pole Pattern; coating on the substrate to form a -liquid :: layer, exposing the liquid photoresist layer to the resistance and exposing the resistance ^
C:\Logo-5\Five Continents\PK8211.ptd 第6頁 五、發明說明(4) 案,將該電阻電 值至屬,去除該 形成數個電阻; 絕緣層;在該第 【發明說明】 為了讓本發明 確被了解,下文 式’作詳細說明 本發明印刷電 植圖案及電容電 時做為電阻之一 入設置製程及電 本發明印刷電 利用液態絕緣材 部及厚度一致, 用於抵抗應力最 本發明將前述 車父佳貫施例内, 明之主要技術内 第2A至2L圖揭 電容設置方法, 請參照第2A圖 在一基板20上依 電容電極圖案23 之上述和 將特舉本 如下。 路板内電 極圖案設 絕緣層及 谷嵌入言免 路板内電 料填平形 以消除該 弱的部分 的主要技 並利用該 容予以適 示本發明 依序各製 所示,本 線路佈局 ’完成將 極圖案以無電解電鍍方式鍍上低接觸電阻 光阻層再暴露該電極圖案,利用塗佈方式 在該基板上利用介電材料塗佈形成一第二 二絕緣層上形成一第二電容電極圖案。 其他目的、特徵、和優點能更明 發明較佳實施例,並配合所附圖 阻及電容設置方法主要將電阻電 置於同層,並利用一介電材料同 電容之一介電層,以整合電阻嵌 置製程之間相同的製程步驟。隱 阻及電容設置方法另將電阻圖警 成一底絕緣層,使薄膜電阻之底 薄膜電阻之厚度差引起的應力作 〇 術内容適當揭示於以下所列舉的 較佳實施例配合相關技術將本發 當實施。 較佳實施例印刷電路板内電阻及 造步驟之示意圖。 第 1!: ί佳實施例 < 製造方法首先 〉〜電阻電極圖案21及 電阻電極圖幻1及第—電容電極C: \ Logo-5 \ Five Continents \ PK8211.ptd Page 6 V. Description of the Invention (4), the resistance value of the resistor is subordinate, and the resistance is formed to form several resistors; the insulation layer; In order for the present invention to be understood, the following formula is used to describe in detail the printing process of the present invention and the electric capacity of the capacitor as one of the resistors in the manufacturing process and the printed electricity of the present invention uses a liquid insulating material with the same thickness for resistance. The most stressful method of the present invention is to describe the capacitor setting method in the 2A to 2L drawings in the main technology of the aforementioned car driver Jia Guan. Please refer to FIG. 2A on a substrate 20 according to the above-mentioned sum of the capacitor electrode pattern 23 as follows. The electrode pattern in the circuit board is provided with an insulating layer and a valley embedded in the circuit board. The main technique of flattening the electrical material in the circuit board to eliminate the weak part is to use this capacity to show the present invention. The electrode pattern is plated with a low contact resistance photoresist layer by electroless plating, and the electrode pattern is exposed. The substrate is coated with a dielectric material to form a second and second insulating layer by a coating method. Electrode pattern. Other objects, features, and advantages can clarify the preferred embodiment of the invention, and in combination with the resistance and capacitor setting methods of the drawings, the resistors are mainly placed on the same layer, and a dielectric material is used as the dielectric layer of one of the capacitors. The same process steps are integrated between the resistor embedded processes. The hidden resistance and capacitance setting method also warns the resistance map as a bottom insulation layer, so that the stress caused by the difference in thickness of the bottom of the thin film resistor is operated. The content of the operation is appropriately disclosed in the preferred embodiments listed below in conjunction with related technologies. When implemented. Schematic diagram of the resistance and manufacturing steps in the printed circuit board of the preferred embodiment. First !: Preferred embodiment < Manufacturing method first> ~ Resistive electrode pattern 21 and Resistive electrode map 1 and Capacitor electrode
C:\Logo-5\Five Continents\PK8211.ptd 511418 五、發明說明(5) 圖案23設置於同層,該電極圖案21及23係屬金屬材料製 成。 二參照第2 B圖所示,本發明較佳實施例之製造方法接著 將々兒極圖案2 1及2 3進行棕黑化處理,使該電極圖案2 1及 23表面針對環氧化物〔epoxy〕具有良好的附著力 C adhesion ]。 〃 Γ t照第2 c圖所示,本發明較佳實施例之製造方法接著 ,二黾極圖案2 1及2 3上塗佈形成一液態絕緣層,並將該液 恝絕緣層烘烤硬化形成一第一絕緣層3 0,該第〆絕緣層3 〇 覆盍盩個基板2 0表面。 请=照第2D圖所示,本發明較佳實施例之製造方法接著 1 I亥第一、纟巴緣層3 〇研磨平坦並暴露該電極圖案2 1及Μ,此 時該二電阻電極圖案21之間剩下形成一底絕緣層3〇a。該^ 底,緣= 3 0a與電阻電極圖案21之間具有相同高度,使揍楚 ,^置薄膜電阻之底部及厚度一致,以消除該薄膜電阻之 厚度差引起的應力作用於抵抗應力最弱的 電極圖案21及23再進行棕黑化處理。 安者將该 請參照第2E圖所示,本著明較佳實施例之製造方法 上塗佈形成一液態光阻層31,該液態光 復瓜该笔極圖案21及23。接著將該液態光阻 二 影方式形成一孔31a,爷孔^3淡入5Φ Λ暴先顯 ^ 忑孔/木入至該電阻電極圖奢91 ”完成再暴露該電阻電極圖案21,其主要為了在阻: 圖案21上沉積低接觸電阻值之金屬。 P适極 请芩照第2F圖所示,本發明較佳實施例之製造方法接著C: \ Logo-5 \ Five Continents \ PK8211.ptd 511418 5. Description of the invention (5) The pattern 23 is set on the same layer. The electrode patterns 21 and 23 are made of metal materials. Referring to FIG. 2B, the manufacturing method of the preferred embodiment of the present invention then performs a browning process on the polar patterns 2 1 and 23, so that the surfaces of the electrode patterns 2 1 and 23 are directed to epoxy. 〕 Has good adhesion C adhesion]. 〃 Γ t As shown in FIG. 2c, the manufacturing method of the preferred embodiment of the present invention is followed by coating the diode patterns 2 1 and 2 3 to form a liquid insulating layer, and the liquid insulating layer is baked and hardened. A first insulating layer 30 is formed, and the third insulating layer 30 covers the surface of the substrate 20. Please = As shown in FIG. 2D, the manufacturing method of the preferred embodiment of the present invention is followed by 1 1 1 and 1 3, and the edge layer 30 is ground and exposed to expose the electrode patterns 21 and M. At this time, the two resistance electrode patterns Between 21, a bottom insulating layer 30a is formed. The bottom and edge have the same height between the resistance electrode pattern 21 and the resistive electrode pattern 21, so that the bottom and thickness of the thin film resistor are consistent, so as to eliminate the stress caused by the thickness difference of the thin film resistor, which is the weakest to resist the stress. The electrode patterns 21 and 23 are subjected to browning. The user refers to FIG. 2E to form a liquid photoresist layer 31 coated on the manufacturing method according to the preferred embodiment. The liquid photo-recovers the pen pole patterns 21 and 23. Next, a hole 31a is formed in the liquid photoresist shadow method, and the hole ^ 3 is faded into 5Φ Λ before being exposed ^ The hole / wood is inserted into the resistance electrode figure 91 ", and then the resistance electrode pattern 21 is exposed, mainly for the purpose of A metal with a low contact resistance is deposited on the resist: pattern 21. Please refer to FIG. 2F for a suitable method.
C:\Logo-5\Five Cont inents\PK8211.ptd 第8頁C: \ Logo-5 \ Five Cont inents \ PK8211.ptd Page 8
將該電阻電極圖案2 1以無 金屬形成一金屬層2la。 電解電鍍方式鍍上低接觸 電阻值 法接著 在該基 a及金 凊麥照弟2G圖所示,本發明較佳實施例之製造方 去除遠光阻層31再暴露該電極圖案21及23。此時, Ϊ20表面上主要剩下該第-絕緣層30、底絕緣層30 屬層21a。 請參 利用塗 電極圖 請參 在砝基 第二絕 電阻22 上相對 案,以 容之電 步驟設 照第2H圖 佈方式形 案2 1之間 照第2 I圖 板2 0上利 緣層3 2覆 之一絕緣 於該第一 組成一電 容值不符 置另一介 成一電 ’並將 所示, 用介電 蓋整個 層及電 電容電 容。若 時,利 電層。A metal layer 2la is formed on the resistive electrode pattern 21 without metal. Electrolytic plating is performed with a low contact resistance value method. Then, as shown in the 2G diagram of the substrate a and the gold alloy, the manufacturer of the preferred embodiment of the present invention removes the far photoresist layer 31 and then exposes the electrode patterns 21 and 23. At this time, the first-insulating layer 30 and the bottom-insulating layer 30 belong to the layer 21a mainly on the surface of Ϊ20. Please refer to the application of the coated electrode diagram. Please refer to the opposite case on the second insulation resistance 22 of the weight base, and use the electrical steps to set the case according to the 2H pattern. One of the two layers is insulated from the first component, and the capacitance value does not match the other dielectric to an electrical ', and the whole layer and the capacitance capacitor are covered with a dielectric as shown. If so, the power layer.
本發明較佳實施 阻22,該電阻22 該電阻22供烤聚 本發明較佳實施 材料塗佈形成一 基板2 0表面。該 容之一介電層。 極圖案2 3處設置 該弟一纟巴緣層3 2 用後續圖式第2 J 例之製造 電性連接 合硬化。 例之製造 第二絕緣 第二絕緣 在該第二 一第二電 之電容值 及2K圖所 方法接著 於二電阻 方法接·著 層32,該 層3 2做為 絕緣層_ 容電極圖" 與預計電 示之製程 若預計設置電容值需要調整電容值時,必須將位於該第 —電容電極圖案2 3上方的第二絕緣層3 2部分去除。請參昭The preferred embodiment of the present invention is a resistor 22, which is used for baking and polymerization. The preferred embodiment of the present invention is coated with a material to form a substrate 20 surface. This capacitor is a dielectric layer. The pole pattern 2 is provided at 3 places. The second edge layer 3 2 is manufactured using the subsequent example 2J of the figure. Electrical connection and hardening. Example of manufacturing the second insulation, the second insulation, the capacitance value of the second one, the second electrical method and the 2K method, followed by the two resistance method, the connection layer 32, the layer 3 2 as the insulation layer _ capacitance electrode diagram " If it is estimated that the capacitor value needs to be adjusted in the process of setting the capacitor value, the second insulating layer 32 must be removed from the capacitor electrode pattern 23. Please show
ZrA· ^ '、、、 弟2 J圖所示’本發明較佳實施例之製造方法接著將該第二 絕緣層32以暴光顯影或雷射燒結方式形成一孔32a,該孔 32a深入至該第一電容電極圖案23,其完成再暴露該電容 電極圖案2 3。 請參照第2 K圖所示,本發明較佳實施例之製造方法接著ZrA, ^ ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, 2, J, the manufacturing method of the preferred embodiment of the present invention, then the second insulating layer 32 is formed by exposure development or laser sintering to form a hole 32a, and the hole 32a penetrates to the The first capacitor electrode pattern 23 is completed to expose the capacitor electrode pattern 23 again. Please refer to FIG. 2K, the manufacturing method of the preferred embodiment of the present invention.
511418 五、發明說明(7) 將電容材料以塗佈方式填入 一電容材 一電容電 請參照 在該第二 電容電極 層24及第 請再參 法相較於 及電容設 減少印刷 明製造方 度差引起 電路板之 適用於製 厚度不均 雖然本 定本發明 範圍内, 圍當視後 料層2 4。此時,,該 極圖案2 3。 弟2 L圖所示,本發 絕緣層3 2之電容材 圖案2 5。因此該第 二電容電極圖案2 5 照第1及2L圖所示 公告第444522號方 置方法適用於將電 電路板體積及減化 法將嵌入電阻置於 的應力作用於抵抗 產品良率及信賴度 造電阻,其相對於 而具有應力易破壞 發明已以前述較佳 ,任何熟習此技藝 當可作各種之更動 附之申請專利範圍 該孔3 2 a並烘烤聚合硬化形成 電谷材料層2 4垂直對應於該第 明車父佳實施例之製造方法最後 料層2 4上垂直對應形成一第二 一電容電極圖.案23、電容材料 組成一電容2 δ。 1本發明之印刷電路板製造方 法:本發明印刷電路板内電阻 阻及電容嵌入設置於同層,以 、Ρ刷笔路板製程,此外,本發 平整底部,以消除該電阻之 應f最弱的部分’以提升印_ ,反硯公告第444522號方法僅、之 i S z之製造方法’電阻具有 、、,口構的缺點。 二鈿例揭示,然其並非用以限 &在不脫離本發明之精神和 2二,,因此本發明之保護範 所界定者為準。511418 V. Description of the invention (7) Filling a capacitor material with a capacitor material by a coating method One capacitor electricity Please refer to the second capacitor electrode layer 24 and the second method to compare the method and the capacitor design to reduce the printing method The difference caused by the difference in the thickness of the circuit board is suitable for the thickness of the substrate. At this time, the pole patterns 2 3. As shown in the figure of Brother L, the capacitor material pattern 25 of the insulating layer 32 of the present invention. Therefore, the second capacitor electrode pattern 2 5 according to the bulletin No. 444522 shown in Figures 1 and 2L is suitable for the volume of the electrical circuit board and the reduction method. The stress placed by the embedded resistor acts to resist the product yield and trust. The resistance is relatively low, and the stress is easy to damage. The invention has been described as above. Anyone who is familiar with this technique can make various changes. The scope of the patent application is attached. The hole 3 2 a is baked and hardened to form an electric valley material layer 2 4 Vertically corresponds to the last material layer of the manufacturing method of the second embodiment of the car, and a second capacitor electrode pattern is formed vertically on the fourth layer. Case 23, the capacitor material constitutes a capacitor 2 δ. 1 The manufacturing method of the printed circuit board of the present invention: The resistance and capacitance of the printed circuit board of the present invention are embedded on the same layer, and the circuit board is brushed with P. In addition, the bottom of the hair is flattened to eliminate the resistance. The weak part 'in order to improve the seal _', instead of the method of Announcement No. 444522, the manufacturing method of the i S z 'resistor has the disadvantages of ,, and structure. The second example reveals that, however, it is not intended to limit & without departing from the spirit of the present invention and 22, so what is defined by the protection scope of the present invention shall prevail.
511418 圖式簡單說明 【圖式說明】 第1圖··中華民國專利公報公告第444522號高分子厚膜 電阻之示意圖。 第2 A圖:本發明較佳實施例之印刷電路板内電阻及電容 設置方法形成電阻及電容電極圖案之剖面示意圖。’ 第2 B圖:本發明較佳實施例之印刷電路板内電阻及電容 設置方法進行棕黑化處理製程之剖面示意圖。 第2 C圖··本發明較佳實施例之印刷電路板内.電阻及電容 設置方形成絕緣層之剖面示意圖。 第2 D :本發明較佳實施例之印刷電路板内電阻及電容設 置方法研磨暴露電極圖案之剖面示意圖。 第2 E圖··本發明較佳實施例之印刷電路板内電阻及電容 設置方法塗佈光阻層後暴光顯影暴露電阻電極圖案之剖I% 示意圖。 第2 F圖··本發明較佳實施例之印刷電路板内電阻及電容 設置方法進行無電解電鍍處理之剖面示意圖。 第2 G圖··本發明較佳實施例之印刷電路板内電阻及電容 設置方法進行去除光阻之剖面示意圖。 第2 Η圖:本發明較佳實施例之印刷電路板内電阻及電容 設置方法塗佈形成電阻之剖面示意圖。 第2 I圖:本發明較佳實施例之印刷電路板内電阻及電容 設置方法形成絕緣層之剖面示意圖。 第2 J圖:本發明較佳實施例之印刷電路板内電阻及電容 設置方法暴光顯影或雷射燒結暴露電容電極圖案之剖面示511418 Brief description of the drawings [Explanation of the drawings] Fig. 1 · Schematic diagram of polymer thick film resistors of the Republic of China Patent Gazette Bulletin No. 444522. FIG. 2A is a schematic cross-sectional view of a method for setting a resistor and a capacitor in a printed circuit board according to a preferred embodiment of the present invention. ′ FIG. 2B: A schematic cross-sectional view of a browning process for a method for setting a resistor and a capacitor in a printed circuit board according to a preferred embodiment of the present invention. Fig. 2C ····················································································· the thickness of the cross-section of the base plate can be divided into two layers; Section 2D: A schematic cross-sectional view of a method of setting a resistor and a capacitor in a printed circuit board according to a preferred embodiment of the present invention by polishing and exposing an electrode pattern. Fig. 2E ... The method for setting the resistance and capacitance in a printed circuit board according to a preferred embodiment of the present invention is a schematic I% cross-sectional view of a resistive electrode pattern after exposure and development after coating a photoresist layer. Fig. 2 F ·········································································---· · ························· Fig. 2G ·············································································· — either the dimensions of the two sides as shown in FIG. Fig. 2 (a): A schematic cross-sectional view of a method for setting a resistor and a capacitor in a printed circuit board according to a preferred embodiment of the present invention to form a resistor. FIG. 2I is a schematic cross-sectional view of an insulating layer formed by a method for setting a resistance and a capacitor in a printed circuit board according to a preferred embodiment of the present invention. Figure 2 J: A method for setting the resistance and capacitance in a printed circuit board according to a preferred embodiment of the present invention.
C:\Logo-5\Five Continents\PK8211.ptd 第11頁 511418 圖式簡單說明 意圖。 第2 K圖:本發明較佳實施例之印刷電路板内電阻及電容 設置方法填入電容材料之剖面示意圖。 第2 L圖:本發明較佳實施例之印刷電路板内電阻及電容 設置方法形成第二電容電極圖案之剖面示意圖。C: \ Logo-5 \ Five Continents \ PK8211.ptd Page 11 511418 Schematic description of the intention. FIG. 2K: A schematic cross-sectional view of a method for setting a resistance and a capacitor in a printed circuit board filled with a capacitor material according to a preferred embodiment of the present invention. FIG. 2 L is a schematic cross-sectional view of a method for setting a resistor and a capacitor in a printed circuit board to form a second capacitor electrode pattern.
圖 號說 明 ] 10 印 刷 電 路 板 11 電 阻 12 電 阻 電 極 圖 案 a 電 阻 厚 度 b 電 阻 厚 度 c 連 接 角 20 基 板 21 電 阻 電 極 圖案 21a 金 屬 層 22 電 阻 23 第 一 電 容 電 極 圖 案 24 電 容 材 料 層 25 第 二 電 容 電 極 圖 案 26 電 容 30 絕 緣 層 3 0a 底 絕 緣 層 31 液 態 光 阻 層 31a 孔 32 絕 緣 層 32a 孔[Illustration of drawing number] 10 Printed circuit board 11 Resistance 12 Resistance electrode pattern a Resistance thickness b Resistance thickness c Connection angle 20 Substrate 21 Resistance electrode pattern 21a Metal layer 22 Resistance 23 First capacitor electrode pattern 24 Capacitive material layer 25 Second capacitor electrode pattern 26 Capacitor 30 Insulating layer 3 0a Bottom insulating layer 31 Liquid photoresist layer 31a hole 32 Insulating layer 32a hole
C:\Logo-5\Five Cont inents\PK8211.ptd 第12頁C: \ Logo-5 \ Five Cont inents \ PK8211.ptd Page 12
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CN102655077A (en) * | 2011-03-03 | 2012-09-05 | 精工电子有限公司 | Method of manufacturing a semiconductor device |
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CN102655077A (en) * | 2011-03-03 | 2012-09-05 | 精工电子有限公司 | Method of manufacturing a semiconductor device |
CN102655077B (en) * | 2011-03-03 | 2016-03-09 | 精工电子有限公司 | The manufacture method of semiconductor device |
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