TW511273B - Semiconductor memory device and its manufacturing method - Google Patents

Abstract

A semiconductor memory device is provided. Its one-bit memory cell (MC) is composed by a MOS transistor with an electrically isolated floating body. The gate 13 of the MOS transistor connects to the word line (WL), its drain diffusion layer 14 connects to the bit-line (BL) and its source diffusion layer 15 connects to the constant source line (SL). Inject carriers that are generated from the impact ionization into the floating body 12 to keep the first threshold state. Release the carriers of the floating body into the second threshold state by applying a forward bias on the drain side PN junction. These two states are the bi-state of memory. Employ this simple transistor structure as a memory unit to get a dynamic memory with less signal lines.

Description

V. Description of the Invention (1) Background of the Invention Field of the Invention The present invention relates to a dynamic semiconductor memory device (DRAM). Related prior art description The previous DRAM uses MOS transistors and capacitors to form memory cells. The miniaturization of DRAM has been greatly improved by using a trench capacitor structure and a stacked capacitor structure. The current unit memory unit size (unit size). If the minimum processing size is F, the area is reduced to 2F X 4F = 8F2. That is, the minimum processing size F is reduced with time, and when the unit size is generally aF2, the coefficient a is also reduced with time. At present, F = 0 · 1 8 μπι, and oc = 8 has been reached in the future. With the development trend of changing cell size or wafer size, it is required to achieve a < 8 when FC 0.18 μηι, and a < 6 when F < 0.1 3 μπι, how to reduce the cell size with microfabrication Area has become a major issue. Therefore, various schemes for making the memory unit of one transistor per one capacitor to 6F2 and 4F2 have been proposed. However, there are technical difficulties that the transistor must be upright, large electrical interference between adjacent memory cells, and manufacturing technical difficulties such as processing and film formation, which are not easy to put into practical use. In addition, many DRAM solutions that do not use capacitors and use a transistor as a memory cell are also listed, as follows: (1) JOHN E. LEISS et al5 1 dRAM Design Using the Taper-Isolated Dynamic CellM (IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. ED-29, NO. 4, APRIL 1982, __ This paper size applies to China National Standard (CNS) A4 specifications (210x 297 mm) 5 (11273 A7 B7 V. Description of the invention (2) pp707-714 ) (2) JP 3-171768 (3) Marnix R. Tack et al, "The Multistable Charge-Controlled Memory Effect in SOI MOS Transistors at Low Temperatures" (IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 37, MAY, 1990, ppl373-1382) (4) Hsing-jen Wann et al, " A Capacitorless DRAM Cell on SOI Substrate1 丨 (IEDM93, pp635-638) (1) The memory cell system is a MOS transistor with a buried channel structure Structure. The parasitic transistor formed at the corner of the cone of the element separation insulating film is used to charge and discharge the surface inversion layer to perform dual memory. (2) The memory cell uses MOS transistors that are separated from each other. The threshold value determined by the well potential of the MOS transistor is used as the dual data. (3) The memory cell is composed of the MOS transistor on the SOI substrate. The negative voltage increased from the outside of the SOI substrate is oxidized by the silicon layer. The hole storage of the film and the interface portion performs the double memory by releasing and injecting the holes. (4) The memory cell is composed of a MOS transistor on an SOI substrate. A MOS transistor is a structure. A structural system is superimposed on the surface of the non-polar diffusion layer, and a reverse conductivity type layer is formed, which essentially combines the pMOS transistor for writing and the NMOS for reading. The substrate area of the NMOS transistor is used as a floating The node stores the double-matrix data by its potential. However, the structure of item (1) is complicated, and the controllability of characteristics is difficult due to the use of parasitic transistors. Although the structure of item (2) is simple, the drain of the transistor Both the source and the source need to be connected to the signal line to control the potential. In addition, due to the production of wells-. -5 The paper size is suitable for financial purposes ^^^ (CNS) A4 specification (21 () > < 297 public ^ " ~ ":-511273 A7 B7 V. Description of Invention (3) Therefore large cell size, and can not be rewritten by bit. Item (3) needs to control the potential from the SOI substrate side, so it cannot be rewritten bit by bit, and it is difficult to control. Item (4) requires a special transistor structure, and word lines, write bit lines, read bit lines, and clear lines are needed on the memory cell, so the number of signal lines is large. SUMMARY OF THE INVENTION One of the objects of the present invention is Provided are a semiconductor memory device and a method for manufacturing the same. A simple transistor can be used to form a memory unit, and dynamic memory of dual data can be performed with fewer signal lines. The one-bit memory early element of the semiconductor memory device according to an embodiment of the present invention is composed of one transistor. 5 The transistor includes: a semiconductor layer, which is a first conductivity type, which is electrically separated from other memory cells and floats. State; the drain diffusion layer, which is of the second conductivity type, is formed on the semiconductor layer of the first conductivity type, and is connected to the bit line; the source diffusion layer, which is of the second conductivity type, is formed on the first conductivity type Type semiconductor layer is isolated from the drain diffusion layer and connected to the source line; and a gate electrode is formed on the semiconductor layer between the drain diffusion layer and the source diffusion layer via a gate insulating film, and is connected In a word line; wherein the transistor has: a first data state having a first threshold voltage of a number of carriers that have an excess on the semiconductor layer; and a second data state having an excess of the semiconductor layer on the semiconductor layer. Many carriers are released _-6 ^ ___ This paper size applies to Chinese National Standard (CNS) A4 specifications (210X 297 mm) 511273 A7 B7 V. Description of the invention (4) Second threshold voltage . In addition, a method for manufacturing a semiconductor memory device according to an embodiment of the present invention includes forming an insulating film on a semiconductor substrate, forming a semiconductor layer of a first conductivity type on the insulating film, and forming a gate formation region on the semiconductor layer. For an open mask, a sidewall insulating film is formed on the opening sidewall of the mask, and impurities are added to the semiconductor layer through the opening of the mask to form an impurity-added layer of a first conductivity type having an impurity concentration higher than that of the semiconductor layer. After the sidewall insulating film is removed, a gate insulating film and a gate are buried in the openings above the mask to form a plurality of openings. After removing the mask, an impurity is added to the semiconductor layer to form a second conductivity type drain. Diffusion layer and source diffusion layer. Brief Description of the Drawings Fig. 1 is a sectional view showing a memory cell structure of a DRAM according to a first embodiment of the present invention. FIG. 2 is an equivalent circuit of a memory cell of the DRAM. FIG. 3 is a layout of a memory cell array of the DRAM. Fig. 4A is a sectional view taken along the line A-Af in Fig. 3. FIG. 4B is a B-B ^ j plan view of FIG. 3. FIG. FIG. 5 shows the relationship between the zigzag potential and the surface potential of the DRAM cell. FIG. 6 is an explanatory diagram of a read mode of the DRAM cell. FIG. 7 is an explanatory diagram of another readout method of the DRAM cell. This paper size applies the Chinese National Standard (CNS) A4 specification (210X 297 mm) 511273 A7 B7 V. Description of the invention (5) Figure 8 is a waveform diagram showing the "1 " data reading / renewing operation of this DRAM. Figure 9 is a waveform diagram showing the “0” data reading / renewing operation of the DRAM. FIG. 10 is a waveform diagram showing the “1” data reading / 0 ”data writing of the DRAM. FIG. 11 is a diagram showing the operation Waveform diagram of "0" data read / "1" data write of DRAM. Figure 12 is a waveform diagram of "1 " data read / renew operation of other DRAM readout methods. Fig. 13 is a waveform diagram showing "0" data read / renew operation of other read methods of the DRAM. ·, Figure 14 shows the "1" data readout of the DRAM's other readout methods, and "0 " data write operation waveforms. Figure 15 shows the" 0 "data readout of the DRAM's other readout methods. ΠΓ · Data writing operation waveform diagram. FIG. 16 is a characteristic diagram showing the gate capacitance Cgb-voltage Vgb of the DRAM cell. FIG. 17 is an equivalent circuit diagram of the constant current readout method of the DRAM cell. FIG. 18 shows the DRAM FIG. 19 is an equivalent circuit for explaining a π0 ”writing speed of the DRAM cell. FIG. 20 is a graph showing a potential change of the p-type layer of FIG. 19. Fig. 21 is a graph showing the gate capacitance Cgb-voltage Vgb of the π0 "data cell of the DRAM cell (when poly-type polycrystalline dream gate). -8- This paper size is applicable to China National Standard (CNS) A4 specifications ( 210X 297 mm) 511273 A7 B7 V. Description of the invention (6) Figure 22 also shows the relationship between the word line potential Vwl of the Π0Π data unit and the table potential VB. Figure 23 shows the word "1" of the DRAM cell. The relationship between the line potential Vwl and the surface potential VB. Figure 24 is a graph showing the gate capacitance Cgb-voltage Vgb of the "1" data cell of the DRAM cell (in the case of a p-type polycrystalline stone gate). Fig. 25 is a graph showing the gate capacitance Cgb-voltage Vgb of the "1" data unit of the DRAM cell (when p-type polycrystalline broken gate). Fig. 26 shows the word line potential Vwl of the ffln data unit and the table body. The relationship between the potential VB (in the case of the n-type polycrystalline silicon gate). FIG. 27 is a graph showing the gate capacitance Cgb-voltage Vgb of the "0" data cell of the DRAM cell (in the case of the p-type polycrystalline silicon gate). . Fig. 28 shows the relationship between the zigzag potential Vwl of the "0ff data unit" and the surface potential VB (in the case of an n-type polycrystalline silicon gate). Fig. 29 shows the gate of the ff 1π data unit when a thin silicon layer is used. Capacitance Cgb-voltage Vgb curve (in the case of ρ-type polycrystalline silicon gate). Figure 30 shows the relationship between the word line potential Vwl of the "Γ 'data unit and the body potential VB. FIG. 31 is a graph showing the gate capacitance Cgb-voltage Vgb of the Π0Π data unit when a thin silicon layer is used (when a ρ-type polycrystalline dream gate is used). FIG. 32 shows the relationship between the word line potential Vwl and the surface potential VB of the Π0Π data unit. Figure 33 is a graph showing the relationship between the impurity concentration of the silicon layer and the threshold threshold of the "1" data. -9- This paper size is in accordance with the Chinese National Standard (CNS) A4 specification (210X297 mm)

Binding 511273 A7 B7 V. Description of the invention (7) Fig. 34 is also a graph showing the relationship between the impurity concentration of the silicon layer and the unit current of the "1" data unit. Fig. 35 is also a graph showing the relationship between the impurity concentration of the silicon layer and the time of change of the bit line potential during readout. Figure 36 shows the relationship between the body potential and the threshold when the data of the 1Π data unit is held (in the case of a P-type polycrystalline silicon gate). Figure 37 shows the body potential and the threshold when the data of the 1Π data unit is held The relationship between (in the case of η-type polycrystalline silicon gate). Fig. 38 is a diagram showing the relationship between the potential change of the word line and the threshold deviation. Fig. 39 is an exemplary layout of a sense amplifier showing the first embodiment of the present invention. Fig. 40 is a cross-sectional view of a DRAM cell structure corresponding to the second embodiment corresponding to Fig. 1. Fig. 41 is a diagram showing the relationship between the surface potential of the MOS transistor and the threshold voltage. Fig. 42A is a review of Fig. 40. The basic pn junction structure diagram of the unit structure effect used for preliminary review. Figure 42B is a diagram showing the electric field distribution of the pn junction structure part shown in FIG. 42A. Figure 43 is the pn junction structure of the drain terminal shown in the review of the unit structure effect of FIG. 40. Fig. 44 shows the relationship between the width of the low-concentration p-type layer and the extension of the depletion layer in Fig. 43. Fig. 45 is also the relationship between the width of the low-concentration p-type layer and the maximum electric field strength. -10- This paper Applicable scale National Standards (CNS) A4 size (210X297 mm)

Binding 511273 A7 B7 V. Description of the invention (8) FIG. 46 is a graph showing the relationship between the width of the low-concentration P-type layer and the extension of the depletion layer when the concentration of the n-type diffusion layer is reduced again. FIG. 47 is a graph showing the relationship between the width of the low-concentration p-type layer and the maximum electric field strength. Fig. 48 is a diagram showing the elongation state of the depletion layer of the cell structure of Fig. 40 under optimized conditions. Fig. 49 is a cross-sectional view of a unit structure showing a modified embodiment of the unit. Structure of Fig. 40; Fig. 50 is a diagram of the ρη junction structure of the drain terminal and its electric field distribution shown in the review of the cell structure effect of Fig. 49; Fig. 51 is a graph showing the relationship between the width of the low-concentration p-type layer and the extension of the depletion layer in Fig. 50; FIG. 52 is also a graph showing the relationship between the width of the low-concentration p-type layer and the maximum electric field strength. Fig. 53 is a diagram showing the elongation state of the depletion layer of the cell structure of Fig. 49 under optimized conditions. FIG. 54 is an explanatory diagram of manufacturing steps of the unit of FIG. 49. FIG. FIG. 55 is an explanatory diagram of manufacturing steps of the unit of FIG. 49. FIG. FIG. 56 is an explanatory diagram of manufacturing steps of the unit of FIG. 49. FIG. FIG. 57 is an explanatory diagram of manufacturing steps of the unit of FIG. 49. FIG. FIG. 58A is a plan view of a unit structure of the third embodiment. Fig. 58B is a sectional view taken along the line A-A 'of Fig. 58A. Fig. 59A is a perspective view of a unit structure according to a fourth embodiment. FIG. 59B is a cross-sectional view taken along the bit line direction of FIG. 59A. FIG. 60A is a layout of a DRAM cell array according to the fifth embodiment. FIG. 60B is a cross-sectional view taken along the line I-Γ of FIG. 60A. -11-This paper size applies to China National Standard (CNS) A4 (210X297 mm)

Loading 511273 A7 B7

FIG. 60C is a cross-sectional view taken along the line II-II ′ of FIG. 60A. FIG. 61A is a plan view showing a separation step of components that should not be implemented. Fig. 61B is a sectional view taken along the line I-Γ of Fig. 61A. FIG. 61C is a cross-sectional view taken along the line III-III of FIG. 61A. FIG. 62A is a plan view showing a transistor formation step in this embodiment. Fig. 62B is a sectional view taken along the line I-Γ of Fig. 62A. FIG. 6C is a cross-sectional view taken along the line II-IΓ of FIG. 62A. Fig. 63A is a plan view showing a step of forming a source wiring layer in this embodiment. Fig. 63B is a sectional view taken along the line I-Γ of Fig. 63A. Fig. 64A is a plan view showing a step of embedding a bit line into a contact hole in this embodiment. Fig. 64B is a sectional view taken along the line I-Γ of Fig. 64A. FIG. 65 is a plan view showing a step of embedding another bit line into a contact hole. Fig. 66 is a sectional view showing a step of forming an interlayer insulating film after the element is formed in the sixth embodiment. Fig. 67 is a sectional view showing a step of burying a contact hole in this embodiment. FIG. 68 is a plan view showing the step of forming the source wiring layer in the conventional embodiment. FIG. 69 is a cross-sectional view showing the step of forming an interlayer insulating film in this embodiment. FIG. 70 is a diagram showing the formation of bit lines in this embodiment. Sectional view of steps. FIG. 71 is a plan view corresponding to FIG. 61A with the element separation structure of the seventh embodiment. _ -12. This paper size is in accordance with Chinese National Standard (CNS) A4 (210X 297 mm) 511273 10 V. Description of the invention (The specific embodiment of the light and detailed sinus is described in detail below. The embodiment of the present invention will be described with reference to the drawings. Figure 1 shows a cross-sectional structure of a memory cell of a DRAM according to a first embodiment of the present invention. 'FIG. 2 shows an equivalent circuit thereof. The memory cell MC is composed of an N-channel MOS transistor of a SOI structure U. That is, a semiconductor chip is used. A silicon oxide film as an insulating film is formed on the substrate 10, and an SOI substrate having a P-type silicon layer 12 is formed on the silicon oxide film. The silicon oxide layer 12 on the substrate passes through the gate oxide film 16, A gate 13 is formed, and a self-integrated n-type source and drain diffusion layers 14 and 15 are formed on the gate 13. The source and drain diffusion layers 14 and 15 are formed with a silicon oxide film at the bottom 丨 j Therefore, when the surface area formed by the p-type silicon layer 12 is separated by the oxide film in the width direction (direction perpendicular to the paper surface of the figure), the bottom surface and the side surface in the channel width direction are separated from other insulation. , The floating state in which the channel length is separated by pn junctions. When the memory cells MC are arranged in a matrix, the gate electrode 13 is connected to the word line WL ', the source diffusion layer 15 is connected to a fixed potential line (ground potential line muscle, and the drain diffusion layer 14 is connected to the bit line b1.) 3 shows the layout of the memory cell array, and Figs. 4 (a) and 4 (b) respectively show the AA, and BB · sections of Fig. 3. The p-type silicon layer 12 is embedded with a silicon oxide film to form a grid pattern. That is, the common drain is shared. The two transistor regions are arranged in the direction of the word line wl so that the elements are separated by the stone oxide film 21. Alternatively, the silicon layer 12 can be etched instead of the silicon oxide film 21 to be buried. The lateral element is separated. The gate electrode 13 is formed continuously in one direction, and μk constitutes the word line WL. The source diffusion layer 15 is formed continuously along the word line WL to form a sigh. This constitutes a fixed potential line- 13- This paper size applies Chinese National Standard (CNS) A4 specification (210X297 mm) 511273 A7 B7 V. Description of the invention (11) (common source line) SL. The transistor is covered with an interlayer insulating film 23 and formed on it There is a bit line BL. The bit line BL contacts the electrode diffusion layer 14 common to the two transistors. It is arranged to intersect the word line WL. Thereby, the bottom surface of the silicon layer 12 and the lateral side in the width direction of the body region of each transistor are separated by an oxide film, and separated by pn junctions in the length direction of the channel to maintain a floating state. The structure of the memory cell array is formed with word lines WL and bit lines BL with a minimum processing size F. The unit cell area is shown as a dashed line on FIG. 3, which is 2F X 2F = 4F2. By the NMOS The operating principle of a DRAM cell composed of a transistor is to use the surface area of the MOS transistor (a p-type silicon layer 12 separated from other insulation) to store the holes of many carriers. That is, by operating the MOS transistor in the pentode region, a large current flows from the anode diffusion layer 14 to cause impact ionization in the vicinity of the anode diffusion layer 14. The holes of the excess carriers generated by the impact ionization are held on the P-type silicon layer 12, and the storage state of the holes (the state where the potential is higher than the thermal equilibrium state) is set to the data "1". The drain is diffused The pn junction between the layer 14 and the p-type layer 12 is forward biased, and the state where the excess holes of the p-type chip layer 12 are released is set to the data "0". < Data " 0 "," 1 "is the potential difference in the surface area of the body, which is memorized as the voltage difference of the threshold of the MOS transistor. That is, the state of the data in the surface area of the body is high by the hole storage Π1Π state The threshold voltage Vthl is lower than the threshold voltage VthO of the state "0 ". In order to maintain the π 1Π data state of the cavity where many carriers are stored in the surface area, a negative bias voltage needs to be applied to the word line. The data remains in the state, as long as the reverse operation (deletion) of data writing is not performed, even if _-14 -____ is performed, this paper size applies the Chinese National Standard (CNS) Α4 specification (210X 297 mm) binding

511273 12 V. Description of the invention (reading operation is not changed. That is, 'different from DRAM using a charge stored on a carrier] DRAM / 1 capacitor, non-destructive reading can be performed. Many kinds of private data reading The word line potential Vwl and the table: potential VB = relationship, and its relationship with the data, 〇 &quot;,]] "is shown in Figure 5. Therefore, the first method of reading data is to use the word Line trade]: given the data, 〇 ,,, '] "^ Threshold threshold voltage VthG, vthl readout potential in the middle, the current does not flow into τ: material: memory unit, but into the" quoti "data In the memory unit. For example, the bit line BL is precharged to a specified potential vbL ·, and then the sub-line WL is driven. As shown in FIG. 6, when the data is &quot; 〇 &quot; Line precharge, the potential does not change, when T data, the precharge potential decreases: The second readout method is to increase the word line w L and then supply current to the bit line I ′ in response to "〇", " 1 ”continuity 'the rising speed of the bit line potential is constant <' pre-charging the bit line BL It becomes 0v, and the bit line current is supplied by the Shengnan word line WL 'as shown in Fig. 7. At this time, by using the virtual cell to detect the difference of the potential rise of the 70 line, the data can be discriminated. The Wanshi system reads the bit line current difference of 1 ”different bit line when the bit line BL button is set to the specified potential. When the current difference is read, a voltage conversion circuit is needed, but the potential difference is differentially amplified and output sensed As a result, in the first embodiment of the present invention, in order to selectively write &quot; 〇 &quot; data, π is the word line machine selected from the memory cell array and the bit is: Line: The surface area of the memory cell selected by the L foot potential releases excess space ^ The capacitance combination between the surface area of the subline is very important. It examines in detail the state of the holes stored in the surface area of k and shell material 1, Must make 511273 A7 B7

V. Description of the invention (The 13 word line is completely biased in the negative direction, and the capacity between the gate and the base of the memory cell is maintained in a state that becomes the capacity of the gate oxide film (that is, the state of the surface is not shaped == layer state). m In addition, the writing operation, "〇", "丨", should be pulsed to reduce power consumption. When "〇" is written, although the hole current flows from the body region of the selected transistor, there is no polarity. The electron current flows into the surface of the surface of the surface of the surface, but the surface of the surface of the surface is not injected with holes. The operation waveforms are described in more detail below. Figures 8 to 11 show the data by using the bit line to select whether there is discharge. Read / renew and read / write operation waveforms in the first read mode. $, Figures 1 and 9 are "1" and ",", "0", and "read / rewrite" of data, respectively. New operation. Before the time ti, the data is held (non-selected). When the word line WL1 is given a negative privacy time of 11, the south word line WL is raised to a positive specified potential. At this time, the: line potential is set at "〇 The threshold of the data is between Vth0 and vtM. This is used to precharge the battery at 1 pm The bit line BLI1 is discharged to a low potential. At the time of data, the bit line potential VBL is maintained. This is used to discriminate the "if,, ποπ data. Continue, at time t2, the potential of the word line WL is increased again, At the same time, the data is read, and the positive potential of the bit line BL is given (Figure 8). The negative potential is given to the bit line (Figure 9). Therefore, when the memory unit is selected as "1", the The large channel current flowing in the pentode operation causes #ionization, and the excess hole injection is kept in the surface area. In the case where the “1” data is written as 0, the non-pole is connected to the forward bias. However, the acupoints were not kept in the surface body area, and “〇” data was written again.

Binding

As a successor, at time t3, the word line W] L is biased in the negative direction, and the read / renew bismuth operation ends. Same as the memory cell that executes 1, 1, and data reading. It is connected to other non-selected memory cells of bit line BL. The word line WL is negative. Therefore, the surface area remains at negative potential, which does not cause Impact ionization. versus

The memory cell that reads out the data is similarly connected to the bit line BL and / 'other non-remote memory cells, and the word line WL is also maintained at a negative potential without causing hole release. Figure 10 and Figure 11 are the “1” data and “〇”, the data readout / write operations using the same reading method. Figure 10 and Figure 丨 read operations at time 〖丨

They are the same as those in FIGS. 8 and 9. After the reading, at time t2, the word line WL is again written in the same selection unit as the "% bit". At the same time as the data, the bit π line BL is given a negative potential (Figure 10). When the data is entered, the bit line bl is given a positive potential (Figure 11). As a result, the data element, the drain, is connected to the forward bias, and the holes in the body region are freed. It is given that, "Single unit of data" causes impact ionization near the drain, and excess holes are injected and maintained in the surface area. * Figures 12 ~ 15 are the second method of pre-charging the bit line BL to 0V, supplying current to the bit line BL after the word line selection, and judging the data by the potential rising speed of the bit line bl Read / Renew and Read / Write Operation Waveforms in Out Mode ... FIG. 12 and FIG. 13 are read / renew operations of “1” data and “〇” data, respectively. At time 11, the word line WL held at the negative potential is raised to a positive potential. At this time, the word line potential is set as shown in FIG. 7 and is higher than the thresholds VthO, Vth 1 of the data of "0" "1". Or, the same as the first reading method, 15 5 、 Explanation of the invention (also: Set the ΐline potential at the threshold of T, T data thv_, vthl foot. Following%, at time t2, 伢 L private machine is in place. Hunt this, Yu Zheng, The memory unit is deep-started, and the potential rise of the bit line rainbow is small: when the data is two or two, the current of the memory unit is low (or no current), ^, and `` 7 '' is rising rapidly. Use this to determine丨, 1 ”, 丨, 〇 丨 丨 data. Following the results, when the data is read at time t3, the bit line BL is given a positive potential (Figure 12). When the data is read as T, the bit is given. Line BL negative potential: Figure "2" When this 'select memory cell is' τ data, the drain current flows, # ionization in f, excess hole injection is maintained in the body area, and T data is written again In other cases, the drain is connected to forward bias, and the excess holes are not kept in the surface area. "0 &quot; data is written again

Q at 14:00 'Offset the word line w L to the negative direction and finish reading / re-reading. Figures 14 and 15 show the reading of "1" and "quota" data using the same reading method, respectively. Read / write operation. The read operation of Figure 14 and Figure 15 at time tl &amp; t2 is the same as that of Figure 12 and Figure 13. After reading, when "0" data is written in the same selection unit, a bit is assigned. The negative potential of the element line BL (Figure 14) is given to the positive potential of the bit line BL (Figure 15) when the data is written. As a result, the "+" of the data unit is not assigned, and the drain is connected to the positive direction. Bias, the holes in the body area are released. In the unit given with "1" data, a large drain current flows in, causing impact ionization near the drain, and excess holes are injected and held in the body area. As described above, 'the DRAM cell of the first embodiment of the present invention is composed of a simple MOS transistor with a floating surface area that is electrically separated from other 1-18- This paper size applies to Chinese National Standard (CNS) A4 Specifications (210X297 mm) 511273 A7 B7 5. Description of the invention (16), can achieve 4F2 unit size. In addition, the potential control of the floating surface area is based on the self-gate capacitance combination, instead of using the back gate control from the back of the SOI substrate. The source diffusion layer is also a fixed potential. That is, the read / write control is simple and is performed only by the word line WL and the bit line BL. Furthermore, since the memory cell is basically non-destructive read, there is no need to provide a sense amplifier on each bit line, so the layout of the sense amplifier is easy. In addition, because of the current reading method, it is highly resistant to noise and can be read even when the open bit line method is used. In addition, the manufacturing process of the memory unit is simple. In addition, the SOI structure is an important technology when considering the performance improvement of logic LSI in the future. The DRAM of the first embodiment of the present invention is also likely to be co-located with a logic LSI of this SOI structure. This is because, unlike the previous DRAM using a capacitor, a process different from that of a logic LSI is not required, and the manufacturing steps are simple. Furthermore, the DRAM of the SOI structure according to the first embodiment of the present invention has an advantage of superior memory retention characteristics as compared with the former case in which the DRAM of one transistor / capacitor type was used as the SOI structure. That is, when a transistor / capacitor-type DRAM was used as an SOI structure, holes were stored on the floating semiconductor surface, and the threshold of the transistor was low, which caused the sub-limit current of the transistor to increase. . As a result, memory retention characteristics are deteriorated. In contrast, the memory cell with only one transistor in the first embodiment of the present invention does not have a transistor path that reduces the memory charge. The data retention characteristic is determined solely by the leakage of the ρη junction, and there is no sub-limited current leakage. The problem. In fact, the following -19- The paper size of the present invention can be judged from the judging criteria listed below. This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm).

A7

(b) Whether this has reached a sufficient level, combined with k degrees (whether the writing speed can reach 10, and whether the body current of about 20 nA or more can be obtained at the time of entry). It is expected that whether the selectivity of 0 is sufficient (the availability of “G” data and, 1 ”data is sufficient for the body surface potential difference AVB: =! V). Can the capacitance between the gate and the surface area be far greater than "Can you take the threshold of the larger" 1 "data? Μ below" to verify these criteria. [Remember the capacity, retention time, and leakage current of the body unit] If you have 1G memory unit iDRAMi memory The average memory retention time of the body unit is RT = 10 sec. Based on the principle of (μ μm), the gate oxide film thickness of the memory unit is tox = 2.5 nm, because the gate oxide film capacity is 14 fF / cm2, therefore, the gate area is 〇1, and the gate oxide film valley Cox is Cox = 0.14 fF. When the pn junction capacitance cj zz 0.08 fF described later is included, the total capacitance is ctotal = 0.22 fF. When the charge is stored in the gate capacitor, the leakage current I leak / node of each cell that changes the potential of AV = 0.1 V during the memory retention time RT = 10 sec is shown in the following formula 1. (Equation 1) I leak / node = Ctotal AV / RT = 2.2 x 10'18 A / node The thickness of the silicon layer on the SOI substrate is 100 At nm, because the pn junction area is -20-This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) 511273 A7 B7

0 · 1 μηηθθ.1 μπΐχ2 =: 〇02 μπι2, so when the leakage current I leak / area per unit area is required, it is shown in the following formula 2. (Equation 2) I leak / area = 2.2 x 10 * 1δ / 0.02 = 1.1 χ 1〇-16 Α / μτη2 When the reverse bias of ρη junction on SOI substrate is about 2 ν, the average leakage current is less than The unit's memory retention time scale is 10 sec, which can obtain the same memory retention characteristics as the DRAM of a solid-state transistor / 1 capacitor. In addition, the leakage current 叩 of the junction on the SOI substrate has previously been shown to be ˜3 x i0_n a small (1 μm per word line direction) (1995 Symp. VSLI Tech., P. 141). In the future, the above-mentioned memory retention characteristics can be fully realized. … Γ Γ ’Write time and body current] The write time is determined by the capacitance of the cell node (interrogator) and the body current isub. As mentioned above, the gate capacitance is ctotal = 0.22fF. The specification of the writing time is twr = 10 nsec. The current required for writing the V voltage in the body area within this time is shown in Equation 3 below. Private (Formula 3)

Isub = CtotalAV / twr

= 0.22 X ΙΟ'15 X 1/10 X 1〇 * 9 = 22 nA into the channel of the unit transistor; and pole voltage * When the power is 10, the above table is about 2/1000 with the current Isub. Desperate, Fang Ji, J &lt; Eclipse

Vds = 2v, when the impact ionizes, it can flow into the required surface current.

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511273 A7 B7 V. Description of the invention (19) [Selectivity and semaphore of "0" write] The CV curve of the memory cell (the relationship between the voltage Vgb between the gate and the body and the capacitance Cgb) is shown in Figure 16 . When the receptor concentration in the surface area is NA = 1018 / cm3, the flat band voltage is VFB = -1.2 V. The Π1Π writing is performed at a word line voltage of Vwl = 1 V (body potential VB = 0.6 V). When the word line potential is lowered after writing, the capacitance Cgb is initially zero due to being blocked by the channel inversion layer. Furthermore, assuming that the threshold value of the Π1Π cell is Vth 1 = 0 V, even if the word line potential is reduced to 0 V, the body potential VB does not change. The capacitor Cgb is made clear because the word line potential is a threshold voltage. Vth 1, which means Vw 1 = 0 V. At this time, the voltage between the gate and the body is Vgb = -0.6 V. In addition, the capacitance per unit area of the pn junction is NA = 1018 / cm3, and the drain voltage is 4 fF / μm2 when the drain voltage is Vd-20V. When the junction area is 0 · 1 μπι X 0 · 1 μηι χ2 = 0.02 μπ2, the pn junction capacitance is Cj = 0.08 fF. In Fig. 16, when Cgb / Cox of Vgb = -0.6 V is 0.8, and Cox = 0.14 fF, the capacitance combination ratio λ to the body region of the gate voltage is shown in Equation 4 below. (Equation 4) λ = Cgb / (Cgb + Cox) = 0.14 x 0.8 / (0.14 x 0.8 + 0.08) = 0.58 Therefore, the word line potential decreases, and the capacitance between the gate and the surface of the surface Cgb begins to appear in the surface area The ratio of the potential change to the potential change of the word line is about 60%. Moreover, when the word line potential is lowered, although the surface potential also decreases, Vgb is greater than -0.6 V at the negative terminal. As a result, the capacitance Cgb becomes larger, which can be reduced due to the combination of capacitance. _-22 -___ This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) 511273

Surface body potential. Finally, as shown in Figure 16, the potential of the word line drops to vwl = -1.3 v, the average capacitance-to-capacitance ratio; when I is 0.6, the surface area of the surface is initially 0.6 v, so only AVB = 1.3 Vx 0 · 6 = 0 · 78 V, which is -0.18 V. At this time, Vgb = -1.12 V. That is, when the potential of the body is injected due to excess hole injection at VB = 0 · 6 V, the: r data is written at the word line potential of Vwl = -1 · 3 V after the data is written. The combination holds _〇 · 18 V. In this state, a certain cell lowers the bit line potential to a negative potential and executes "0" writing. When the surface potential is lowered, the word line potential is -1 when the surface potential is lower than -0.58 V. · For 3 V non-selected cells, the holes in the surface of the cell also flow to the drain, and the data is destroyed. Therefore, to avoid data destruction, the minimum value of the body potential at the time of data writing is -0.18 V. Since the maximum value of the "1" data writing voltage is the built-in voltage 0.6 ν, the maximum signal amount is 0.6 V- (-0.18 V) = 0 · 78 V. Therefore, the above-mentioned ΔνΒ is "0", and the signal amount difference (surface potential difference) between the data and the "1" data. [Non-destructive readout confirmation] As described above, the memory cell according to an embodiment of the present invention can perform non-destructive readout in principle. In fact, in order to ensure non-destructive reading, it is necessary to confirm (1) that even if reading is performed repeatedly "0 ·, data to the cell, there is no hole injection in the body area, (2) even if reading is repeatedly performed" 1 "data To the cell, there is no hole injection in the body area. Because the maximum number of repetitions at this time maxNmax is equivalent to between a certain renewal and the next renewal (such as 128 msec), the same cell continuously performs read operations.

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-23- 511273 A7 B7 5. Explanation of the invention (21) operation (100 nsec), so it is about Nmax = 128 msec / 100 nsec = 1.28X 1016 times. (1) The non-destructiveness of the "0" data that maintains the hole storage state of the watch body should be the key. Therefore, even if a current flows during reading, it is necessary to perform reading in a linear region at a low current of about Vds = 0.5 V. Or, as in the aforementioned first reading method, a method in which no current flows in the unit of π〇π data is adopted, which is more non-destructive. The above is the criterion for judging the basic feasibility of the DRAM according to the first embodiment of the present invention. Next, the results of analyzing the performance of the DRAM according to the first embodiment of the present invention will be further described in order. [Bit line potential change during readout] The above is to verify the second readout method described in FIG. 12 and FIG. 13, that is, the bit line potential change when a certain current is supplied to the bit line to perform readout. Figure 17 shows the equivalent circuit used in this verification. For simplicity, it is assumed that the potential of the bit line BL is precharged to 0 V 'and the potential V w 1 of the word line 1 W L is at t> 0, as shown in the following formula 5, and is set at the threshold 値 Vth of the memory cell MC (VthO, Vth 1) or more. (Equation 5)

Vwl &gt; On the Vth bit line BL, when t> 0, a certain current of I c is supplied, as shown in the following formula 6, which is less than the saturation current I of the unit transistor when V gs = V w 1 dsat (Equation 6)

Ic &lt; Idsat = (k / 2) (Vwl-Vth) 2 -24- This paper size applies Chinese National Standard (CNS) A4 specification (210X 297 mm) 511273 A7 B7 V. Description of invention (22) and k = ( W / L) (sox / tox) peff At this time, the change in the potential Vbl of the bit line BL is represented by the following formula 7 when the terminal current of the cell transistor is Ids. (Equation 7) dVbl / dt = (l / Cbl) (Ic-Ids) Because the unit transistor operates in the linear region, Vbl &lt; Vwl-Vth is established. At this time, the non-polar current Ids of the unit transistor is given by Equation 8 Means. (Equation 8)

Ids = k [Vwl-Vth- (l / 2) VblJVbl When formula 8 is integrated into formula 7, the following formula 9 is obtained. (Formula 9)

Vbl = α · β [1-exp (t / tO)] / [Pa * exp (t / tO)] because cc = Vwl-Vth + [(Vwl-Vth) 2-2Ic / k] 1/2 Vwl-Vth -[(Vwl-Vth) 2-2Ic / k] 1/2 to = 2Cbl / [k (ap)] According to the assumptions of Equation 5 and Equation 6, a &gt; β &gt; 0 is satisfied. Therefore, Equation 9 is a convex increasing function for time t, which is Vbl (0) = 0 and Vbl (〇〇) = P. FIG. 18 shows the calculation result of Equation 9. Suppose the threshold of the unit of Π0Π data is Vth0 = 0.3 V, the threshold of the unit of Π1Π data is Vthl = -0.3 V, the threshold of the virtual unit is Vthd = 0 · 05 V, and the bit line capacitance Cbl = 100 fF, the gain factor of the unit current is k = 2.0 x 1 (T5 (A / V2), and use -25- This paper size applies to China National Standard (CNS) A4 specifications (210 X 297 mm)

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511273 A7 --------___ B7 V. Description of the invention (23 ^ ^ ~-

Ie-0'9 Idsat = 13 μΑ, Vwl = 15 V, meanwhile displaying the line voltage VblO at the time of "〇" data, and the bit line voltage Vbll at the time of "" data are the signal private pressure ¥ 31§0 'Vsigl And the voltage Vbld of the reference bit line. As a result, it can be known that a signal of 100 mV can be obtained after n nsec due to the rise of the word line. The virtual single το is a MOS transistor with the same structure as the memory unit, and it should be a type that can appropriately set the surface potential. For this reason, the self-integration is based on the processing limit and temperature change of the threshold of the fa unit. At this time, by selecting the body potential of the virtual list 70, the most appropriate setting can be set, 0 ,,, "1," the signal amount of the data. Γ〇π writing speed] &quot; The 0 ”write, as described above, samples the holes in the body region by joining the P-type body region of the forward-biased memory transistor with the ρη of the n-type drain. This "〇," the writing speed is reviewed using the equivalent circuit of Fig. 19 as follows. When t = 〇, ρη is bonded to the ρ layer and 11 layers, both 2 · 2 ν, and is in a balanced state. 1 &gt; 〇, When the terminal is 0 ν, the potential change state of the surface body (ρ-type layer) with capacitance is calculated. If the potential of the time tip-type layer is V, the following formula ι0 holds.

(Equation 10) t = -CiodV / I At this time, I is the current of the ρη junction, and is expressed by the following Equation 11. (Formula 11) ί = Is [exp (V / r | .Vt; M) Gu τ Setsuka Standard (CNS) A4 Specification (21G. ^ Public Love) ^ -— 511273 A7 ____ —_B7 V. Description of the Invention (24 ) In Equation 11, IS is the saturation current, η is the coefficient between i ~ 2, Vt is the Thermal Voltage, and Vt = kT / q. When integrating Equation 11 into Equation 10, the following formula is obtained: 12. (Formula 12) V = ri.Vt.ln [l / {l- [l_exp (-VO / ri.Vt)] exp (t / t〇)}] At this time, to is tO = Cr ^ vt / Is given constant. Using the number in the following formula 13 to calculate the result of formula 12 is shown in Figure 2 (Equation 13)

Is = Js · Aj

Js = 6.36 X l (T5A / m2 Aj = 0.01 μπι2 T = 8.5〇C Vt = 0.0309 η = 1

t0 = 10.7 sec VO = 2.2 V From the calculation results in Fig. 20, it can be seen that when "〇" is written, the potential of the surface (P-type layer) of about insee is fixed below 0 · 7 V. [Potential change in the body region] As mentioned above, regarding the selectivity of "0" writing, the relationship between the word line potential and the body potential will be described with reference to FIG. 16. That is, it is explained in detail that after writing is performed with a positive word line potential Vwl, the reduction is _-27-This paper size applies the Chinese National Standard (CNS) A4 specification (210X 297 mm) 511273 A7 -----— —_ — B7 V. Invention: Line potential to negative i, hold data, raise word line to positive potential again, read pen position Vr, and read out, what kind of potential change is displayed on the surface of body area 0 unit transistor foot brake The capacitance Cgb per unit area between the electrode and the surface (p-type layer) of the SOI substrate is represented by the following formula 14 using the potential difference Vgb between the gate and the surface. (Formula 14)

Cgb / Cox = i / [i + 2 * ID2 (Vgb-5) / Vt] I / 2 The capacitance per unit area of the gate oxide film, c0x, uses the boundary electric constant and the oxide film thickness tox, and Cox = εοχ / tox means. The ID is a dimensionless dimension normalized by γ = (ssi / sox) tox ′ Debye Length LD, and is obtained according to the following formula 15. (Formula 15) ID = (sox / esi) LD / tox = (sox / ssi) [kT * ssi / (q2NA)] l / 2 / tox At this time, the parameter δ is determined by the following conditions. That is, 'Formula 14 is the thickness w ρ of the depletion layer diffused on the surface of the surface according to the following formula 16 (see Table 6). This is an undimensionalized person who still normalizes the actual thickness of the depletion layer wp ) Find it out. (Equation 16) wp = -1 + [1 + ID2 (Vgb-6) / Vt] I / 2 At this time, Vgb = VFB (flat band voltage). Under the condition of wp = 1 D, it shows -28-

This paper size applies to China National Standard (CNS) A4 (210X297 mm) 511273 A7 B7

V. Description of the invention (26) The following formula 17 is shown. (Equation 17) ID = -1 + [1 + ID2 (Vgb-5) / Vt] 1/2 To solve this equation 17, the parameter δ is the following equation 18. (Equation 18) δ = VFB- (1 + 2 / ID) Vt Although the relationship between Cgb and Vgb can be obtained from Equation 14 and Equation 18, it does not cover a wide Vgb region. Therefore, when the voltage between the gate and the source Vgs exceeds the threshold 电 Vth of the transistor, Ggb = 0, and at the same time, it is replaced with 1 to calculate Cgb 値 for a wide range of Vgb 値The calculation results are shown in FIG. 21. When the word line is a p-type polycrystalline silicon gate, the relationship between the voltage Vgb and the capacitance Cgb between the word line of the unit of 0Π data and the surface of the cell is obtained. The conditions are tox = 2.5 nm, ΝΑ = 5 X 1018 / crn3, temperature 85 ° C, VFB = 0 · 1 V, VthO = 1 · 5 V, VB = · 〇 · 7 V, Cox = 0 · 14 fF, Cj = 0.08 fF 〇 In addition, changes to the gate voltage The change in the body potential of AVg AVb is expressed by the following formula 19. (Equation 19) △ Vb two [Cgb / (Cgb + Cj)] AVg At this time, Cj is the capacitance of the input body of the series (the pn junction capacitance described above) -29- This paper size applies the Chinese National Standard (CNS) A4 specification (21 × X 297 mm) 511273 A7 B7 V. Description of the invention (27) When the formula is fixed and formula 19 is changed, formula 20 is obtained. (Formula 20 ) AVg = (1 + Cgb / Cj) AVgb When formula 20 is integrated, the following formula 2 1 is obtained. (Equation 21)

Vg-VgO = igL [l + Cgb / Cj] dVgb When formula 21 is rewritten, formula 22 is obtained. (Formula 22)

Vgb-VgbO = (Vg-VgO)-igL (Cgb / Cj) dVgb When calculating the formula 22, the change AVb of the body voltage VB can be obtained from the voltage change AV g of the gate voltage Vwl (word line). The unit of "0" data is calculated under the same parameter conditions as in the calculation of Figure 21 above, as shown in Figure 22. From this result, if the word line is 2.0 V, perform a "0" write to reduce the surface of the table to -0.7 V and the word line decreases to -2 V. When holding the data, the surface potential at this time remains at -2.1 V . The word line is then raised to 1.0 V, and when reading is performed, the surface of the body is only raised to approximately -0.9 V. That is, the cell potential of the Π0Π data is lower than that at the time of writing. Therefore, the reading limit is extended by 0.2 V. The results of performing the same calculation on the "1" data element are shown in Figure 23. The relationship between the capacitance Cgb and the voltage Vgb at this time is shown in FIG. 24. Figure 21 and Figure 22 use the same parameters. ”For 1Π data, it can be seen that after writing, the surface of the table is 0.6 V, the word line is maintained at -2.0 V, and the surface of the table is -1.0 V. Π0Π 资 -30- This paper size applies Chinese National Standards (CNS) Α4 specification (210X297 mm) V. Description of the invention (28) In principle, the body potential of the surface can reach _10 ν. However, the "2" written in "&quot; 〇" will drop to -1.5 bits When the line is restored to pn junction coupling (coupling ratio is 18%), the surface of the surface rises by 0.3 v, which becomes _〇7 v. Therefore, in the case of "0" data in FIG. 22, the potential after writing becomes _07v. It is the same when writing. Although there is capacitive coupling of the bit line, it is different from π〇 ”writing. It is the current flowing into the body Isub. In the writing, 丨, the data, the built-in voltage 0 · 6 V rises to the potential v shown in Equation 23 below. (Formula 23)

Isub ^ Is [exp {V / (n.Vt) -l}] η brings Isub = 14 nA, Is = 6.36xl0, A, vt == () 〇3ι v &quot; = 1.2, get ν = 0 96 v. Therefore, the body's electricity is close after the data is written! The V 'bit line drops from uv to 0V, even though it drops 0 3 V' due to the coupling, there is still more than 0: ¥. The body potential after the data is written into the current, that is, "actually 1", should be calculated by U. ο V 〇 or more, in order to set the flat band voltage at VFB = 〇1㈣. This corresponds to when a gate (word line) of p-type polycrystalline silicon is formed on the p-type silicon layer i of the SOI substrate. Secondly, on the same SOI substrate, when the closed pole is used by 极, the result of the same calculation is performed. At this time, + band = -1 · 1 V. Figure 25 is the result of calculating the capacitance Cgb-voltage Vgb for the "1" data unit. Figure 26 is the same for the data unit. Find the word, edge voltage Vwi, and body voltage ... The result of the relationship. The parameters other than the flat band voltage are the same as those in Figure 21 and Figure 22 above. V. Explanation of the invention (29. The thresholds are all Vthl =: :() V. ☆: According to the above results, it can be ensured that 0 " Kezhi is the word line at the time of writing is 1 person σ σth0 = I ν., _ ^ Ma ^ · 5 V, it is 0 5 V when it is stated. The author,, if the pressure is -2 · 5 V, then 丨, j 丨, Zi-Beke's word for waiting, compared with the use of ρ-type polycrystalline gate / table body, Vi word line amplitude, only 0.2; not ^ VFB = (Compared to the time of MV, the results of the same-valley Cgb-voltage Vgb characteristics transfer to Thai competition <electricity I # 阳 a "sub, the spring pressure Vwl-surface body voltage VB characteristics of the fruit. Threshold VthO =;! V. Χ, &amp; 苻 "raw junction-0.8V, when the bit is 飧 ....., although the surface potential of the foot &lt; The coupling of the ρη junction is only U, 3 V above, and 丨 而成, resulting in -0 · 5 V. At this time, although the word line at the time of writing is also 1 · 5 V, _ η is + Ri ^ η &lt; ΛΓ ^ *, 1 due to the fact that when the term is 0. 5 V, the surface potential only returns 0. 15 V and becomes _0 · 65 ν. Knowing the above ρ type When crystalline silicon gate and η-type polycrystalline silicon gate electrode when the operating conditions are organized into the following Table 1 and Table 2. [Table 1]

g. Type Polycrystalline Silicon Gates Vwl (read) = 1 V Vwl (hold) = -2 V Vwl (write) = 2 V

Vbl (丨 丨 0nwrite) = -1.6 V Vbl (n lnwrite) = 1.6 V VthO = 1.5 V Vthl = 0.5 V -32- This paper size applies to China National Standard (CNS) A4 (210 x 297 mm) (Centimeter) 511273 A7

1 ’’ lean material unit? Table body potential at the time of purchase VB == 〇. Ό v 〇 Table body potential at the time of data unit purchase = _ 1 V

[Table 2] In the case of η-type polycrystalline broken gate Vwl (read) = 0.5 V Vwl (hold) = -2.5 V Vwl (write) = 1.5 V Vbl (丨 丨 0nwrite) = -1 · 4 v

Vbl (丨 丨 1 丨 ’write) = 1 · 4 v

VthO = 1.0 V Vthl = 0 V

Table body potential VB when reading "1" data unit = 0.6 v n0 &quot; Table body potential VB = V when reading data unit In addition, in Tables 1 and 2 above, π 1, preferably Xn

The bit line potential V (&quot; l, We) 'at the time T i is entered should be determined by the substrate current (hole current) and the write time. It belongs to an indeterminate system, which is a display setting assumption. From the above, the advantages of using a polycrystalline dysprosium can be understood. The word line amplitude is 4 V at all times. When the voltage is lowered, the following measures must be taken. (A) The threshold 値 Vth deviation must be reduced. (B) The memory cell current must be reduced. (C) The Cj / Cox reduction ratio is related to (A) and (B). In the past, it was assumed that △ vth: Vth〇Vthi =丨 〇v However, it can be strictly controlled at about 0.8V ~ 0.6V. If it can reach △ vth = -33- This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm)

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M1273

0.6 V, the amplitude of the winter line can be reduced and suppressed at 2 χ 1.2 v = 2 · 4 v. The following is a detailed review of item (c). This is not to reduce the boundary of Δνίι, but to reduce the voltage of the word line. The member (C) requested that the thickness of the rare earth layer Tsi of the SOI substrate be thinner than 100 nm assumed in the past, and at the same time or alone, it can be responded by reducing the impurity concentration of the n-type source and drain diffusion layers. The former reduces the pn junction capacitance Cj relatively by reducing the 卯 junction area. In the latter case, since the condition that the depletion layer extends to the 11-type diffusion layer is provided, the junction capacitance Cj between the source and drain diffusion layers and the surface body region is also reduced. Figures 29 and 30 show that the junction capacitance is halved to Cj = 0 〇4 fF, instead of the junction capacitance q = 0 used in the past verification. Cgb_Vgb curve and Vwl-VB curve. Conditions other than Cj are the same in FIGS. 23 and 24, and the gate is P-type polycrystalline silicon. Cj = 0.04 fF corresponds to a silicon layer thickness of 50 nm. Therefore, after writing a table potential of 0 · 6 v to the "1" data cell, when the word line is lowered to -2 · 0 V, the table potential drops to -1 · 3 v. Therefore, it can be seen that the table is lowered. The zigzag potential required for body potential to -1 V, that is, the zigzag potential required for data retention Vwl (hold) = _1.6V. Similarly, when the data unit of '〇' uses Cj = (h04 fF The cgb-Vgb * line and Vwl-VB curve are shown in Figure 31 and Figure 32, respectively. The conditions other than Cj are the same as those in Figure 21 and Figure 22. As mentioned above, a thin silicon layer (Tsi = 50 nm) will be used. The operating conditions of the DRAM cell when the S0I substrate is shrunk correspond to Table 1, as shown in Table 3 below. -34- This paper size applies to China National Standard (CNS) A4 specification (210X297 mm) 511273

[table 3]

Vwl (read) = 0.8 V Vwl (hold) = -1.6 v Vwl (write) = 1.6 y Vbl (n0 丨 丨 write) =: 4 6 v Vbl (”l” write) =: "6 v VthO = 1.3 V Vthl = 0.3 V 1 Table body potential at the time of unit cell output Vb = ο ”v” 〇 ”Table body potential when the data unit is read out VB =] Halving to 50 nm and 'linger] Private Valley Yi Shi' can reduce the word line amplitude from 4 v to 3.2 v. It should be noted that the threshold difference W of the data, 〇 &quot;, T can still be If the silicon layer on the V.S.sub.substrate can be thinned to 30 nm, low voltage can be realized. When the silicon layer is too thin, the silicon layer will be completely depleted, which may cause loss of memory. The work itself. Therefore, the thickness of the silicon layer should be about 50 planes. Figure 33 shows that the surface potential VB is [乂] and the threshold difference between 0 and 6 v △ impurity: the relationship with the concentration of NA in the stone layer. At this time, the gate oxide film thickness is Tox / 2.5 nm, and the temperature is T = 85 ° c. It is understood that to ensure ^ v, NA =: L〇xl0i9 / cm3. Because of this, the impurity concentration is relatively Thick, and set at NA = 8x10iW, followed by 〇8 v. At this time, the operation bar of Table 3 Ding slightly positive as follows in Table 4.

511273 A7 ____ B7 V. Description of the invention (~) *-[Table 4]

Vwl (read) = 0.7 V Vwl (hold) = -1.6 V Vwl (write) = 1.4 V

Vbl (n0’’write) = -1.6 V Vbl (丨 丨 l’ ’write) = 1.4 v

VthO = 1.1 V Vthl = 0.3 V

Table potential VB when the data unit is read out = 0.6 V π〇π Table potential when the data unit is read out VB = -1 V In Table 4, the bit line potential Vbl when writing "1" due to "1" ( "丨", such as), is determined by the substrate current (hole current) and the write time. Therefore, 1 · 4 v is a hypothetical sigh. When the unit transistor adopts a general structure instead of a 丄 structure, it can be determined by Increasing the substrate current lsub can achieve this level of low voltage. Under the above operating conditions, the maximum voltage of the unit transistor is 30 V. The gate oxide film thickness is τχ = 2 · 5 nm, so "1 &quot; At the moment of writing, an electric field of about 12 MV / cm is generated on the gate oxide film, which affects reliability. However, if the gate oxide thickness is increased to ensure reliability, it should be avoided because the capacitance combination ratio used to control the body potential will deteriorate. Therefore, other insulating films such as Ai203, which have a high dielectric constant, should be used for the gate insulation film instead of the silicon oxide film. In order to achieve a lower voltage, it is desirable to make the thickness of the silicon layer Tsi of the S0i substrate as thin as about 30 nm, to improve the threshold controllability of the cell transistor, and at the same time to take a large mobility. Taking the above measures into consideration, a voltage reduction of about 2.0 V to 2.5 V should be achieved. ____ -36- The paper rule of this paper-511273 A7 B7 V. Description of the invention (34) It can ensure that the “1” cell current Idsl written into the unit transistor when the threshold difference AVth shown in FIG. 33 is equal to The corresponding data reading time Δt is shown in Figs. 34 and 35, respectively. The cell current is obtained from Idsl = (k / 2) oVth / 2) 2. In addition, the readout time At is set by setting the potential of the word line between Vth 1 and VthO at the time of readout, and only turning on the "1" data unit to obtain the self-predicted bit line of the capacitance Cbl = 100 fF. The time until the charge potential is discharged to 200 mV. Results At NA = 6 X 1018 / cm3, Idsl = 1.4 μA, At = 15 nsec ° Fig. 36 is the surface voltage VB of the investigation "1" when the data unit is held, due to the relationship with the threshold Vthl The result of the degree of decline. The conditions are: gate oxide film thickness tox = 2.5 nm, impurity concentration NA = 5 X 1018 / cm3, flat band voltage VFB = 0.1 V, surface potential VB1 = 0.6 V, gate oxidation Film capacitance Cox = 0.14 fF, junction capacitance Cj = 0.04 fF. In addition, the holding potential of the word line is Vwl = Vthl-2 V. As a result, when Vthl = 0.5 V or more, the surface potential at the same time as Vthl is maintained Rise. When Vthl &lt; 0.5 V, the body potential saturates at -0.93 V. This means that when the word line drops to Vthl &lt; 0.5 V, the capacitance Cgb saturates at the gate oxide film capacitance Cox. Therefore, the flat band voltage VFB = 0.1 V , That is, when the gate is a p-type polycrystalline silicon film, it should be set to Vthl &lt; 0.5 V. Since it is known that △ Vth = VthO-Vthl = 0.8 V, VthO &lt; 1.3 V. Therefore, VthO = 1.1 V and Vthl = 0.3 V are good choices. The operation method of the above integration is shown in Table 5 below. In addition, the parameters of the integration device are as follows: Table 6. -37- This paper scales applicable Chinese National Standard (CNS) A4 size (210 X 297 mm)

Binding 511273 A7 B7 V. Description of Invention (35) [Table 5]

VthO = 1.1 V, Vthl = 0.3 V Vwl (read) = 0.7 V Vwl (hold) = -1.7 V Vwl (write) = 1.5 V Vbl (&quot; O1 丨 write) = -1.5 V Vbl (丨 Twrite) = 1 5 V VB (Hlf, read) = 0.6 V VB (n0f, read) = -1.0 V VB (f, l, fwrite) = 0.6 V VB (, f0, fwrite) = -0.9 V VB ('Thold) = -1.0 V VB (ff0, fhold) = -2.4 V

Vmax = 3 · 2 V (Vds between non-selected WL and ΠΓ · write BL) [Table 6] p-type polycrystalline stone gate NA = 5 X 1018 / cm3 tox = 2.5 nm Channel length L = 0.1 μηι , Channel width W · 0.1 μηι Tsi = 50 nm k = (W / L) (sox / tox) μοΐΐ = 2.0 x 10'5 A / V2 At this time, the readout characteristic of the DRAM cell is at the bit line When the capacitance Cbl is 100 f F, the time until the potential difference of 200 m V is added is A t = 15 nsec. -38- This paper size is in accordance with Chinese National Standard (CNS) A4 (210 X 297 mm). 5. Description of the invention (36)

Corresponding to Tables 5 and 6, as shown in Tables 7 and 8 below when the n-type polycrystalline stone gate is activated), the body potential VB, due to the threshold. Other conditions are the same as those in Figure 36. At this time, the operating procedures and device parameters are as follows, [Table 7],

VthO = 0.1 V, Vthl: = -〇 · 7 ν Vwl (read) = 0.3 V Vwl (hold) = -2.7 V Vwl (write) = 0 · 5 V Vbl (,, 0,, write) = -1.5 γ Vbl (丨 丨 lnwrite) = 0.5 V VB (丨 丨 1 丨, read) = 0.6 V VB (n0f, read) = -1.0 y VB (f, lffwrite) = 0.6 V VB (&quot; O '丨 write ) = -0.9 v

VB (丨 T, hold) = -1.0 V VB (M0f, hold) = -2.4 V

Vmax = 3.2 V (Vds between non-selected WL and "1" written to BL) [Table 8] n-type polycrystalline silicon gate NA = 5 X 1018 / cm3 tox = 2.5 nm (CNS) A4 specification (210 x 297 mm) 511273 A7 ___________ B7 V. Description of the invention (37) Channel length L = 0.1 μπι, wide width w = 〇 ″ μιη Tsi = 50 nm k = (W / L) ( 8〇x / tox) μ ^ ΐΐ = 2.0 x 10'5 A / V2 At this time, the readout characteristic of the DRAM cell is that when the bit line capacitance cbl = 100, the time until the potential difference of 200 mV is added is △ 〖= 15 nsec. However, it is not a problem whether Vbl (&quot; l ', write) flows enough substrate current Isub at 0.5 v, and when it is forced to be above 0.5 V, the maximum voltage Vmax in this part rises. In this regard, it is advantageous to use p-type polycrystalline silicon on the gate, that is, for the threshold 値 VthO 'at the threshold of the word line vwi ( Although write) is determined, the bit line potential Vbl (,, 1 write) determined by the "1" write characteristic separate from it is higher than the word line potential Vwl, and Vmax is determined by Vbl (,, 1 ,, write ) -Vwl (hold) to determine. If Vwl (Write) g Vbl (,, l, fwrite), then Vmax = Vwl (write) -Vwl (hold), the operating voltage can be minimized. The above calculation is only This is a related standard DRAM cell. Actually, the manufacturing process will cause the threshold variation and k variation of unit transistors between batches, wafers, wafers, and wafers. In addition, there are also bit line capacitors. And design word line potential changes. In addition, it is also necessary to consider the fit noise between the bit lines. In addition, there is also a change in threshold 値 Vth due to temperature. When using a reference cell close to a memory cell, Can compensate some of the above-mentioned threshold changes In other words, with this readout method, basically, the above-mentioned threshold changes can be limited to the differences within the chip only. The temperature of the paper caused by temperature changes is -40. This paper standard applies to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 511273 A7 B7 V. Description of the invention (38) Limitation changes can be completely eliminated on the system. As mentioned above, the memory unit of the first embodiment of the present invention is in principle non- Destructive readout and current readout. Figure 39 shows the layout of a sense amplifier that uses the cell characteristics of this memory cell. Paired bit lines BL, bBL are arranged on both sides of the sense amplifier SA, The open bit line method is adopted. When one of the bit line pairs BL and bBL enables the word line WL, the other enables the virtual word line DWL that selects the virtual cell DC. The virtual cell DC is the same as the memory cell MC The MOS transistor structure is used to give the intermediate body potential of the data π ″, ”1π to its surface area. In the figure, the two bit line pairs BL and bBL are selected by the selection gate SG and connected to a sense amplifier. SA. Connect The bit lines of one sense amplifier SA are alternately arranged with the bit lines connected to the adjacent sense amplifier SA. At this time, for the four memory cells MC selected by one word line WL at the same time, two sense cells Sense amplifier SA. That is, among the data of the four memory cells MC selected at the same time, actually two are detected by the sense amplifier SA, and the remaining memory unit data is not sent to the sense for reading. Sense amplifier. The first embodiment of the present invention does not cause destructive readout caused by general DRAM, so this sense amplifier method can be adopted. Although the DRAM cell according to the first embodiment of the present invention is a DRAM type based on the 0.1 μm principle, the following two conditions need to be met. • Condition 1: The substrate bias effect must be fully utilized. • Condition 2: The leakage current of the pn junction must be reduced. These conditions 1, 2 are contrary to the requirements for the impurity concentration in the surface area. Condition 1 Increases the threshold of π〇π, π 1π data by a large substrate bias effect -41-This paper size applies Chinese National Standard (CNS) A4 specification (210 X 297 mm) 511273 A7 B7 V. Invention Explanation (39) 値 The voltage difference, therefore, the impurity concentration (receptor concentration) NA of the P-type silicon layer 12 (surface area) in FIG. 1 must be NA 2 5 X 1018 / cm3 or more. This case will be described with reference to Fig. 41. FIG. 41 shows the relationship between the body potential VB and the threshold Vth of the NMOS transistor depending on the receptor concentration NA. When the receptor concentration is NA1, the threshold voltage difference of "0" and "1" data is ΔVthl, and when the receptor concentration is NA2, the threshold voltage difference is Δνα], AVthl> AVth2. That is, in order to increase the threshold of the "0", "1" data and the voltage difference, the receptor concentration needs to be increased above a certain level. In addition, the acceptor concentration above NA = 5 X 1018 / cm3 must also make the fine MOS transistor with a channel length = 0.1 μm actually perform the operation. In addition, Condition 2 is to ensure the data retention characteristics. At this time, the impurity concentration in the surface area should be lower. The 0.1 μηι principle DRAM type, in order to maintain 10 seconds of data in the body area, the pn junction leakage of the source and drain must be suppressed below 3 X 10 "7 A / cm2. In addition, in order to reduce leakage current The permeation current of the components must be suppressed to 2.5X105 V / cm or less in the electric field formed in the depletion layer of the pn junction. This is to make the receptor concentration in the surface area reach NA = 1.0 X 1017 / cm3 or less. The electric field in the depletion layer is 1.7 X 10 V / cm (with a reverse bias of 2 V) at the concentration of the upper acceptor required under Condition 1. It cannot meet the requirements of Condition 2. Figure 40 corresponds FIG. 1 shows the structure of a DRAM cell MC having a second embodiment that can satisfy the opposite conditions 1, 2 above. The difference from the cell structure of FIG. 1 is that the surface area is composed of a p-type silicon layer 12. That is, in this embodiment, the P-type diffusion layer 12 a having a lower boron concentration (acceptor concentration) connected to the drain and source diffusion layers 14 and 15 and the self-drain and source diffusion layers 14 and 42 are arranged. -This paper size applies to China National Standard (CNS) A4 (210X 297 mm) 511273 A7 B7 V. Description of the invention 40) The p + -type diffusion layer 12b having a high boron concentration (acceptor concentration) in the central portion of the 15-way away channel constitutes the surface body region. The p + -type diffusion layer 12b is formed to the depth of the silicon oxide film 11 at the bottom. The cell structure takes the form of sandwiching the equivalence between two NMOS transistors with a low threshold voltage and an NMOS transistor with a high threshold voltage. At this time, the entire threshold voltage is controlled by the p + -type diffusion layer 12b at the center. In addition, since the drain and source diffusion layers 14 and 15 form a pn junction with the low-concentration p-type diffusion layer 12a, the leakage current is smaller than that of the entire surface area formed by the p + -type diffusion layer. Smaller. The above results can meet the two opposite conditions 1, 2 above. Specifically, can we use the unit structure shown in Figure 40 to obtain the effect? Or what concentration and position need to be set? The review results are as follows. First, As shown in FIGS. 42A and 42B, when a reverse bias is applied to the voltage V on the pn junction between the n-type diffusion layer (donor concentration ND) and the p-type diffusion layer (acceptor concentration NA), the Range and intensity distribution of internal electric field E as a preliminary review It is assumed that the pn junction is an abrupt junction. As shown in FIG. 42 and FIG. 42B, the X-axis is set in the direction across the pn junction. At this time, the potentials in the n-type diffusion layer and the p-type diffusion layer are (j & gt) D, φ A, the front end position in the η-type diffusion layer of the depletion layer is -xn, the front end position in the p-type diffusion layer is xp, Poisson's equation and the electric field ED in the η-type diffusion layer and the p-type diffusion layer , ΕΑ is expressed by the formula 24. ε is the dielectric constant of silicon. (Formula 24) d2 (j) D / dx2 =-(q / 2s) ND (-xn &lt; x &lt; 0) ά2φΑ / άχ2 =-( q / 2s) NA (0 &lt; x &lt; xp) -43- This paper size applies to China National Standard (CNS) A4 (21〇x 297 mm)

装 亲 511273 A7 B7 V. Description of the invention (41) ED = -άφϋ / άχ (-χη &lt; χ &lt; 0) ΕΑ = -άφA / dx (0 &lt; χ &lt; χρ) Built-in potential is ()) For bi, the boundary condition is expressed by the following formula 25. (Formula 25) ED (-xn) = 0 (|) D (-xn) = φΜ + V ED (0) = ΕΑ (0) φϋ (0) = φΑ (0) EA (xp) = 0 φΑ (χρ ) = 0 When using these boundary conditions to solve Equation 24, the following Equation 26 is obtained. (Formula 26) ED = (q / e) ND-x + A (-xn &lt; x &lt; 0)-(q / 2e) ND * x2-A-x + B (-xn &lt; x &lt; 0) ΕΑ =-(q / e) NA-x + C (0 &lt; x &lt; xp) φΑ = (q / 2s) NA * x2-C * x + D (0 &lt; x &lt; xp) In Equation 26, A to D are constants determined by the boundary conditions of Equation 25. When the answer of Equation 26 is brought into the equation of the boundary condition of Equation 25, the following Equation 27 is obtained. (Formula 27)-(q / s) ND.xn + A = 0 -44- This paper size applies Chinese National Standard (CNS) A4 specification (210 X 297 mm) 511273 A7 B7 V. Description of invention (42)

_ (q / 2s) ND-xn2 + Αχη + B = (|) bi + VA = CB = D-(q / e) NA-xp + C = 0 (q / 2s) NA * xp2-C * xp + D = 0 Equation 27 is the equation that determines the six unknowns xn, xp, A, B, C and. By solving this equation, the following formula 28 is obtained. (Equation 28) χη = {2εΝΑ (φΗ + V) / qND (NA + ND)} 1'2 χρ = {2εΝΑ (φΜ + V) / qNA (NA + ND)} 1/2 In addition, the maximum electric field intensity Em ax is The electric field at x = 0 is expressed by the following formula 29. (Formula 29)

Emax = A = (q / e) ND * xn = (2qNA.ND ((() bi + ν) / ε (ΝΑ + ND)) 1/2 The width of the entire depletion layer W = xn + xp is given by the following formula 3 0. (Formula 30) W = {2ε (ΝΑ + ND) ((|) bi + V) /qNA.ND} 1/2 The electric field intensity distribution is shown in Figure 42 (b). Tf ο According to the preliminary review results above, As shown in Figure 43 (a) (b), when reviewing the p-type diffusion layer divided into high acceptor concentration NA and low acceptor concentration na. This is equivalent to -45- This paper size applies the Chinese National Standard (CNS) A4 specification (210X 297 mm) 511273 A7 B7 V. Description of the invention (43 The structure of the drain junction of the unit structure of the embodiment shown in Figure 40. At this time, the junction is also a sudden joint. For comparison with the results of the previous preliminary review , Use the large letter X to represent the distance axis, instead of the small letter X. The front end position Xp of the depletion layer diffused on the p-type diffusion layer exceeds the region of the low acceptor concentration na, thus Xp &gt; L. At this time, the poise The loose formula and the electric field formula divide the p-type diffusion layer into a high acceptor concentration NA region and a low acceptor concentration na region to form the following formula 31. The potential φ A and the electric field EA ′ for the southern acceptor concentration NA region A potential φ a, E a represents a lower region of the receptor concentration na electric field. (Equation 31) is mounted

(12φϋ / άΧ2 =-(q / 2s) ND d2 ^ / dX2 =-(q / 2s) na ά2φΑ / άΧ2 =-(q / 2s) NA ED = -d (j) D / dX (-Xn &lt; X &lt; 0) (0 &lt; X &lt; L) (L &lt; X &lt; Xp) (-Xn &lt; X &lt; 0)

Ea = -d &lt; t &gt; a / dX (0 &lt; X &lt; L)

EA = -άφΑ / dX (L &lt; X &lt; Xp) Order

The boundary conditions are expressed by the following formula 32. (Formula 32) ED (-Xn) = 0 (t &D; D (-) Cn) = φM + V ED (0) = Ea (0) φϋ (0) = φΕ (0) Ea (L) = EA (L ) -46-This paper size applies Chinese National Standard (CNS) A4 specification (210X 297mm) 511273 A7 B7 V. Description of the invention (44) φα (ί) = φΑ (ί) Ε Α (Χρ) = 〇φΑ ( Χρ) = 〇 When formula 3 1 is solved, the following formula 3 3 is obtained. (Formula 33) (-Xn &lt; X &lt; 〇) (-Xn &lt; X &lt; 0) (0 &lt; X &lt; L) (0 &lt; X &lt; L) (L &lt; X &lt; Xp) (L &lt; X &lt; Xp)

ED = (q / B) ND-X + a Φ〇 =-(q / 2s) ND-X2.AX + Β Ea =-(q / s) na-X + C

(q / 2s) na.X2-C.X + D EA =-(q / s) NA.X + E φΑ = (q / 2s) NA.X2 Fine constant of E · X + F. In the following formula 33, A to F are determined by the boundary conditions of formula 32. The answer of formula 33 is brought into the formula 34 in the formula of the boundary conditions of formula 32.

(Formula 34)-(q / s) ND-Xn + Α = Ο-(q / 2s) ND.Xn2 + Αχη + B = (j &gt; bi + V Α = C Β = D-(q / s) na- L + C =-(q / s) NA * L + E (q / 2e) na-L2-C-L + D = (q / 2s) NA * L2-EL + F-(q / B) NA * Xp + E = 0 -47- This paper size is in accordance with China National Standard (CNS) A4 (21〇x 297 mm) 511273 A7 B7 V. Description of the invention (45) (ς / 2ε) ΝΑ × χ2-Ε · χρ + F = 0 Equation 34 is an equation that determines the eight unknowns Xn, Xp, A, B, C, D, E, and WF. By solving this equation, the following equation 35 is obtained. (Equation 35)

Xn = -L- (NA-na) / (NA + ND) + L-((NA / ND) (NA-na) (ND + na) / (NA + ND) 2 + (xn / L) 2) 1 / 2 Xp = (l / NA) * [ND * Xn + (NA-na) -L] Here, xn in Equation 35 shows the depletion layer vs. n-type diffusion layer obtained from the pn junction of Figure 42 previously. Extending, it is expressed by formula 2 8. The electric field when the maximum electric field intensity Emax is X = 0 is expressed by the following formula 36. (Formula 36)

Emax = A = (q / e) ND * Xn The electric field intensity distribution at this time is shown in Figure 43 (b). In Equation 35, when the L pole is close to 0 or the acceptor concentration na is very close to NA, it can be confirmed that Xn = xn. Based on the results of the above review, we will continue to specifically review the optimization conditions for the cell structure in Figure 40. First, Figure 44 shows that the high acceptor concentration of the p-type diffusion layer is NA = 5xl018 / cm3, the low acceptor concentration is na = lxl017 / cm3, and the donor concentration of the n-type diffusion layer is ND = 1 X 102G / cm3, plus When the voltage was V = 2.0V and the ambient temperature was 85 ° C, the relationship between the width L of the low acceptor concentration region and the extensions of the depletion layers Xn and Xp were obtained. In the unit of FIG. 40, when the channel length is 0.1 μm, and the extension of the depletion layer from the source and the drain is symmetrical, in order to avoid punch-through, Xp &lt; 5 X 1 (Γ6 cm -48- Dimensions are applicable to China National Standard (CNS) A4 (210 x 297 mm) 511273

. In order to satisfy this condition, L &lt; 40 × 10-6 em = 〇 〇4 μηι should be used as shown in FIG. 44. In order to retain a certain degree of margin, L = 〇〇 2 _ is more appropriate. At this time, it can be seen that the extension χρ of the depletion layer to the p-type diffusion layer penetrates into the NA region of the high acceptor concentration 〇1 μm.

When the relationship between the maximum electric field strength and the distance L is displayed under the same conditions as in FIG. 44, it is shown in FIG. 45. When the above-mentioned appropriate cut distance [= 〇〇2 μm, the maximum electric field strength is Emax = 9.0xi05 V / cm. This is compared with the case where the region with high osteoblasts / Chendu NA = 5 X l018 / cm3 constitutes the entire condyle region. Although the region is small, the maximum electric field is only weakened by about 1/2. It is best to reduce it to 1/3 of this electric field. Therefore, the effect of reducing the donor concentration 1 ^ 1) of the n-type diffusion layer in FIG. 43 was reviewed. For this reason, the depletion layer is also expected to reduce the maximum electric field strength by extending the end of the diffusion layer. The figure is for Figure 44. When the donor concentration of the n-type diffusion layer 1 ^] 〇 is reduced to ND = lxl0i7 / Cm3, the width of the low acceptor concentration region ^ and the extension of the depletion layer χη, χρ are calculated. The result of the relationship. In addition, FIG. 47 shows the relationship between the maximum electric field strength Emax and the distance L at this time corresponding to FIG. As a result, when the concentration of the source and drain diffusion layers is reduced, when L = 〇 〇25 pm and χρ = 0.03 μιη, the maximum electric field strength Emax = 3 〇χ ι〇5 v / ⑽ can be obtained. The dimensions of the cell structure of Fig. 40 and the extended state of the depletion layer in this optimized condition are shown in Fig. 48. When the concentration of the 11-type diffusion layer at the source and the drain is reduced, a problem arises with respect to the contact resistance thereof. The general implementation of bit line contact of DRAM is to perform diffusion in the contact hole. Or, it is applied to the source and drain diffusion layers -49- This paper size is applicable to the Chinese National Standard (CNS) A4 specification (21 × 297 mm) 511273 A7 B7 V. Description of the invention (47) A metal silicide film is formed on the surface The silicified structure is also effective. However, when the concentration of the n-type diffusion layer of the source and the drain is as low as ND = 1 X 1017 / cm3, as shown in FIG. 48, the depletion layer having a width as large as Xn = 0 · 1 μm also extends to the source and the drain. Inside the polar diffusion layer. In order to suppress such depletion of the source and drain, a so-called LDD structure should be adopted. Corresponding to the unit structure of Fig. 40, the implementation form of the unit structure using the LDD structure is shown in Figs. The stepless diffusion layer 14 is composed of a low donor concentration n-type diffusion layer 14a and a high donor concentration n + type diffusion layer 14b connected to the channel region. The source diffusion layer 15 is also composed of an n-type diffusion layer 15a having a low donor concentration and an n + -type diffusion layer 15b having a high donor concentration connected to the channel region. A metal silicide film 18 is formed on the source electrode, the drain diffusion layer and the gate electrode in a silicide step. However, the L D D structure may be performed only on the terminal of the bit line in the terminal and the source. Secondly, the extension of the depletion layer and the electric field intensity distribution when the cell structure using this LDD structure is specifically reviewed. Figures 50 (a) (b) correspond to Figure 43 (a) (b), respectively, showing the unit structure as a model-type pn junction structure and electric field distribution without extreme junctions. The n-type diffusion layer is composed of a low donor concentration nd region and a high donor concentration ND region, and the p-type diffusion layer is composed of a low acceptor concentration na region and a high acceptor concentration NA region. The width of the low donor concentration nd region is Ln, and the width of the low acceptor concentration na region is Lp. The high donor concentration ND region and the high acceptor concentration NA region have concentrations determined respectively by the resistance required by the bit line contact and the source line contact and the required characteristics of the transistor. The extension of the depletion layer is assumed to constitute a reverse bias bar such as Xp> Lp, Xn> Ln. -50- This paper size applies to China National Standard (CNS) A4 (210X 297 mm).

511273 A7 B7 V. Description of the invention (48) pieces. At this time, the Poisson equation is expressed as the following Equation 37 for Equation 32. Corresponds to the potential φ A and electric field EA in the NA region of high acceptor concentration, and φ a 'E a' to the potential (|) D and electric field in the ND region of low donor concentration na region, respectively. The potential and electric field of ED ^ low donor concentration nd region are &lt; |) d, Ed, respectively. (Formula 37) ά2φϋ / άΧ2 =-(q / 2e) ND (-Xn &lt; X &lt; -Ln) ά2φά / άχ2 =-(q / 2s) nd (-Ln &lt; X &lt; 0) ά2φΕ / άχ2 = (q / 2s) na (0 &lt; X &lt; Lp) ά2φΑ / άχ2 = (q / 2s) NA (Lp &lt; X &lt; Xp) ED = -άφϋ / άχ (-Xn &lt; X &lt; -Ln) Ed = -άφά / άAX (- Ln &lt; X &lt; 0) Ea = -d (j &gt; a / dX (0 &lt; X &lt; Lp) EA = -άφΑ / dX (Lp &lt; X &lt; Xp) The boundary condition is expressed by the following formula 38 (Equation 38) ED (-Xn) = 0 φϋ (-Χη) = φΒί + V ED (-Ln) = Ed (-Ln) &lt; t) D (_Ln) = (j) d (-Ln)

Ed (0) = Ea (0) φά (0) = φα (0)

Ea (Lp) = EA (Lp) -51-This paper size applies to Chinese National Standard (CNS) A4 (210 x 297 mm) 511273 A7 B7 V. Description of the invention (49) (J &gt; a (Lp) = cj ) A (Lp) EA (Xp) = 〇φΑ (χρ) = 〇 When solving Equation 37, we get the following formula 39 (Equation 39) ED = (q / e) ND-X + A φϋ =-(q / 2s ) ND * X2-A * X + Β Ed = (q / s) nd * X + C (-Xn &lt; X &lt; -Ln) (-Xn &lt; X &lt; -Ln) (-Ln &lt; X &lt; 0) φά =- (q / 2e) nd-X2-C * X + D (• Ln &lt; X &lt; 0) Ea =-(q / s) na * X + E (0 &lt; X &lt; Lp) (q / 2s) na-X2 -E * X + F (0 &lt; X &lt; Lp) EA =-(ς / ε) ΝΑ ×× + G (Lp &lt; X &lt; Xp) φΑ = (q / 28) NA-X2-G * X + H (Lp &lt; X &lt; Xp) In Equation 39, A to Η are constants determined by the boundary conditions of Equation 38. Bringing the answer of Equation 39 into the equation of the boundary condition of Equation 38 gives the following Equation 40. (Formula 40)-(q / e) ND-Xn + A = 0

_ (q / 2s) ND-Xn2 + Αχχ + B = (() bi + V

-(q / s) nd-Ln + C =-(q / s) ND-Ln + A-(q / 28) nd * Ln2 + C * Ln + D ==-(q / s) ND * Ln2 + A * Ln + B -52- The paper size is applicable to Chinese National Standard (CNS) A4 specification (210X297 mm) 511273 A7 B7 V. Description of invention (50)

C = E D = F

-(q / e) na * Lp + E =-(q / s) NA-Lp + G (q / 2e) na-Lp2-E * Lp + F = (q / 2s) NA * Lp2-G * Lp + H -(q / s) NA * Xp + G = 0 (q / 2s) NA.Xp2-G.Xp + H = 0 When solving the 10 equations of Equation 40, i0 variables χη, Xp, A ~ Η . The width Ln, Lp of the depletion layer is expressed by the following formula 41. (Formula 41)

Xn = [(ND-nd) Ln- (NA-na) Lp] / (NA + ND) + [l / (NA + ND)] (NA / ND) 1/2. ((NA-na) (ND + na) Lp2. (ND-nd) (NA + nd) Ln2 + 2 (NA-na) (ND-nd) LpLn + (NA + ND) (2s / q) ((|) bi · V)] 1/2 Xp = [(NA-na) Lp- (ND-nd) Ln] / (NA + ND) + [l / (NA + ND)] (ND / NA) 1/2-[(ND-nd) (NA + nd) Ln2 + (NA-na) (ND * na) Lp2 + 2 (ND-nd) (NA-na) LpLn + (NA + ND) (2s / q) ((|) bi + V) 1/2 Electric field strength The distribution is shown in Figure 50 (b). The maximum electric field Emax is 値 at X = 0. The third term in Equation 39 is provided by Equation 42 below. (Formula 42)

Emax = C ~ (q / ε) {NA * Xp- (NA-na) / Lp} The following description takes the specific number to obtain the results of Xp, Xn, and Emax calculated above. _ -53- This paper size applies to China National Standard (CNS) A4 (210X 297 mm) 511273 A7 B7

V. Description of the invention Fig. 51 shows that the high acceptor concentration of the p-type diffusion layer is NA = 5 X 10 8 / cm3, the low acceptor concentration is na = 1 X 1017 / cm3, and the high donor concentration of the n-type diffusion layer is ND = lxl019 / cm3, low donor concentration is nd = 2xi〇17 / cm3, applied voltage is V = 2.0 V, ambient temperature is 85 ° C, and the width of the low donor concentration region is fixed at Ln = 0.03 μηι. The result of the relationship between the width Lp of the low acceptor concentration region and the extension V Xn, Xp of the depletion layer. FIG. 52 is a result of obtaining the maximum electric field strength Emax under the same conditions. According to the above result ', if Lp = 0.025 μm is set, Xp = 0.03, and the maximum electric field strength is Emax = 5.0 x 105 V / cm. Fig. 53 shows the depletion layer diffusion pattern of the cell structure and the size of each part of the graph at the maximum electric field intensity in the electrodeless region. The above analysis of the maximum electric field strength is as shown in Fig. 43, which is lower than that on the drain diffusion layer; when compared with the case layer, it is 1/3 or less. Therefore, as shown in Fig. 4-9, while the surface layer is formed by the high-degree layer and the low-concentration layer, by using the LDD structure of the pole and the source, the maximum electric field strength can be suppressed, the leakage current can be reduced, Make full use of the substrate offset effect. That is, the conditions 1, 2 opposite to the previous ones can be satisfied, and excellent DRAM characteristics can be obtained. Next, a specific manufacturing method for forming the memory cell MC structure shown in Fig. 49 will be described with reference to Figs. 54 to 57. The memory cell of FIG. 49] ^ (: is actually configured as the same cell array as described in FIGS. 3 and 4. That is, the side of the p-type silicon layer 12 perpendicular to the paper surface is connected to the element separation insulating film A pattern is formed as a line-shaped element region, but the description of the element separation step is omitted. As shown in FIG. 54, firstly, the p-type silicon layer ι2 (-54 mm constituting the low-concentration type layer 12a) is used. DESCRIPTION OF THE INVENTION (52) A mask 31 having an opening in an element region is formed on the surface, and a sidewall insulating film 32 is formed on the side wall of the opening of the mask 31. Specifically, the mask 31 is a stacked oxide film and is patterned by RIE. Continue to deposit the silicon nitride film and etch back, leaving the side wall insulating film 32. In this state, boron ions are implanted to form a high-concentration p + -type layer 12b on the P-type silicon layer 12. Next, as shown in tf in FIG. 55, after the sidewall insulating film 32 is selectively removed by etching, a gate insulating film 16 is formed on the surface of the exposed p-type silicon layer 12. Then, a polycrystalline silicon film is deposited, planarized, and the gate electrode 13 is buried. Next, as shown in FIG. 56, the mask 3 丨 is removed by etching. Continuing, the gate electrode 13 is used as a mask to implant ion ions to form low-concentration drain and source diffusion layers 14a and 15a. Continuing, as shown in Fig. 57, a sidewall insulating film 33 is formed on the sidewall of the gate electrode 13. Continuing, human #ions are injected again to form high-concentration electrode and source diffusion layers 14b and 15b. Thereafter, as shown in FIG. 49, a metal silicide film 18 is formed on the drain, source diffusion layers 14b, i5b, and gate 13 through a silicide step. When the drain diffusion layer 14 and the source diffusion layer 5 are not formed, the steps shown in FIG. 57 are not required. That is, in the state of Fig. 56, the memory cell mc shown in Fig. 40 can be obtained. As described above, by applying the damascene method to the formation of the gate electrode, the P + -type layer 12b can be formed in a self-aligned state at the center portion of the channel length direction in the surface area of the transistor. The structure of forming a high-concentration layer in the central part of the surface area of the single crystal transistor is not limited to a structure in which the unit transistor is a plane. FIG. 58A and FIG. 58β show a plan view of a memory cell Mc portion of a third embodiment in which a transistor-shaped semiconductor layer is used to form a 枉 -shaped semiconductor layer and its a_a, and a cross-section ____ 55 Sakimoto Paper Chi Qi Cai _ ϋ_) A view frame (210X 297 mm) A7

Figure &quot; A pillar M layer 49 is formed on ^, and the shell of the sharp layer 49 constitutes a so-called surrounding gate transistor (SGT; Sur_ding Gate

TransmoO. An n + -type source diffused sound 3 is formed at the bottom of the columnar rare layer 49, and a P + -type layer 46 is formed in a state of being sandwiched by the P-type layer 45. An n + type drain diffusion layer 44 is formed on the surface of the columnar silicon layer 49. A gate insulating film 41 is formed on the lateral periphery of the pillar-shaped layer 41, and a gate electrode 42 is formed by enclosing the gate insulating film 41. The gate electrode 42 is formed continuously in one direction and forms a rare line WL. The SGT thus formed is covered by the interlayer insulating film, and a bit line (BL) 48 is formed thereon. The bit line 48 is connected to the n + type diffusion layer ^ The surface area of the memory cell of this SGT structure is also Floating, using the same writing method described in the previous embodiment, dynamic data memory can be performed by keeping excess carriers in the body area or releasing them. Continue, by placing in the body area The impurity concentration and size of the high-concentration 〆-type layer 46 and the low-concentration p-type layer 45 in the central part are optimized. Second, the sufficient & plate bias effect to increase the threshold of the double-threshold voltage difference is also Excellent data retention characteristics to reduce leakage current can be obtained. Figs. 59A and 59B show the fourth embodiment of a transistor / a single DRAM unit structure. Fig. 59A shows the bit line 58 in a dotted line for convenience. Observing the oblique view of the underlying structure, FIG. 59B shows a cross-sectional view along the bit line direction. In the present implementation, the p-type fragmentation layer separated by the fragmented oxide film 51 is $ 2 (this structure is low; Layer 5 2a) In the state of exiting above and on both sides, in seconds An island shape is formed on the plate 〇. Continue, on the top and both sides of the silicon layer 52, through the closed pole -56- This paper size applies the Chinese National Standard (CNS) A4 specification (210X 297 public love) 511273 5. Description of the invention (S4) The insulating film 53 forms a gate 54 to constitute a unit transistor. The gate 54 is continuously patterned in one direction to form a word line WL. In the transistor region of the silicon layer 52, in the length direction of the passivation A P + -type layer 52 having a south concentration is formed in the central portion of the electrode. The drain and source diffusion layers 55 and 56 are composed of low-trace 11-type diffusion layers 55 &amp;, 5 63 and high-concentration 11 + -type diffusion layers 5513,561. LDD structure. The transistor region is covered by an interlayer insulating film 57 on which bit lines 58 are formed. The bit lines 58 are in contact with the wave pole diffusion layer. The surface area of the memory cell in this embodiment is also floating. The same writing method described in the state, | # can be performed by keeping excess 4 carriers in the body area, or releasing it, to perform dynamic data memory. Continue, by arranging in the central part of the body area The impurity concentration of the high-concentration p + -type layer 52b and the low-concentration p-type layer 52 &amp; The degree and size are optimized to obtain a sufficient substrate bias effect to increase the threshold voltage difference of the dual voltage data, and also to obtain excellent data retention characteristics to reduce leakage current. = Brief description with reference to Figure 3 and Figure 4 Unit 2 Column Structure with Unit Unit Area of Servo 2 'Next, a more specific embodiment of the cell array structure and manufacturing method will be described. FIG. 60A is the layout of the cell array, and FIG. 6 is its r cross-sectional view. Fig. A coffee substrate in which an insulating film 102 such as a stone evening oxide film is formed on a stone evening substrate ιo, and a p-type hard layer 103 is formed thereon. The element layer 103 is embedded with the element isolation insulating film 109 in the same manner, and the element formation region is formed into elongated linear shapes along the bit line BL direction, and is divided at a certain pitch on the word line side. ^ Therefore, the transistor is arranged in a moment on the separated silicon layer 10 of the element, that is, the gate electrode 105 is formed on the stone layer 103 and the gate insulating film ⑽ is continuously formed. 57 The scale applies to the Chinese National Standard (CNS) A4 specification (210X297 public love) 511273 A7 ___ _ B7 V. Description of the invention (55) The pattern of the word line WL. The gate electrode 105 is covered with a silicon nitride film 1006 on the upper side and the side surface ′, which is a protective film which can obtain a larger interlayer insulating film which is formed later and the etching selection ratio of 1 i 5. A self-integrated source and non-electrode diffusion layer 107, 108 is formed on the gate 105. The source and non-electrode diffusion layers 107, 108 are formed with an insulating film 102 to the bottom of the silicon layer 103. The side where the transistor is formed is covered with an interlayer insulating film such as a silicon oxide film, and is planarized. On the interlayer insulating film Π 〇, a contact hole 111 for the source diffusion layer 107 is opened in a line shape continuous in the word line WL direction, and a source wiring layer 112 composed of a polycrystalline precious film or W si is buried therein. . The interlayer insulating film 1 10 is buried in the source wiring layer 112, and an interlayer insulating film 1 15 such as a stone oxide film is further formed and flattened. A contact hole 1 16 is formed in the interlayer insulating film η 5 for the electrode diffusion layer 108, and a pin 1 17 such as a polycrystalline silicon film is embedded therein. Continuing, a bit line (BL) 118 crossing the word line WL is formed on the interlayer insulating film 115, and the pin 117 is connected in common. Next, specific manufacturing steps will be described. FIGS. 16A, 61B, and 61C respectively show a plan view at the stage of forming a device isolation insulating film 109 on the p-type silicon layer 10 of the SOI substrate, and M 'and 11-IΓ cross-sectional views thereof. This can be obtained by etching the silicon layer 103 with RIE to form an element isolation trench, and embedding the element isolation insulating film 109 in the element isolation trench. Thereby, the silicon layer 103 is divided into a plurality of line-shaped element formation regions continuous in the direction of the bit line. Figs. 62A, 62B, and 62 are a plan view and a sectional view of I-? And II-1? At the stage of forming an electric crystal on the silicon layer 103, respectively. In other words, a continuous gate 105 forms a pattern of the word line WL through the gate insulating film 104. The top and side surfaces of the gate electrode 105 are covered with a silicon nitride film 106. Specifically, -58 · f paper size is suitable for domestic use (CNS) A4 size (210 X 297 public love) 1 ~~ 511273 A7 B7 5. Invention description (56) The gate protection structure can be adjusted by A laminated film of a polycrystalline silicon film and a silicon nitride film is patterned, and then a silicon nitride film is formed on a sidewall thereof. Continuing, the gate 105 is used as a mask to implant ions to form a source and drain diffusion layer 107, 108 °. Figs. 63A and 63B are substrates formed by covering an element with an interlayer insulating film 110. In this interlayer insulating film A plan view of the formation stage of the embedded source wiring layer n 2 and its γ-γ cross-sectional view. That is, after the interlayer insulating film 11 such as a silicon oxide film is formed flat, a contact hole 111 is formed in the source diffusion layer 107 by RIE in a line-shaped continuous manner parallel to the word line WL. Further, a polycrystalline silicon film is deposited and etched back, and a source wiring layer 112 is buried in the contact hole 111 to form the source wiring layer 112. 64A and 64B show an interlayer insulating film 115 formed on the interlayer insulating film 110 that forms the source wiring layer 112, and the connection of the anti-electrode expansion layer 1 08 is buried on the interlayer insulating film 1 丨 5. The floor plan of Liao 1 1 7 and its I · I, sectional view. That is, after the interlayer insulating film i5, such as a silicon oxide film, is formed flat, a contact hole 116 is opened in the electrode diffusion layer 108 by RIE. Further, a polycrystalline shredded film is deposited, etched back, and pins 1 1 7 are embedded in the contact holes 116 to form. Thereafter, as shown in FIG. 60B, a bit line 118 is formed on the interlayer insulating film ι15 to connect the pins 1 1 7 in common. As described above, the word line WL and the bit line BL are formed at a pitch of the minimum processing size F. As shown by a single-dot broken line on FIG. 60A, a DRAM cell array having a 4F2 cell area can be obtained. When the element separation structure shown in FIG. 6A is used, although the source extension layer 107 is dispersedly formed in the direction of the word line WL, in this embodiment, the source wiring layer 1 1 2 can be formed to connect the same The source diffusion layer 107 obtains a low-resistance common source line. _ -59- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm)

Binding

The contact holes 111 of the source wiring layer 112 and the contact holes 116 for the bit line pins 117 are self-integrated on the gate 105 protected by the silicon nitride film 106. Therefore, in the RIE step of contact hole processing, by making the mask opening larger than F, the contact hole can be formed without being affected by the misalignment of the mask. As shown in FIG. 64A, the contact hole U6 of the bit line of the above embodiment is formed only on the electrode diffusion layer 108. In addition, as shown in FIG. 65, the contact holes 116b of bit lines may be formed in a line shape continuous in the word line W L direction in the same manner as the contact holes 1 1 1 of the source electrode. At this time, although the pin 117 of the bit line is also embedded in a line shape, it must be left only under the bit line B L in the end. At this time, after forming the bit line BL pattern, the bit line BL can be used as a mask to etch the pins 1 1 7. · In the above embodiment, when the top and side surfaces of the source wiring layer 112 are covered with a protective film in the same manner as the gate 105, the margin of the bit line contact alignment must be greater. This embodiment will be described below. The steps before the element formation step of FIG. 62B are the same as those of the previous embodiment. 'Only the sections corresponding to the section of FIG. 62B will be used to describe the subsequent steps. First, as shown in FIG. 66, an interlayer insulating film 201 such as a silicon oxide film is deposited on a substrate on which an element is to be formed, and then planarized by etching. At this time, the silicon nitride film 106 covering the gate electrode 105 is etched as a stopper film, and an interlayer insulating film 201 is buried in the gate gap. After that, as shown in FIG. 67, contact holes for the source and drain diffusion layers 107, 108 are opened in the interlayer insulating film 201, and the pins 202 are buried by polycrystalline silicon deposition and etchback, respectively. 203. When opening a contact hole with RIE, if a mask with continuous line-shaped openings in the direction of the bit line BL is used, the gate electrode -60- This paper size applies the Chinese National Standard (CNS) A4 specification (210X 297 mm)

Equipment ______ — —_ B7 V. Description of the Invention (58) The gap of 105 is formed with a self-integrated contact hole. However, the pins 202 on the source diffusion layer 107 are the same as those in the previous embodiment, and may be parallel to the word line wL. After that, as shown in FIG. 68, a pattern of a source wiring layer 204 which is commonly connected to the pins 202 on the source diffusion layer 107 in the word line WL direction is formed. The upper and side surfaces of the source wiring layer 204 are covered with a silicon nitride film 205 of a protective film. Specifically, the 'child protection structure' can be obtained by forming a multilayer film pattern of a polycrystalline silicon film and a silicon nitride film ', forming the source wiring layer 204, and forming a silicon nitride film on the side surface thereof. Next, as shown in FIG. 69, an interlayer insulating film 206 such as a silicon oxide film is deposited again and planarized. Continuing, a bit buried wiring trench and a contact hole are formed on the interlayer insulating film 206 by the dual damascene method, as shown in FIG. 70, the buried bit line 207 is embedded. In this embodiment, since the periphery of the source wiring layer 204 is protected by the silicon nitride film 205, the width in the direction of the bit line in which the bit line contacts can be made sufficiently large. Thereby, a low-resistance bit line contact can be adopted without being affected by the misalignment. As shown in FIG. 61A, the two embodiments described above are divided into linear continuous element formation regions. Therefore, each element formation region is discontinuous in the word line direction. In addition, as shown in FIG. 71, the linear element formation region may be divided into element formation regions at positions where the source diffusion layers are formed so as to be connected in the word line direction. In this case, the 'source diffusion layer itself is continuously formed in the word line direction to form its own common source line. At this time, the source wiring layer 112 can also be formed as in the above embodiment, which also helps to share the source line. Reduced resistance. -61-This paper size applies the Chinese National Standard (CNS) A4 specification (21 × 297 mm) 511273 A7 B7 V. Description of the invention (59) The present invention is not limited to the above embodiment. In the embodiment, an N-channel MOS transistor formed on a P-type silicon layer is used. However, a P-channel MOS transistor formed on an n-type silicon layer is used as a memory unit. Dynamic memory can also be performed by the same principle. . At this time, many carriers are electrons, using storage and release on the surface area of the electrons. In addition, in the embodiment, an SOI substrate is used. However, a MOS transistor using a floating semiconductor layer separated by ρη bonding can also form a memory cell with the same principle. As described above, various embodiments of the present invention can provide a semiconductor memory device that can form a memory cell with a simple transistor structure and perform dynamic memory of dual data with fewer signal lines. -62- This paper size applies to China National Standard (CNS) A4 (210X 297mm)

Claims (1)

Patent application scope A semiconductor memory device: a transistor semiconductor layer constituting a memory unit, which is a first conductivity type separated from a floating state; a drain diffusion layer, which is a semiconductor layer of a second conductivity type, connected As for the bit line, the transistor includes: n and other memory cells are electrically formed on the first conductive power source diffusion layer, which is a semiconductor layer of the second conductivity type and the drain electrode; and It is formed on the first conductive dispersion layer and connected to the source line gate. It is formed on the semiconductor layer between the drain diffusion layer and the source diffusion layer via a gate insulating film, and is connected to the word center. The transistor has: the first data state, which has a first-threshold threshold voltage of a number of carriers that have an excess on the semiconductor layer; and the third phase, which has a first threshold of excess release on the semiconductor layer. Two threshold voltages. 2. If the semiconductor memory device of scope i of the application _ item, wherein the above-mentioned data state causes the impact ionization in the vicinity of the drain junction by operating the transistor described above, excess ion generated by the impact ionization will be generated. Many carriers are held on the semiconductor layer, the second data state imparts a forward bias between the semiconductor layer and the drain diffusion layer, and the excess carriers in the semiconductor layer are discharged from the drain diffusion layer. 3. For a semiconductor memory device according to item 丨 of the application, wherein -63- 511273 6. Scope of patent application The upper semiconductor layer is a silicon layer formed on a silicon substrate through an insulating film. 4. The semiconductor memory device according to item 3 of the patent application, wherein the upper silicon layer is a p-type, and the transistor is an N-pass MOS transistor. 5. The semiconductor memory device according to item 丨 of the application, wherein the potential of the source line is fixed. 6. The semiconductor memory device according to item 5 of the scope of patent application, where ^ when data is written, ^ use the source line as a reference potential, and assign a word line above the reference potential to the word line of the selected transistor. A potential, a second potential lower than the reference potential is provided on the t-line of the non-selected transistor, and a third potential higher than the reference potential is provided on the bit line when the first data state is written The potential is given a fourth potential lower than the reference potential when the second data-like complaint is written. 7. The semiconductor memory device according to item 1 of the scope of patent application, wherein the source line is used as a reference potential when data is read out, and the word line of the selected transistor is given, and the voltage is set at the first threshold voltage. And a fifth potential higher than the second threshold voltage and higher than the reference potential to detect the conduction / non-conduction of the selected transistor. 8. The semiconductor memory device according to item 7 of the patent application scope, wherein the semiconductor layer includes a first impurity-added region, which is connected to the non-polar diffusion layer and the upper paper standard (CNS) A4 Specifications ⑽χ 297 公 爱)-'-, ί ----------- ^ --------- (Please read the notes on the back before filling out this page) Intellectual Property Bureau, Ministry of Economic Affairs Printed by Employee Consumer Cooperative Co., Ltd. 511273, the source diffusion layer is described in the scope of the patent application; and the second impurity addition region is configured separately from the drain diffusion layer and the source diffusion layer, and is connected to the first impurity addition region, and has The impurity concentration is higher than the above-mentioned first impurity addition region. 9. If the semiconductor memory device according to item 丨 of the patent application, wherein the source line is used as a reference potential when data is read out, it is given on the word line of the selected transistor, which is higher than the above first and second lines. The threshold voltage is a fifth potential higher than the reference potential, and the continuity of the selected transistor is detected. 10. The semiconductor memory device according to item 9 of the patent application scope, wherein the semiconductor layer includes: a first impurity added region, which is connected to the drain diffusion layer and the source diffusion layer; and, a second impurity added line The region is separated from the drain diffusion layer and the source diffusion layer, is connected to the first impurity-added region, and has a higher impurity concentration than the first impurity-added region. 11. The semiconductor memory device according to item i of the application, wherein the semiconductor layer includes a first impurity-added region that is connected to the drain diffusion layer and the source diffusion layer; and a second impurity-added region, It is arranged separately from the above-mentioned and the source diffusion layer and the source diffusion layer, and is connected to the first impurity-added region, and has an impurity concentration that is lower than the first impurity-added region. -65- This paper size applies to China National Standard (CNS) A4 specifications x 297 Gongai A8 B8 C8 D8 Patent Application Scope 12 · If you apply for a semiconductor memory device with the scope of patent application item 11, among them (Please read the precautions on the back before (Fill in this page) At least the drain diffusion layer of the drain diffusion layer and the source diffusion layer includes: a third impurity added region, which is connected to the first impurity added region to form a pn junction; and a fourth impurity added The region is formed separately from the above-mentioned first impurity-added region and has an impurity concentration higher than the above-mentioned third impurity-added region. 13. As in the case of a semiconductor memory device under the scope of patent application No. 1, in reading data, the After the high word line is higher than the second threshold threshold voltage, a certain current is poured into the bit line to detect the potential difference generated on the bit line. Private 14. If the scope of patent application is the first! In the semiconductor memory device, when the data is read, the word line is raised above the second threshold voltage, and the bit line is maintained at a certain voltage and the current required to flow into the clamp is detected. Current difference. 15 · Semiconductor memory device according to the scope of application patent No. 丨 3, wherein the semiconductor layer includes the first impurity-added region printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, which is connected to the drain diffusion layer and the source An electrode diffusion layer; and a second impurity added region, which are separately disposed from the drain diffusion layer and the source diffusion layer, are connected to the first impurity added region, and have a higher impurity concentration than the first impurity added region . 16. If you apply for a semiconductor memory device with the scope of patent application No. 丨 4, in which -66 paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 6. The scope of the patent application is connected to the drain diffusion layer And the above semiconductor layer includes a source diffusion layer including a first impurity added region; and a plutonium-impurity added region, which is separated from the drain diffusion layer and the source diffusion layer, and is connected to the first impurity added region; And has the impurity concentration in the above-mentioned _ impurity added region. 17. For example, the semiconductor memory device of the first patent application park, wherein a plurality of sensing amplifiers are provided on several bit lines, and from these bit lines, One of the selected bit lines is connected to the above-mentioned sense amplifier. 18. A semiconductor memory device comprising: an SOI substrate, which is formed with a silicon layer on a silicon substrate through an insulating film; and several transistors, which The two transistors are formed on the silicon layer, and the two transistors sharing the drain diffusion layer are separated in the channel width direction and arranged in a matrix. Several rare wires are connected in common. On the gates of the transistors juxtaposed in the first direction; a number of bit lines arranged in a second direction crossing the first direction to be connected to the drain diffusion layer of the transistor; and a common source Line, which is formed by the continuous arrangement of the source diffusion layers of the transistors juxtaposed in the first direction; wherein the transistor has: a first data state, which has a large amount of excess remaining on the silicon layer; The first threshold voltage of the carrier; and the second data state, which has a number of -67- above which are released from the excess of the carrier on the silicon layer. This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm). ) 511273 A8 B8 C8 D8 Printed by the Consumers 'Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs' Applicable patent scope two threshold voltages. 19. If a semiconductor memory device with the scope of patent application No. 18, where the minimum processing size is F, an electrical The crystals are arranged in a matrix with a unit size of 邛 χ 2f. 20. The semiconductor memory device according to item 18 of the scope of patent application, wherein the above-mentioned drain diffusion layer and the above-mentioned The source diffusion layer is formed to a depth of the above-mentioned insulating film under the above-mentioned silicon layer. ㈢ 21. The semiconductor memory device according to item 18 of the patent application range, wherein the first data state is operated by operating the transistor above the drain electrode. Impact ionization is caused in the vicinity of the junction, and an excessive number of carriers generated by the impact ionization are held on the silicon layer, and the second data state imparts a forward direction between the silicon layer and the drain diffusion layer. Bias, the excess carrier in the above-mentioned silicon layer is drained out of the drain diffusion layer. 22. For example, the semiconductor memory device of the scope of application for patent No. 21, wherein the above-mentioned silicon layer is p-type, and the above-mentioned transistor is 1 ^ channel 1 ^ 〇8 transistor. 23. The semiconductor memory device according to claim 18, wherein the potential of the common source line is fixed. 24. The semiconductor memory device according to item 23 of the patent application, wherein the data is written with the common source line as a reference potential, and a word higher than the reference potential is given to the word line of the selected transistor. Potential, ,, is given on the non-selected transistor's word line to -68 below the above-mentioned reference voltage p-This paper size applies to Chinese National Standard (CNS) A4 specifications ⑽χ 297 issued) (Please read the precautions on the back before (Fill in this page) Click on the --------------- line — -nn H n H ϋ n. 511273 is8 —_§ 6. The scope of patent application is one potential, one is written in the above In the case of the first data state, a third potential at the reference potential is given to the bit line, and a fourth potential lower than the reference potential is given when the second data state is written. 25. The semiconductor memory device according to item 18 of the scope of patent application, wherein when data is read out, the common source line is used as a reference potential, and the word line is selected on the selected transistor, and the first threshold is Between the voltage and the second threshold voltage, and a fifth potential higher than the reference potential, the conduction / non-conduction of the selected transistor is detected. 26. The semiconductor memory device according to item 18 of the scope of patent application, wherein when data is read out, the above-mentioned common source line is used as a reference potential and is given on the word line of the selected transistor, which is higher than the above-mentioned first and first The second threshold voltage is a fifth potential higher than the reference potential, and the continuity of the selected transistor is detected. 27. The semiconductor memory device according to item 25 of the patent application scope, wherein the above-mentioned Shi Xi layer includes: the first impurity adding region of printed clothing of the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, which is connected to the drain diffusion layer and the source An electrode diffusion layer; and a second impurity added region, which are separately disposed from the drain diffusion layer and the source diffusion layer, are connected to the first impurity added region, and have an impurity concentration that is trapped in the first impurity added region . 28. The semiconductor memory device according to item 26 of the patent application, wherein the above-mentioned silicon layer of the patent application includes: a first impurity addition region, which is connected to the drain diffusion layer and the source diffusion layer; The second impurity added region is disposed separately from the drain diffusion layer and the source diffusion layer, is connected to the first impurity added region, and has an impurity concentration that is lower than the first impurity added region. 29. For the semiconductor memory device with the scope of patent application No. 丨 8, when the data is read, the word line of the selected transistor is raised to a voltage higher than the first threshold voltage, and a certain current flows into the bit line. The potential difference generated on the bit line of the selected transistor is detected. 30. If the semiconductor memory device according to item 18 of the scope of patent application is applied, when the selected transistor is raised, the word line of the two selected transistors is raised to a voltage higher than the above-mentioned second threshold voltage, and then the selected transistor is positioned. The element wire waits for a certain voltage, flows the required current into the clamp, and detects its current difference. 31. The semiconductor memory device according to item 29 of the application, wherein the fragmented layer includes: a first impurity-added region, which is connected to the drain diffusion layer and the source diffusion layer; and a second impurity-added region, It is arranged separately from the non-electrode diffusion layer and the upper electrode diffusion layer, and is connected to the first-doped f added region having an impurity concentration higher than that of the first impurity added region. 32. If the semiconductor memory device according to item 30 of the scope of patent application, the fragmentary layer contains the first impurity addition region which is connected to the drain diffusion layer and the upper -70- 511273 A8 B8 C8 D8. A source diffusion layer; and a second impurity-added region, which is separated from the upper-diffusion electrode layer, and the first-impurity-added region is connected to the impurity concentration of the first impurity-added region. 33. If the semiconductor memory device under the scope of patent application is applied, when the data is read out, the selected thunder is given to-? Shibuo <〈After the sub-line is higher than the above-mentioned first limit of the turtle pressure, a certain current is flown into the selected line, and the detection is made on the bit line. 34. If the semiconductor device in the 24th scope of the patent application is applied, and the data is read, the word line of the selected transistor is raised; after the voltage is higher than the above threshold, the selected transistor will be used. The bit line maintains a certain voltage, and the required current flows into the clamp, and the current difference is detected. 35. The semiconductor memory device according to item 33 of the application, wherein the fragmentation layer includes: a first impurity-added region, which is connected to the drain diffusion eyebrow and the source diffusion layer; and Two impurity-adding areas, which are separated from the polar diffusion layer, are connected to the above-mentioned polar diffusion layer, and are connected to the above-mentioned printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. The impurity concentration is higher than the above-mentioned first impurity addition region. 36. The semiconductor memory device according to claim 34 in the scope of patent application: wherein the above-mentioned layer includes: a first impurity adding region which is connected to the drain diffusion layer and the source diffusion layer; and a second impurity addition Area, its line of blood F 4-P '77 ^ MH and polar diffusion layer with the above source 71-This paper size applies Chinese National Standard (CNS) A4 specifications (21〇X 297 g t) 511273 A8 B8 C8 _______ D8 6. Scope of Patent Application: The Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs prints a polarized layer separation configuration, which is connected to the above-mentioned impurity-added region and has an impurity concentration higher than that of the above-mentioned first impurity-added region. 37. The semiconductor memory device according to item 18 of the patent application, wherein several 7G lines are each provided with a sense amplifier, and a bit line selected from the bit lines is connected to the above-mentioned sense amplifier. 38 · A semiconductor memory device comprising: an SOI substrate formed with a silicon layer on a silicon substrate via an insulating film; and a plurality of transistors having an array arranged on the silicon layer in a matrix form on the top and sides In the state covered by the protective film, a gate electrode formed in a continuous zigzag pattern in one direction; and a pole drain and a diffusion layer formed by self-integration with the gate electrode; The first interlayer insulating film, which is covered The above-mentioned transistors; a source wiring layer, which is buried on the source diffusion layers of the above-mentioned transistors, and is embedded in the first interlayer insulating film and connected to the word line in a line-like first contact hole; Inside; a second interlayer insulating film, which is formed on the upper 7L wire pin of the first interlayer insulating film, is formed on the drain diffusion layer of each transistor, and is buried in the second interlayer insulating film and opened A second contact hole; and a bit line 'which is arranged on the second interlayer insulating film crossing the word line' is connected to the drain diffusion layer of the transistor via the bit line pin, wherein the above The transistor has: Information status, which has the above table body _-72-^ Paper size applies Chinese National Standard (CNS) A4 specifications (210 x_i97 public love) ---- (Please read the precautions on the back before filling this page). Click. Order! line! -n I nn ϋ nnn _ 511273 _ ~ § 6. The second data state of the many carriers remaining in the area covered by the patent application has the above-mentioned table # / 匕 私 压; and 罘 released to the drain diffusion layer The second threshold is the threshold voltage. Xi Xizai-39. If the silicon layer of the above-mentioned SOI substrate of the semiconductor memory device of the 38th area of the application for a patent is divided by a knife edge fe, the book is divided in a certain pitch in the direction of the word line-knife J A line-shaped element formation region is connected in the direction of the above-mentioned lines. 8. 40. If you apply: The semiconductor memory device according to Item 38, in which the 罘 -lean material state causes the ionization of impact near the junction of the drain electrode by operating the transistor, and will be generated by the impact ionization. Many of the excess carriers are maintained on the hard layer, and the second data state imparts a lateral offset between the silicon layer and the drain diffusion layer, and the excess carriers in the silicon layer are discharged from the drain diffusion layer. 41. The semiconductor memory device according to item 38 of the application, wherein the silicon layer is p-type, and the transistor is an N-channel MOS transistor. 42. The semiconductor memory device according to claim 38, wherein the potential of the source wiring layer is fixed. 43. If the semiconductor memory device according to item 38 of the scope of patent application, when the data is read out, the source wiring layer is known as the reference potential, and is given on the word line of the selected transistor, within the first threshold. Between the chirp voltage and the second threshold chirp voltage, which is higher than the reference potential, the conduction / non-conduction of the selected transistor is detected. _______ -73- This paper size is applicable to τguan standard (CNS) A4 specifications ⑵Q χ4 (Please read the precautions on the back before filling this page) Order --------- line 丨 «Intellectual Property of the Ministry of Economic Affairs Printed by the Consumer Cooperative of the Bureau of the People's Republic of China 6. Application for patent coverage 8888 ABCD Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 44. For example, the semiconductor memory device with the scope of patent application No. 38, where the above-mentioned source wiring layer is made when data is read out It is a reference potential, which is given on the word line of the selected transistor, a potential higher than the first and second threshold threshold voltages, and higher than the reference potential, and the continuity of the selected transistor is detected. 45. The semiconductor memory device according to item 38 of the scope of patent application, wherein when data is read, the word line is raised to a voltage higher than the second threshold voltage, a certain current flows into the bit line, and the bit line is detected. Generate a disparity. Private 46. If the semiconductor memory device of the 38th scope of the application for the patent, where / in the data reading, raise the word, line to a voltage higher than the above-mentioned second threshold, 'to keep the bit line a certain voltage, and flow into the clamp The required current, and the difference in current is detected. 47. The semiconductor memory device according to item 38 of the scope of patent application, wherein a plurality of sensing amplifiers are provided on each of the plurality of bit lines, and one bit line selected from these bit lines is connected to the above-mentioned sense amplifier. . 48 · A semiconductor memory device comprising: an SOI substrate, which is formed with a silicon layer on a silicon substrate via an insulating film; a plurality of private θ-shaped bodies, which are arranged in a matrix on the silicon layer, above and In a state where the side surface is covered by the first protective film, a gate electrode having a zigzag pattern continuous in one direction is formed; and a source drain electrode and a diffusion layer formed by self-integration with the gate electrode; a first interlayer insulating film, which It covers the above-mentioned several transistors; I paper-scale paper towels 'read_φ ((: Ν3) Α4 size⑵ -74- 297 mm) ·!' ------- II ------ --I -Order --------- Line 丨-(Please read the notes on the back before filling this page) I nn · 1 · 511273 The source pin is embedded in the contact hole formed on the source diffusion layer of the transistors of the interlayer insulating film; the non-terminal pin is embedded in the each of the interlayer insulating films. In the contact hole on the drain diffusion layer of the transistor; the source wiring layer is connected to the source pins arranged in the word line direction, and the upper and side surfaces are covered by a second protective film; the second interlayer insulation A film that covers the source wiring layer; and a bit line that is arranged on the second interlayer insulating film crossing the word line and connected to the drain diffusion layer of the transistor through the drain pin Wherein, the transistor has: a first data state having a first threshold voltage of a plurality of carriers remaining in excess on the surface of the watch body region; and a second data state having a plurality of excess data in the above body region The carrier is released to a second threshold voltage of the drain diffusion layer. 49. The semiconductor memory device according to item 48 of the patent application, wherein the silicon layer on the SOI substrate is separated by an element insulation film, and is divided in a direction of the word line in a direction of the word line at a certain interval. The linear element forms a region. 50. The semiconductor memory device according to claim 48 of the patent scope, wherein the first data state is loaded by operating the transistor to cause impact ionization in the vicinity of the drain junction, and will be generated by the impact ionization. Many excess carriers remain on the fragmented layer, and the second data state is between the silicon layer and the drain diffusion layer -75-This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) ) Hold Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 3112/3 6. Scope of patent application The forward bias is given, and many of the carriers in the above silicon layer are excluded from the diffusion layer. "And 51. The semiconductor memory device according to item 48 of the patent application, wherein the fragmented layer is p-type, and the transistor is an N-channel MOS transistor. 52. The semiconductor memory device according to claim 48, wherein the potential of the source wiring layer is fixed. 53. The semiconductor memory device according to item 48 of the scope of patent application, wherein the source wiring layer is used as a reference potential when data is read, and is given on the word line of the selected transistor, within the first threshold. Between the voltage and the second threshold voltage, and a potential higher than the reference voltage, the conduction / non-conduction of the selected transistor is detected. 54. For example, the semiconductor memory device under the scope of application for patent No. 48, in which the above-mentioned source wiring layer is used as a reference potential when data is read out, and is given on the word line of the selected transistor, which is higher than the first and the above-mentioned word lines. Two threshold voltages, and a potential lower than the reference potential, detect the continuity of the selected transistor. 55. For example, the semiconductor memory device under the scope of patent application No. 48, in which the word line is raised above the second threshold voltage when the data is read, a certain current flows into the bit line and Potential difference. 56. If the semiconductor memory device under the scope of patent application No. 48, when the data is stated, the south word line is higher than the above-mentioned second threshold threshold voltage -76- 210 X 297 mm) m --- · ---.-------- xin -------- order --------- line * {Please read the back Zhuyin? Please fill in this page for matters) Α8 Β8 C8 D8 Scope of patent application After printing by the Intellectual Property Office of the Ministry of Economic Affairs, the Consumer Electronics Co., Ltd. keeps the bit line at a certain voltage and flows into the current required by the clamp to detect its current difference. 57. The semiconductor memory device according to item 48 of the claim, wherein each of the bit lines is provided with a sense amplifier, and a bit line selected from the bit lines is connected to the above-mentioned sense amplifier. 58 · A method for manufacturing a semiconductor memory device, comprising: forming an insulating film on a semiconductor substrate; forming a semiconductor layer of a first conductivity type on the insulating film; and forming a mask with an opening in a gate formation region on the semiconductor layer Film 5 forms a side wall insulating film on the opening side wall of the mask, and through the opening of the mask, an impurity is added to the semiconductor layer to form a first conductivity type impurity layer with an impurity concentration higher than that of the semiconductor layer. " After the sidewall insulating film is removed, a gate insulating film and a gate are buried in the openings above the mask to form a plurality of openings. After removing the mask, impurities are added to the semiconductor layer to form a second conductivity type drain diffusion. Layer and source diffusion layer 59. A method for manufacturing a semiconductor memory device, comprising: forming an insulating film on a semiconductor substrate; forming a semiconductor layer of a first conductivity type on the insulating film; and forming a gate on the semiconductor layer A mask with an opening in the electrode formation area forms a first sidewall insulation film on the opening sidewall of the above mask, ______ _77_ This paper Ruler applies to China National Standard (CNS) A4 specifications (210 X 297 public love (please read the precautions on the back before filling out this page) Release 11 --- line 丨 «511273 A8 B8 C8 D8 Through the opening of the mask, impurities are added to the semiconductor layer to form a first impurity-added layer of a first conductivity type having an impurity concentration higher than that of the semiconductor layer. After removing the first sidewall insulating film, A gate insulating film and a gate are buried in the upper openings. After removing the mask, an impurity is added to the semiconductor layer, and a second conductivity-type second impurity-added layer is formed on the drain region and the source region. A second sidewall insulating film is formed on the non-electrode side wall, impurities are added to the semiconductor layer, and first-conductivity-type first-concentration-type first-conductivity-type-concentrations are formed on the drain region and the source region. Three impurity added layers. (Please read the precautions on the back before filling this page) Order ---- 1 ---- Line 丨 Printed by the Staff Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs-78- This Zhang scale applicable Chinese National Standard (CNS) A4 size (210 X 297 mm)