JP2007141958A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress the reduction of holes accumulated in a channel body during reading/writing operations of the other memory cell. <P>SOLUTION: A semiconductor device is composed by using a double SOI substrate having insulating films 12, 14. A silicon layer 15 is made as the channel body so as to form a gate electrode 45 on the surface of the silicon layer 15 via a gate insulating film 44. A source diffusion layer 46 and a drain diffusion layer 47 are formed at a depth reaching the insulating layer 14 so as to obtain a memory cell MC. A contact plug 48 for applying a substrate bias voltage to a silicon layer 13 is embedded as in a state of penetrating the silicon layer 15 and the insulating film 14. The substrate bias voltage is applied to the silicon layer 13 corresponding to each memory cell MC by a word line unit. A local insulating film 50 is formed extendingly in a word line direction so as to separate the silicon layer 13 corresponding to each memory cell MC by a word line unit. The substrate bias voltage is set to a value capable of preventing the reduction of the holes accumulated in the channel body during non-writing and during non-reading. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device having a memory. Specifically, in the present invention, a first insulating film, a first semiconductor layer, a second insulating film, and a second semiconductor layer are formed in this order on a semiconductor substrate, and are formed in the second semiconductor layer. A memory cell composed of a MISFET having a floating channel body and a gate for forming a channel formed on the surface side of the channel body is provided, and a substrate bias voltage is applied to a first semiconductor layer corresponding to the memory cell. By providing a bias voltage application unit for applying a voltage, it is possible to suppress a decrease in majority carriers accumulated in the channel body during read / write operations of other memory cells without affecting characteristics other than the memory region. This relates to a semiconductor device.

  Conventionally, an FBC (Floating Body Transistor Cell) memory has been proposed as a memory that can be formed on an SOI (Silicon On Insulator) substrate.

  FIG. 16 shows a structure of a normal SOI substrate 30. This SOI substrate 30 has a structure in which a silicon layer (silicon single crystal film) 33 is formed on a silicon substrate 31 via an insulating film 32. This SOI substrate is manufactured by a well-known SIMOX (Separation by IMplanted OXygen) method, a bonding method, or the like.

  FIG. 17 shows a principle configuration of an FBC memory cell MC (b) that is a memory cell constituting the above-described FBC memory. An SOI substrate in which a p-type silicon layer 303 is formed on a silicon substrate 301 via an insulating film 302 such as a silicon oxide film is used.

  Using the silicon layer 303 as a channel body, a gate electrode 305 is formed on the surface of the silicon cell 303 via a gate insulating film 304, and a source diffusion layer 306 and a drain diffusion layer 307 are formed to a depth reaching the insulating film 302. An n-channel MISFET (Metal Insulator Semiconductor Field Effect Transistor) as (b) is configured.

  Each memory cell MC (b) is arranged in a matrix with floating channel bodies that are separated from each other, and a cell array 308 is formed as shown in FIG. In this case, the drain 307 is connected to the bit line BL, the gate electrode 305 is connected to the word line WL, and the source 306 is connected to a fixed potential line such as a ground line.

  The operation principle of the memory cell MC (b) utilizes hole accumulation, which is the majority carrier of the channel body (p-type silicon layer 303) of the MISFET. That is, by operating the MISFET as a pentode, a large channel current flows from the drain 307 and impact ionization occurs near the drain junction.

  Excess majority carriers (holes) generated by the impact ionization are held in the channel body, and the state is set to, for example, data “1”. Data “0” is defined as a state in which a forward current is caused to flow between the drain 307 and the channel body to discharge excess holes in the channel body to the drain.

  Data “0” and “1” are channel body potential differences, and are stored as MISFET threshold differences. That is, as shown in FIG. 19, the threshold value Vth1 in the data “1” state where the channel body potential Vbody is high due to hole accumulation is lower than the threshold value Vth0 in the data “0” state where the channel body potential is low.

  In order to stably hold the data “1” in which holes are accumulated in the channel body, it is preferable to hold the voltage VWL applied to the word line WL negative. This data holding state does not change even if a read operation is performed unless a reverse data write operation is performed. That is, unlike a one-transistor / one-capacitor DRAM that uses capacitor charge retention, nondestructive reading is possible.

  Data reading is basically performed by detecting a difference in conductivity between the memory cells MC (b). Since the relationship between the word line voltage VWL and the body potential Vbody is as shown in FIG. 19 described above, for example, an intermediate read voltage between threshold values Vth0 and Vth1 of data “0” and “1” is applied to the word line WL. Thus, data can be detected by detecting the presence or absence of current in the memory cell. Alternatively, data can be detected by applying a voltage exceeding the threshold values Vth0 and Vth1 to the word line WL and detecting the magnitude of the current of the memory cell.

  20A and 20B show the write operation of the memory cell MC (b). FIG. 20A shows a write operation of data “1”. In the state where a high positive voltage is applied to the word line (gate) WL, a high positive voltage is applied to the bit line (drain) BL, and as described above. Impact ionization occurs near the drain junction, accumulating holes in the channel body. FIG. 20B shows a write operation of data “0”. In the state where a high positive voltage is applied to the word line (gate) WL, a negative voltage is applied to the bit line (drain) BL, and the channel body (p-type) is applied. The pn junction between the silicon layer 303) and the drain 307 is forward-biased, and holes are discharged from the channel body 303.

  21A and 21B show the read operation of the memory cell MC (b). FIG. 21A shows a read operation of data “1” and data “0”. The data is destroyed by impact ionization on the bit line (drain) BL in a state where a high positive voltage is applied to the word line (gate) WL. Apply a low positive voltage to avoid this. FIG. 21B shows the relationship between the drain current Ids and the gate voltage Vgs at the time of reading. For example, a voltage VWLread exceeding the threshold values Vth0 and Vth1 is applied to the word line WL, a drain current difference ΔIds (= I1−I0) corresponding to the difference between the threshold values Vth0 and Vth1 is detected by a sense amplifier, and data “0” is detected. "," 1 "is identified.

  The memory cell MC (b) described above responds to the voltage change of the bit line (drain) BL during the operation of reading / writing data of other parts, that is, when a negative voltage is applied to the word line (gate) WL. As a result, a phenomenon that holes accumulated in the channel body decrease (pass / gate leakage phenomenon in the MOS transistor) occurs.

  As shown in FIG. 18, in the cell array 308, a plurality of memory cells MC (b) are arranged in a matrix, and the drain 307 of each memory cell MC (b) is connected to the bit line BL for each column. The gate electrode 305 of the cell MC (b) is connected to the word line WL for each row.

  For example, a high positive voltage is applied to the word line WL-2, a positive and negative voltage is applied to the bit line BL-2, and data “1” and “0” are applied to the memory cell MC (b) -m to be written. When data is written, the drain voltage of the other memory cell MC (b) -s connected to the bit line BL-2 fluctuates and a leak current flows to the gate, so that the memory cell MC (b)- When holes are accumulated in the channel body of s, the holes flow out of the channel body.

Therefore, for example, in Patent Document 1, an auxiliary gate composed of an n ⁺ type layer capacitively coupled via an insulating film is provided on the back surface of the channel body (p-type silicon layer), and a substrate bias voltage (negative) is applied to the auxiliary gate. It has been proposed to stabilize the hole holding by applying a voltage of (1).

JP 2003-31693 A

  However, in the configuration of Patent Document 1, a substrate bias voltage is applied to a silicon substrate of a normal SOI substrate (see FIG. 16). For example, in an SOC (System On Chip) device, the same substrate bias voltage as that in the memory region is applied to other regions that are not the memory region, and the optimum substrate bias voltage is set between the memory region and the other region that is not the memory region. If they are different, optimum characteristics cannot be obtained in each region.

  Further, in the configuration of Patent Document 1, the substrate bias voltage is applied to the silicon substrate, and the portion to which the substrate bias voltage is applied is exposed, so that the substrate bias voltage is likely to fluctuate due to changes in the external environment. ing. For this reason, the substrate bias voltage fluctuates due to a change in the external environment, and data in the memory may be lost.

  An object of the present invention is to suppress a decrease in majority carriers accumulated in a channel body during read / write operations of other memory cells without affecting characteristics other than the memory region.

The concept of this invention is
A semiconductor substrate;
A first semiconductor layer formed on the semiconductor substrate separated by a first insulating film;
A second semiconductor layer formed on the first semiconductor layer and separated by a second insulating film;
A memory cell composed of a MISFET having a floating channel body formed in the second semiconductor layer and a gate for forming a channel formed on the surface side of the channel body;
And a bias voltage applying unit that applies a substrate bias voltage to the first semiconductor layer corresponding to the memory cell.

  In the present invention, there is provided an SOI substrate having a two-layer insulating film in which a first insulating film, a first semiconductor layer, a second insulating film, and a second semiconductor layer are formed in this order on a semiconductor substrate. Used. One memory cell is composed of one MISFET. This MISFET has a floating channel body formed in the second semiconductor layer, and a gate for forming a channel formed on the surface side of the channel body.

  A bias voltage applying unit that applies a substrate bias voltage to the first semiconductor layer corresponding to the memory cell is provided. In this case, since the first semiconductor layer is separated from the semiconductor substrate by the first insulating film and does not apply the substrate bias voltage to the semiconductor substrate, the first semiconductor layer is not affected by the characteristics other than the memory region. It is possible to suppress the decrease of majority carriers accumulated in the channel body during the read / write operation of the memory cell. In this case, the substrate bias voltage is not applied to the semiconductor substrate, but the substrate bias voltage is applied to the first semiconductor layer formed on the semiconductor substrate while being separated by the first insulating film. Yes, the substrate bias application part is not exposed, and even if the external environment changes, the substrate bias voltage is not easily affected, and fluctuations in the substrate bias due to changes in the external environment, as well as the loss of memory data Can be avoided.

  For example, a local insulating film that separates the first semiconductor layer in the memory region where the memory cell exists and other regions is provided. As a result, the memory region and the other regions are separated, and an optimum substrate bias voltage can be applied to each first semiconductor layer.

  In the memory region, a plurality of memory cells are arranged in a matrix, and each MISFET has a drain connected to a bit line, a gate connected to a word line, and a source connected to a fixed potential line to form a cell array. ing. The substrate bias voltage applied to the first semiconductor layer by the bias voltage application unit is a first value that can suppress a decrease in majority carriers accumulated in the channel body at the time of non-writing and non-reading. . Thereby, it is possible to suppress a decrease in majority carriers accumulated in the channel body during the read / write operation of other memory cells.

  For example, the substrate bias voltage applied to the first semiconductor layer by the bias voltage application unit is a second value suitable for writing when writing data “0”, “1”, or writing data “1”. It is said. As a result, the voltage applied to the bit line (drain) BL at the time of writing can be lowered, and the pass-gate leakage phenomenon can be hardly caused in the memory cell portion connected to the same bit line BL and not to be written.

  Further, for example, the substrate bias voltage applied to the first semiconductor layer by the bias voltage application unit is a second value suitable for writing at the time of writing and reading. In this case, the time that is not a voltage suitable for holding the majority carriers accumulated in the channel body becomes longer, but the switching frequency of the substrate bias voltage can be lowered.

  Further, for example, the substrate bias line connected to the bias voltage application unit is arranged in parallel with the word line. This simplifies the layout.

  According to the present invention, the first insulating film, the first semiconductor layer, the second insulating film, and the second semiconductor layer are formed in this order on the semiconductor substrate, and the floating formed in the second semiconductor layer. Having a memory cell having a channel body and a gate for forming a channel formed on the surface side of the channel body, and applying a substrate bias voltage to the first semiconductor layer corresponding to the memory cell. A bias voltage applying unit for applying is provided, and it is possible to suppress a decrease in majority carriers accumulated in the channel body during the read / write operation of other memory cells without affecting characteristics other than the memory region.

  An embodiment of the present invention will be described. FIG. 1 shows an SOC (System On Chip) device 100 to which the present invention can be applied. The SOC device 100 includes two CPUs (Central Processing Units) 101A and 101B, a DRAM (Dynamic Random Access Memory) 102, a ROM (Read Only Memory) 103, a logic IC 104, an analog IC 105, and a serial I / O. A system LSI (Large Scale Integrated circuit) including an F unit 106, a parallel I / F unit 107, and an optical port 108. An optical fiber 110 is connected to the optical port 108 of the SOC device 100 for communication with the outside.

  This SOC device 100 is formed on a double SOI substrate 10. FIG. 2 shows the structure of the double SOI substrate 10. In this double SOI substrate, a silicon layer (silicon single crystal film) 13 is formed on a silicon substrate 11 via an insulating film 12, and a silicon layer (silicon single crystal) is further formed on the silicon layer 13 via an insulating film 14. Crystal film) 15 is formed. Here, the silicon substrate 11 constitutes a semiconductor substrate, the insulating film 12 constitutes a first insulating film, the silicon layer 13 constitutes a first semiconductor layer, and the insulating film 14 constitutes a second insulating film. The silicon layer 15 constitutes a second semiconductor layer.

  The double SOI substrate 10 is manufactured by, for example, (1) SIMOX method, (2) bonding (polishing) method, (3) bonding (smart cut) method, or the like.

  (1) A manufacturing process of a double SOI substrate by the SIMOX method will be described.

  First, as shown in FIG. 3A, an SOI substrate is prepared. This SOI substrate is obtained by forming a silicon layer 16 on a silicon substrate 11 via an insulating film 12, for example, a silicon oxide film. The thickness of the silicon layer 16 is set to a thickness required by an epitaxial growth process or the like.

  Next, as shown in FIG. 3B, oxygen ions having a high energy and a high concentration are implanted from the surface of the silicon layer 16.

  Next, as shown in FIG. 3C, a high-temperature annealing process is performed to react the implanted oxygen ions with silicon, thereby generating an insulating film 14 made of a silicon oxide film in the silicon layer.

  Thus, by generating the insulating film 14 in the silicon layer, the double SOI substrate 10 in which the insulating film 12, the silicon layer 13, the insulating film 14, and the silicon layer 15 are formed in this order on the silicon substrate 11. Is obtained.

  Next, as shown in FIG. 3D, the thickness of the silicon layer 15 is adjusted to a desired thickness. For example, the thickness is increased by an epitaxial growth process, or is decreased by a thermal oxide film formation and etching process.

  (2) A manufacturing process of a double SOI substrate by a bonding (polishing) method will be described.

  First, as shown in FIG. 4A, an SOI substrate is prepared. This SOI substrate is obtained by forming a silicon layer 13 on a silicon substrate 11 via an insulating film 12, for example, a silicon oxide film. Then, a silicon oxide film 17 is formed on the surface of the silicon layer 13 by thermal oxidation. The thickness of the silicon layer 13 is set to a thickness required by an epitaxial growth process or the like.

  Further, as shown in FIG. 4B, a silicon substrate 18 is prepared, and a silicon oxide film 19 is formed on the surface thereof by thermal oxidation.

  Next, as shown in FIG. 4C, the silicon substrate 18 prepared in FIG. 4B is bonded to the SOI substrate prepared in FIG. 4A. In this case, the silicon oxide film 19 of the silicon substrate 18 is overlaid on the silicon oxide film 17 of the SOI substrate and bonded by heating and pressing.

  Next, as shown in FIG. 4D, the thickness of the silicon layer 18 on the surface side is adjusted to a desired thickness by polishing by CMP (Chemical Mechanical Polishing). Thereby, the double SOI substrate 10 in which the insulating film 12, the silicon layer 13, the insulating film 14, and the silicon layer 15 are formed in this order on the silicon substrate 11 is obtained.

  (3) A manufacturing process of a double SOI substrate by bonding (smart cut) will be described.

  First, as shown in FIG. 5A, an SOI substrate is prepared. This SOI substrate is obtained by forming a silicon layer 13 on a silicon substrate 11 via an insulating film 12, for example, a silicon oxide film. Then, a silicon oxide film 20 is formed on the surface of the silicon layer 13 by thermal oxidation. The thickness of the silicon layer 13 is set to a thickness required by an epitaxial growth process or the like.

  Further, as shown in FIG. 5B, a silicon substrate 21 is prepared. Then, hydrogen ions are implanted into the silicon substrate 21 to define the substrate separation position.

  Next, as shown in FIG. 5C, the silicon substrate 21 prepared in FIG. 5B is bonded to the SOI substrate prepared in FIG. 5A. In this case, the surface of the silicon substrate is overlaid on the silicon oxide film 17 of the SOI substrate and bonded by heating and pressing.

  Next, as shown in FIG. 5D, the silicon substrate 21 is cut and separated at the substrate separation position by heating to a temperature at which the substrate separation phenomenon occurs due to concentration of the ion-implanted hydrogen. Then, as shown in FIG. 5E, the separation position of the silicon substrate 21 is polished and finished. Thereby, the double SOI substrate 10 in which the insulating film 12, the silicon layer 13, the insulating film 14, and the silicon layer 15 are formed in this order on the silicon substrate 11 is obtained.

  In place of the silicon substrate 18 in the above bonding (polishing) method or the silicon substrate 21 in the above bonding (smart cut) method, a substrate made of germanium, strained silicon, silicon-germanium or the like is used. A substrate similar to the double SOI substrate 10 can be manufactured and used instead of the double SOI substrate 10. Further, instead of the silicon layer 16 in the SIMOX method, a semiconductor layer made of germanium, strained silicon, silicon-germanium or the like is used, an insulating film 14 is formed in the semiconductor layer, and the same as the double SOI substrate 10. It is also conceivable to use a double SOI substrate 10 instead of the double SOI substrate 10.

  FIG. 6 shows a configuration of an FBC memory cell MC that is a memory cell constituting the DRAM 102 of the SOC device 100 described above. As described above, the double SOI substrate in which the insulating film 12, the silicon layer 13, the insulating film 14, and the silicon layer 15 are formed in this order on the silicon substrate 11 is used. The silicon layer 15 is a p-type silicon layer.

  Then, with the silicon layer 15 as a channel body, a gate electrode 45 is formed on the surface via a gate insulating film 44, and a source diffusion layer 46 and a drain diffusion layer 47 are formed at a depth reaching the insulating film 14, and a memory is formed. An n-channel MISFET as the cell MC is configured.

  A contact plug 48 made of polycrystalline silicon or the like is embedded in a state of penetrating the silicon layer 15 and the insulating film 14. The contact plug 48 is electrically connected to the silicon layer 13 existing between the insulating film 12 and the insulating film 14. The contact plug 48 constitutes a bias voltage application unit for applying a substrate bias voltage to the silicon layer 13.

  A local insulating film 49 is formed between the channel body and the contact plug 48 so that the substrate bias voltage is not applied from the contact plug 48 to the channel body.

  Each memory cell MC constituting the DRAM 102 is arranged in a matrix with floating channel bodies separated from each other, and a cell array 51 is formed as shown in FIG. In this case, the drain 47 is connected to the bit line BL, the gate electrode 45 is connected to the word line WL, the source 46 is connected to the fixed potential line SL, for example, the ground line, and the contact plug 48 is connected to the substrate bias line VL. Note that the fixed potential line SL is not shown in FIG.

  A substrate bias voltage is applied to the silicon layer 13 corresponding to each memory cell MC in units of word lines. Therefore, a local insulating film 50 extending in the word line WL direction is formed to separate the silicon layer 13 corresponding to each memory cell MC in units of word lines.

  Since the writing and reading operations of the memory cell MC are the same as the writing and reading operations of the memory cell MC (b) described above, description thereof is omitted.

  The substrate bias voltage applied to the silicon layer 13 corresponding to each memory cell MC will be described.

  At the time of non-writing and non-reading, the substrate bias voltage (voltage applied to the substrate bias line VL) applied to the silicon layer 13 is the first that can suppress the decrease of holes that are majority carriers accumulated in the channel body. For example, −1V. This first value is a phenomenon in which holes accumulated in the channel body are reduced (pass / gate / gate) even when the voltage of the bit line (drain) BL changes during the operation of reading / writing data of other portions. This is a voltage value that can hardly cause a leakage phenomenon).

  For writing and reading, for example, the following (1) to (3) are set.

  (1) As shown in FIG. 8, when data “1” and “0” are written, the substrate bias voltage applied to the silicon layer 13 is set to a second value suitable for writing, for example, 0V.

  (2) As shown in FIG. 9, when data “1” is written, the substrate bias voltage applied to the silicon layer 13 is set to a second value suitable for writing, for example, 0V.

  In these cases (1) and (2), except when data “1” and “0” are written, or except when data “1” is written, the substrate bias voltage decreases the number of holes accumulated in the channel body. The above-mentioned first value, for example, 0 V, can be suppressed. Therefore, even if the voltage of the bit line (drain) BL changes, the pass-gate leakage phenomenon is less likely to occur than when the substrate bias voltage is at the second value.

  In the case of (1) and (2), the substrate bias voltage is set to the second value suitable for writing when data “1” and “0” are written or when data “1” is written. For this reason, the voltage of the bit line BL when data is written can be set low, and the pass-gate leakage phenomenon is less likely to occur in the portion connected to the word line WL where data writing is not desired.

  (3) As shown in FIG. 10, at the time of data writing and reading, the reference bias voltage applied to the silicon layer 13 is set to a second value suitable for writing, for example, 0V.

  In this case, as compared with the cases (1) and (2), the time when the substrate bias voltage is not a value suitable for holding the holes accumulated in the channel body becomes longer. However, the switching frequency of the substrate bias voltage can be remarkably lowered as compared with the cases (1) and (2).

  As described above, since the insulating film 14 is formed by the SIMOX method or the bonding method, it is generally thicker than the gate oxide film 44. This is a method for applying a substrate bias voltage suitable for realizing recording and reproduction.

  Next, a method of arranging the substrate bias line VL with respect to the bit line BL and the word line WL will be described.

  In the present embodiment, as described above, the substrate bias line VL needs to be connected in addition to the fixed potential line SL, the bit line BL, and the word line WL. In this case, as shown in FIG. 11, by arranging the fixed potential line SL and the bit line BL in parallel, it is easy to arrange the word line WL and the substrate bias line VL that are driven simultaneously in parallel. . On the other hand, as shown in FIG. 12, if the fixed potential line SL and the bit line BL are arranged orthogonally, a more complicated layout is required to arrange the word line WL and the substrate bias line VL in parallel. Is required.

  As described above, the substrate bias voltage is applied to the silicon layer 13 corresponding to the memory cell MC via the contact plug 48. Since the silicon layer 13 is separated from the silicon substrate 11 by the insulating film 122 and does not apply a substrate bias voltage to the silicon substrate 11, it does not affect the characteristics other than the memory region where the memory cell MC exists, It is possible to prevent the majority carriers accumulated in the channel body from being reduced during the read / write operation of other memory cells MC.

  Further, the substrate bias voltage is not applied to the silicon substrate 11 but the substrate bias voltage is applied to the silicon layer 13 formed on the silicon substrate 11 while being separated by the insulating film 12. Even if the applied portion is not exposed and the external environment changes, the substrate bias voltage is not easily affected, and fluctuations in the substrate bias due to changes in the external environment, and loss of data in the memory can be avoided.

  In the SOC device 100 shown in FIG. 1, at least a local insulating film 55 that separates the silicon layer 13 is provided between a memory region where the DRAM 102 exists and other regions. FIG. 13 shows a memory area where the DRAM 102 is formed, and a logic / analog area where the logic IC 104 and the analog IC 105 are formed. As described above, the substrate bias voltage is applied to the silicon layer 13 corresponding to the memory region by the contact plug 48 in units of the word line WL. A predetermined substrate bias voltage is applied to the logic / analog region by a contact plug 56 formed in the same manner as the contact plug 48 in the memory region.

  As described above, since the local insulating film 55 for separating the silicon layer 13 is provided between the memory region and the other region, an optimum substrate bias is applied to each of the silicon layers 13 corresponding to the memory region and the other region. Can be applied, and the highest characteristics of the SOC device 100 can be obtained.

In the SOC device 100 shown in FIG. 1, for example, optical communication using an optical waveguide is performed between the CPU 101A and the CPU 101B. In the present embodiment, as shown in FIG. 14, the optical waveguide 61 for optical communication is formed using the insulating film 12, the silicon layer 13, and the insulating film 14. In FIG. 14, the optical waveguide region is shown to be adjacent to the memory region. In this case, a thick portion as the optical waveguide 61 is formed in the silicon layer 13 sandwiched between the insulating films 12 and 14. Since the refractive index of silicon (Si) is 3.5 and the refractive index of silicon dioxide (SiO ₂ ) is 1.5, the optical waveguide 61 can be formed by the insulating film 12, the silicon layer 13, and the insulating film 14. . A substrate bias voltage is not applied to the silicon layer 13 corresponding to the optical waveguide region.

  Here, with reference to FIG. 15, the manufacturing process of the optical waveguide 61 in the case of manufacturing by the SIMOX method will be described. In FIG. 15, portions corresponding to those in FIG. 3 are denoted by the same reference numerals, and detailed description thereof is omitted.

  First, as shown in FIG. 15A, an SOI substrate is prepared. This SOI substrate is obtained by forming a silicon layer 16 on a silicon substrate 11 via an insulating film 12, for example, a silicon oxide film. The thickness of the silicon layer 16 is set to a thickness required by an epitaxial growth process or the like.

  Next, as shown in FIG. 15B, a silicon oxide film 22 is formed on the surface of the silicon layer 16 by thermal oxidation. Then, patterning is performed to form a mask 23 made of silicon dioxide corresponding to the optical waveguide pattern, as shown in FIG. 15C.

  Next, as shown in FIG. 15D, oxygen ions are implanted in a state where the mask 23 is disposed on the silicon layer 16. In this case, in the portion where the mask 23 is disposed, the ion velocity is reduced by the mask 23, so that oxygen ions are implanted shallowly, while in the portion where the mask 23 is not disposed, oxygen ions are implanted deeply.

  Next, as shown in FIG. 15E, the SOI substrate in which oxygen ions are implanted in the silicon layer 16 is subjected to a high temperature annealing treatment, and the implanted oxygen ions and silicon are reacted to form a silicon oxide film ( An insulating film 14 is generated, and an optical waveguide 61 composed of the insulating film (silicon oxide film) 12, the silicon layer 13 and the insulating film (silicon oxide film) 14 is formed. Note that the mask 23 is removed before or after the annealing process or after some annealing.

  The present invention can suppress a decrease in majority carriers accumulated in a channel body during read / write operations of other memory cells without affecting characteristics other than the memory region, and a semiconductor device having a memory (DRAM). Applicable.

It is a figure which shows an example of the SOC device which can apply this invention. It is sectional drawing which shows the structure of a double SOI substrate. It is a figure which shows the manufacturing process of the double SOI substrate by a SIMOX method. It is a figure which shows the manufacturing process of the double SOI substrate by the bonding (polishing) method. It is a figure which shows the manufacturing process of the double SOI substrate by the bonding (smart cut) method. It is sectional drawing which shows the structure of the FBC memory cell which is a memory cell which comprises DRAM. It is a figure which shows the cell array by which the some FBC memory cell is arranged in matrix. It is a figure which shows the example of a setting of the substrate bias voltage at the time of writing and at the time of reading. It is a figure which shows the other example of a setting of the substrate bias voltage at the time of writing and reading. It is a figure which shows the further another example of a setting of the substrate bias voltage at the time of writing and at the time of reading. FIG. 5 is a diagram illustrating an arrangement example of a word line WL, a bit line BL, a fixed potential line SL, and a substrate bias line VL. FIG. 5 is a diagram illustrating an arrangement example (comparative example) of word lines WL, bit lines BL, fixed potential lines SL, and substrate bias lines VL. It is a figure for demonstrating isolation | separation of a memory area | region and another area | region. It is a figure for demonstrating the optical waveguide formed in the SOI substrate. It is a figure which shows the manufacturing process of a SIMOX optical waveguide. It is sectional drawing which shows the structure of a normal SOI substrate. It is sectional drawing which shows the fundamental structure of the conventional FBC memory cell. It is a figure which shows the cell array by which the some FBC memory cell is arranged in matrix. It is a figure which shows the relationship between a body potential and a word line voltage. It is a figure for demonstrating the write-in operation | movement of a FBC memory cell. It is a figure for demonstrating the read-out operation | movement of a FBC memory cell.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10 ... Double SOI substrate, 11 ... Silicon substrate, 12, 14 ... Insulating film, 13, 15 ... Silicon layer, 44 ... Gate oxide film, 45 ... Gate electrode, 46 ... Source diffusion layer, 47 ... Drain diffusion layer, 48, 56 ... Contact plug, 49, 50, 55 ... Local insulating film, 51 ... Cell array, 61 ... Optical waveguide, 100 ... SOC devices, 101A, 101B ... CPU, 102 ... RAM

Claims (7)

A semiconductor substrate;
A first semiconductor layer formed on the semiconductor substrate separated by a first insulating film;
A second semiconductor layer formed on the first semiconductor layer and separated by a second insulating film;
A memory cell composed of a MISFET having a floating channel body formed in the second semiconductor layer and a gate for forming a channel formed on the surface side of the channel body;
And a bias voltage applying unit that applies a substrate bias voltage to the first semiconductor layer corresponding to the memory cell. The semiconductor device according to claim 1, further comprising a local insulating film that separates the first semiconductor layer in a memory region in which the memory cell exists and another region. A plurality of the memory cells are arranged in a matrix, each MISFET has a drain connected to a bit line, a gate connected to a word line, and a source connected to a fixed potential line to form a cell array.
The substrate bias voltage applied to the first semiconductor layer by the bias voltage application unit is a first value that can suppress a decrease in majority carriers accumulated in the channel body during non-reading and non-writing. The semiconductor device according to claim 1, wherein: The semiconductor device according to claim 3, wherein the substrate bias voltage applied to the first semiconductor layer by the bias voltage application unit is a second value suitable for writing at the time of writing. The substrate bias voltage applied to the first semiconductor layer by the bias voltage application unit is set to a second value suitable for writing when data “1” is written. Semiconductor device. 4. The semiconductor device according to claim 3, wherein a substrate bias voltage applied to the first semiconductor layer by the bias voltage application unit is a second value suitable for writing during writing and reading. 5. . The semiconductor device according to claim 3, wherein a substrate bias line connected to the bias voltage application unit is disposed in parallel with the word line.

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