CN1354523A - Semiconductor storage device and its making method - Google Patents

Abstract

An bit memory cell MC is composed of one MOS transistor having a floating bulk region which is electrically isolated from others. A gate electrode of the MOS transistor is connected to a word line WL, a drain diffusion region thereof is connected to a bit line BL, and a source diffusion region thereof is connected to a fixed potential line SL. The memory cell stores a first threshold state in which majority carriers produced by impact ionization are injected and held in the bulk region of the MOS transistor and a second threshold state in which the majority carriers in the bulk region of the MOS transistor are emitted by a forward bias at a pn junction on the drain side as binary data. Thereby, a simple transistor structure is used as a memory cell, enabling dynamic storage of binary data by a small number of signal lines can be provided.

Description

Semiconductor storage and manufacture method thereof

Technical field

The present invention relates to a kind of dynamic semiconductor memory device (DRAM).

Background technology

Existing DRAM is the memory cell that is made of MOS transistor and capacitor.The miniaturization of DRAM advances greatly along with adopting grooved capacitor structure or laminated body, capacitor structure.Now, suppose that minimum process size rule is F, then the size of unit storage unit (cell size) narrows down to 2F * 4F=8F ²Area.That is, minimum process size rule F dwindles simultaneously with regenerating, and generally establishing cell size is α F ²The time, factor alpha is also dwindled with regenerating, and F=0.18 μ m can realize α=8 now.

From now on, in order to ensure also with the same constant cell size or the development trend of chip size in the past, with regard to the μ m of F＜O.18, α＜8 are satisfied in requirement, and then the μ m of F＜O.13, just require α＜6, how to form the little cell size of area and just become big problem with microfabrication.Therefore, also proposed all memory cell and be made into 6F transistor/one electric capacity ²Or 4F ²The motion of size.But existence must become transistor fabrication the technical difficulty of longitudinal type, and the problem that electrical interference increases between consecutive storage unit also has the difficulty on the manufacturing technologies such as processing, growing film, and practicability also is not easy.

Therefore, also propose not use electric capacity, and, enumerate following several by the DRAM of a transistor fabrication memory cell.

(1)JOHN?E.LEISS?et?al，”DRAM?Design?Using?the?Taper-IsolatedDynamic?Cell”(IEEE?TRANSACTION?ON?ELECTRON?DEVICES，VOL.ED-29，NO.4，APRIL?1982，pp707-714)

(2) spy opens flat 3-171768 communique

(3)Marnix?R.Tack?et?al，”The?Multistable?Charge-Controlled?MemoryEffect?in?SOI?MOS?Transistor?at?Low?Temperature”(IEEE?TRASCTION?ONELECTION?DEVICES，VOL.37，MAY，1990，pp1373-1382)

(4)Hsing-jen?Wann?et?al，”A Capacitorless?DRAM?Cell?on?SOISubstrate”，(IEDM93，pp635-638)

(1) memory cell, the MOS transistor of being imbedded the raceway groove structure by employing constitutes.Utilize the parasitic transistor of the tapering part formation of device isolation dielectric film, surperficial inversion layer is discharged and recharged, carry out binary storage.

(2) memory cell, the MOS transistor that adopts trap one by one to isolate, by the threshold value of the trap potential decision of MOS transistor as binary data.

(3) memory cell is made of the MOS transistor on the SOI substrate.Apply big negative voltage from SOI substrate one side, utilize the hole accumulation of the oxide-film of silicon layer and interface portion, emitting, injecting and carry out binary storage by means of this hole.

(4) memory cell is made of the MOS transistor on the SOI substrate.MOS transistor is textural to be one, but overlaps to form the opposite conduction layer with leaking the diffusion layer surface, makes entire combination in fact and writes with PMOS transistor and the structure of reading with nmos pass transistor.The substrate zone of nmos pass transistor as unsteady node, is carried out binary data storage according to its current potential.

But, (1) complex structure, owing to utilize parasitic transistor, thereby the controlled aspect of characteristic is also had difficulty.(2) though structure is simple, transistorized source electrode, drain electrode connect holding wire together and need carry out control of Electric potentials.In addition, owing to be that trap is isolated, cell size is big, and can not rewrite every.With regard to (3), need carry out control of Electric potentials from SOI substrate one side, therefore, can not every be rewritten, there is difficult point controlled aspect.(4) need to make special transistorized structure, in addition, need to make word line on the memory cell, write bit line, readout bit line and bus, holding wire increases.

Summary of the invention

The object of the present invention is to provide and a kind ofly make memory cell by simple transistor configurations, available a few signals line carries out the semiconductor storage and the manufacture method thereof of dynamic memory to binary data.

According to the semiconductor storage of one embodiment of the invention, one memory cell is made of a transistor,

Above-mentioned transistor comprises:

Semiconductor layer, this semiconductor layer are the 1st conduction types, become quick condition with other memory cell electricity isolation;

Leak diffusion layer, this leakage diffusion layer is the 2nd conduction type, is formed on the semiconductor layer of above-mentioned the 1st conduction type, and is connected with bit line;

Source diffused layer, this source diffused layer are the 2nd conduction types, isolate being formed on the semiconductor layer of above-mentioned the 1st conduction type with above-mentioned leakage diffusion layer; And

Gate electrode, this gate electrode are situated between and are formed on the above-mentioned semiconductor layer between above-mentioned leakage diffusion layer and the above-mentioned source diffused layer with gate insulating film, and are connected with word line;

Wherein

Above-mentioned transistor has, and has the 1st data mode of the 1st threshold voltage that keeps superfluous majority carrier in above-mentioned semiconductor layer and has the 2nd data mode of emitting the 2nd threshold voltage of superfluous majority carrier in the above-mentioned semiconductor layer.

And, according to the manufacture method of the semiconductor storage of one embodiment of the invention,

On Semiconductor substrate, form dielectric film;

On above-mentioned dielectric film, form the semiconductor layer of the 1st conduction type,

On above-mentioned semiconductor layer, be formed on grid and form the mask that the district has window,

On the window sidewall of aforementioned mask, form side wall insulating film,

By the above-mentioned window of aforementioned mask, add impurity to above-mentioned semiconductor layer, formation has the impurity interpolation layer of impurity concentration than the 1st conduction type of above-mentioned semiconductor floor height,

Remove after the above-mentioned side wall insulating film, imbed and form gate insulating film and gate electrode at the above-mentioned window of aforementioned mask

Remove after the aforementioned mask, add impurity for above-mentioned semiconductor layer, form the leakage diffusion layer and the source diffused layer of the 2nd conduction type.

Description of drawings

Fig. 1 is the profile of the DRAM memory cell structure of expression the 1st embodiment of the present invention.

Fig. 2 is the equivalent electric circuit of this DRAM memory cell.

Fig. 3 is the layout of this DRAM memory cell array.

Fig. 4 A is A-A ' profile of Fig. 3.

Fig. 4 B is B-B ' profile of Fig. 3.

Fig. 5 is the word line potential of this DRAM unit of expression and the graph of a relation of bulk potential.

Fig. 6 is the playback mode that is used to illustrate this DRAM unit.

Fig. 7 is another playback mode that is used to illustrate this DRAM unit.

Fig. 8 is the working waveform figure that expression this DRAM " 1 " data are read/refreshed.

Fig. 9 is the working waveform figure that expression this DRAM " 0 " data are read/refreshed.

Figure 10 is that expression this DRAM " 1 " data are read/working waveform figure that " 0 " data write.

Figure 11 is that expression this DRAM " 0 " data are read/working waveform figure that " 1 " data write.

Figure 12 is the working waveform figure that " 1 " data of another playback mode of this DRAM of expression are read/refreshed.

Figure 13 is the working waveform figure that " 0 " data of another playback mode of this DRAM of expression are read/refreshed.

Figure 14 is that " 1 " data of another playback mode of this DRAM of expression are read/working waveform figure that " 0 " data write.

Figure 15 is that " 0 " data of another playback mode of this DRAM of expression are read/working waveform figure that " 1 " data write.

Figure 16 is the gate capacitance Cgb-voltage Vgb performance plot of this DRAM unit of expression.

Figure 17 is the equivalent electric circuit of the constant current playback mode of this DRAM unit.

Figure 18 is the bit line potential change figure of the work of reading of this DRAM unit of expression.

Figure 19 is the equivalent electric circuit that is used to illustrate " 0 " writing speed of this DRAM unit.

Figure 20 is the p type layer potential change figure of expression Figure 19.

Figure 21 is gate capacitance Cgb-voltage Vgb curve (the during the P type polysilicon bar utmost point) figure of " 0 " data cell of this DRAM unit of expression.

Figure 22 is word line potential Vwl of expression identical " 0 " data cell and the graph of a relation of bulk potential VB.

Figure 23 is the word line potential Vwl of " 1 " data cell of this DRAM unit of expression and the graph of a relation of bulk potential VB.

Figure 24 is gate capacitance Cgb-voltage Vgb curve (the during the p type polysilicon bar utmost point) figure of expression " 1 " data cell.

Figure 25 is gate capacitance Cgb-voltage Vgb curve (the during the n type polysilicon bar utmost point) figure of expression " 1 " data cell.

Figure 26 is relation (the during the n type polysilicon bar utmost point) figure of the word line potential Vwl and the bulk potential VB of expression " 1 " data cell.

Figure 27 is gate capacitance Cgb-voltage Vgb curve (the during the p type polysilicon bar utmost point) figure of expression " 0 " data cell.

Figure 28 is relation (the during the n type polysilicon bar utmost point) figure of the word line potential Vwl and the bulk potential VB of expression " 0 " data cell.

Gate capacitance Cgb-voltage Vgb curve (the during the p type polysilicon bar utmost point) figure of " 1 " data cell when Figure 29 is expression employing thin silicone layer.

Figure 30 is that word line potential Vw1 of " 1 " data cell and the graph of a relation of bulk potential VB are somebody's turn to do in expression.

Gate capacitance Cgb-voltage Vgb curve (the during the p type polysilicon bar utmost point) figure of " 0 " data cell when Figure 31 is expression employing thin silicone layer.

Figure 32 is that word line potential Vwl of " 0 " data cell and the graph of a relation of bulk potential VB are somebody's turn to do in expression.

Figure 33 is an expression silicon layer impurity concentration and the graph of a relation of the difference of the threshold value of " 0 ", " 1 " data cell.

Graph of a relation between the cell current of the impurity concentration of this silicon layer of Figure 34 and " 1 " data cell.

Figure 35 is the time chart of the bit line potential change of impurity concentration when reading of this silicon layer of expression.

Figure 36 be the data of expression " 1 " data cell when keeping bulk potential and the graph of a relation (the p type polysilicon bar utmost point) of threshold value.

Figure 37 be the data of expression " 1 " data cell when keeping bulk potential and the graph of a relation (the n type polysilicon bar utmost point) of threshold value.

Figure 38 is the graph of a relation of variation of expression word line potential and threshold deviation.

Figure 39 is the sense amplifier layout illustration of expression the present invention the 1st embodiment.

Figure 40 is the profile of the DRAM unit structure of expression the 2nd embodiment corresponding to Fig. 1.

Figure 41 is the bulk potential of expression MOS transistor and the graph of a relation of threshold voltage.

Figure 42 A is the basic pn knot structural map that the preparation of the expression unit structure validity that is used to inquire into Figure 40 is inquired into.

Figure 42 B is the distribution map of the electric field that the pn structure shown in the presentation graphs 42A is made part.

Figure 43 is that the drain region side pn structure that expression is used to inquire into the unit structure validity of Figure 40 is made and its distribution map of the electric field.

Figure 44 is the low concentration P type layer width of expression among Figure 43 and the graph of a relation of depletion layer stretching, extension.

Figure 45 is the concentration of expression n type diffused layer when lower, the graph of a relation of the low concentration p type layer width of corresponding Figure 44 and depletion layer stretching, extension.

Figure 47 is the graph of a relation of identical low concentration P type layer width of expression and maximum field intensity.

Figure 48 is the mode figure that the depletion layer of the unit structure optimal condition of expression Figure 40 stretches.

Figure 49 is the unit structure profile of the embodiment of the expression unit structure that improves Figure 40.

Figure 50 is that the drain region side pn structure that expression is used to inquire into Figure 49 unit structure validity is made and its distribution map of the electric field.

Figure 51 is the low concentration P type layer width of expression among Figure 50 and the graph of a relation of depletion layer stretching, extension.

Figure 52 is the graph of a relation of identical low concentration P type layer width of expression and maximum field intensity.

Figure 53 is the mode figure that the depletion layer of the unit structure optimal condition of expression Figure 49 stretches.

Figure 54 is the unit manufacturing procedure picture that is used to illustrate Figure 49.

Figure 55 is the unit manufacturing procedure picture that is used to illustrate Figure 49.

Figure 56 is the unit manufacturing procedure picture that is used to illustrate Figure 49.

Figure 57 is the unit manufacturing procedure picture that is used to illustrate Figure 49.

Figure 58 A is the unit structure plane graph of expression the 3rd embodiment.

Figure 58 B is A-A ' profile of Figure 58 A.

Figure 59 A is the unit structure stereogram of expression the 4th embodiment.

Figure 59 B is the profile along the bit line direction of Figure 59 A.

Figure 60 A is the layout of the DRAM cell array of the 5th embodiment.

Figure 60 B is I-I ' profile of Figure 60 A.

Figure 60 C is II-II ' profile of Figure 60 A.

Figure 61 A is the plane graph of the device isolation operation of this embodiment of expression.

Figure 61 B is I-I ' profile of Figure 61 A.

Figure 61 C is II-II ' profile of Figure 61 A.

Figure 62 A is the plane graph that the transistor of this embodiment of expression forms operation.

Figure 62 B is I-I ' profile of Figure 62 A.

Figure 62 C is II-II ' profile of Figure 62 A.

Figure 63 A is the plane graph that the source wiring layer of this embodiment of expression forms operation.

Figure 63 B is I-I ' profile of Figure 63 A.

Figure 64 A is the plane graph that the bit line contact plug of this embodiment of expression is imbedded operation.

Figure 64 B is I-I ' profile of Figure 64 A.

Figure 65 is the plane graph that another bit line contact plug of expression is imbedded operation.

Figure 66 is the profile that the interlayer dielectric after the device of expression the 6th embodiment forms forms operation.

Figure 67 is the profile that the contact plug of this embodiment of expression is imbedded operation.

Figure 68 is the profile that the source wiring layer of this embodiment of expression forms operation.

Figure 69 is the profile that the interlayer dielectric of this embodiment of expression forms operation.

Figure 70 is the profile that the bit line of this embodiment of expression forms operation.

Figure 71 is a plane graph of representing the device isolation structure of the 7th embodiment corresponding to Figure 61 A.

Embodiment

Below, with reference to accompanying drawing, embodiments of the invention are described.

Fig. 1 represents the profile construction of unit storage unit of the DRAM of the present invention the 1st embodiment, and Fig. 2 represents its equivalent electric circuit.Memory cell MC is made of the N-channel MOS transistor of SOI structure.That is, adopt on silicon substrate 10, to form silicon oxide film 11, use the SOI substrate that is formed with P type silicon layer 12 on this silicon oxide film 11 as dielectric film.On the silicon layer 12 of this substrate, being situated between forms gate electrode 13 with gate oxidation films 16, by gate electrode 13 autoregistrations formation n type source, leakage diffusion layer 14,15.

Make the source, leak the degree of depth that diffusion layer 14,15 forms arrival bottom silicon oxide film 11.Therefore, the tagma that constitutes by P type silicon layer 12, if carry out the isolation of channel width dimension (direction vertical with the accompanying drawing paper) with oxide-film, then the side of bottom surface and channel width dimension and its insulation are isolated, and orientation becomes the quick condition of being isolated by the pn knot.

Arrange in matrix form under the situation of this memory cell MC, gate electrode 13 connects word line WL, and source diffused layer 15 is connected and fixed equipotential line (earthing potential line) SL, leaks diffusion layer 14 and is connected on the bit line BL.

Fig. 3 represents the layout of memory cell array, and Fig. 4 (a) and (b) are A-A ', the B-B ' section of presentation graphs 3 respectively.P type silicon layer 12 forms the clathrate figure by landfill silicon oxide film 21, that is, two transistor area in total drain region are carried out device isolation and configuration in word line WL direction by silicon oxide film 21.Perhaps also can be undertaken that transversal device is isolated and without landfill silicon oxide film 21 by etch silicon layer 12.Gate electrode 13 forms continuously in a direction, and becomes word line WL.Source diffused layer 15 forms continuously along word line WL direction, and becomes fixed potential line (common source line) SL.Cover by interlayer dielectric 23 on the transistor, form bit line BL on it.Configuration bit line BL contacts the total leakage diffusion layer 14 of itself and two transistors, and intersects with word line WL.

Therefore, the silicon layer 12 in this memory cell array tagma, the side of bottom surface and channel width dimension is isolated mutually by oxide-film, and quick condition is isolated and kept to orientation mutually by the pn knot.

And, in this memory cell array, suppose with the spacing of minimum process size F to form word line WL and bit line BL, unit cell area then, shown in the dotted line of Fig. 3 like that, be 2F * 2F=4F ²

The operating principle of the DRAM unit that is made of this nmos pass transistor is, utilizes the majority carrier hole accumulation of MOS transistor tagma (the P type silicon layer 12 of isolating with all the other insulation).That is,, expand the several layers 14 big electric currents of outflow, near leaking diffusion layer 14, cause ionization by collision from leaking along with make the MOS transistor action in the pentode zone.The superfluous majority carrier hole that generates with ionization by collision remains in the P type silicon layer 12, with this hole accumulation state (than the high state of thermal equilibrium state current potential), for example is defined as data " 1 ".Add forward bias for the pn knot that leaks between diffusion layer 14 and the P type silicon layer 12, regulation drain electrode one state of being sidelong out P type silicon layer 12 excess holeses is data " 0 ".

Data " 0 ", " 1 " are the potential differences in tagma, and store as the threshold voltage difference of MOS transistor.That is, with the hole accumulation, the threshold voltage vt h1 of tagma high potential data one state is lower than the threshold voltage vt h0 of data " 0 " state.In order to keep the state of " 1 " data in accumulation majority carrier hole in the tagma, need add back bias voltage to word line.This data hold mode is exceeded with the write activity (wiping) that does not carry out opposite data, and it is also constant to read action, and is promptly different with the capacitive based DRAM in 1 transistor/1 of the electric charge accumulation that utilizes electric capacity, can carry out nondestructive read-out.

As for the playback mode of data, can think have several.The relation of word line potential Vwl and bulk potential VB is exactly the relation of Fig. 5 data " 0 " and " 1 ".Therefore data the 1st method of reading is, gives word line WL data " 0 ", the centre of threshold voltage vt h0, the Vth1 of " 1 " read current potential, do not flow through electric current in " 0 " memory of data unit, and flow through electric current in " 1 " memory of data unit.Specifically, for example, make bit line BL be pre-charged to the current potential VBL of regulation, and rear drive word line WL.Therefore, as shown in Figure 6, during " 0 " data, VBL is constant for the bit-line pre-charge current potential, and during " 1 " data, precharge potential VBL descends.

The 2nd playback mode is, word line WL is risen after, to bit line BL supplying electric current,, utilize the rate of climb difference of bit line current potential according to the conducting degree of " 0 ", " 1 ".Briefly, BL is pre-charged to 0V with bit line, as shown in Figure 7, word line WL is risen, and supplies with bit line current.At this moment, it is poor to rise according to the current potential that utilizes dummy cell to detect bit line, can carry out discriminating data.

The 3rd playback mode is, when reading out in the current potential clamp bit line BL of regulation, and the mode of the bit line current difference that " 0 ", " 1 " are different.Want read current poor, need current-voltage conversion circuit, and potential difference is carried out the difference amplification the most at last, is read.

In the 1st embodiment of the present invention, for selectivity writes " 0 " data, promptly the tagma for the selected memory cell of the current potential of the word line WL that only selects from the inside by memory cell array and bit line BL emits excess holes, and the capacitive coupling between word line WL and the tagma is just very important.It is narrated after going through, but the state in accumulation hole need be with the enough reverse bias of word line in data " 1 " tagma, and electric capacity between the grid of memory cell and substrate is remained on the state (the promptly surperficial state that does not form depletion layer) that becomes gate oxidation films electric capacity.

And write activity it is desirable to " 0 ", " 1 " writes minimizing power consumption as pulse together." 0 " is write fashionable, flows into hole current from selecting transistorized tagma to the drain region, flows into electronic current from the drain region to the tagma, and can be to the tagma injected hole.

The following describes action waveforms more specifically.Fig. 8～Figure 11 adopts the 1st playback mode, the action waveforms of reading/refreshing and reading when carrying out discriminating data according to having or not of selected cell bit line discharges/write.

Fig. 8 and Fig. 9 are respectively reading/refresh activity of " 1 " data and " 0 " data.Up to moment t1 is data hold mode (nonselection mode), adds negative potential on the word line WL.At moment t1, word line WL rises to the positive potential of regulation.At this moment word line potential is set between the threshold voltage vt h0 and threshold voltage vt h1 of " 0 ", " 1 " data.Therefore, during " 1 " data, precharge in advance bit line BL becomes electronegative potential by discharge.During " 0 " data, keep bit line current potential VBL.Differentiate " 1 ", " 0 " data thus.

And, at moment t2, make word line WL current potential higher, when sense data is " 1 " simultaneously, add positive potential (Fig. 8) for bit line BL, when sense data is " 0 ", apply negative potential (Fig. 9) for bit line BL.Therefore, select storage unit is when " 1 " data, and according to the excessive channel current of pentode stream of action, the ionization that bumps to tagma injection and the superfluous hole of maintenance, writes " 1 " data once more.When " 0 " data, the drain region knot becomes forward bias, writes " 0 " data that the tagma does not keep excess holes once more.

And at moment t3, word line WL reverse bias finishes to read/refresh activity.With with other the non-select storage unit that carries out that memory cell same bit lines BL that " 1 " data read links to each other in, word line WL is a negative potential, so the tagma keeps negative potential, ionization can not bump.With with other the non-select storage unit that carries out that memory cell same bit lines BL that " 0 " data read links to each other in, still word line WL keeps negative potential, the hole does not take place emit.

Figure 10 is to use each " 1 " data of identical playback mode and the read/write actions of " 0 " data with Figure 11.In the action of reading of the moment of Figure 10 and Figure 11 t1, same with Fig. 8 and Fig. 9 respectively.After reading, at moment t2, word line WL becomes more high potential, when same selected cell writes " 0 " data, applies negative potential (Figure 10) for simultaneously bit line BL, when writing " 1 " data, applies positive potential (Figure 11) for bit line BL.Therefore, in the unit that " 0 " data are provided, the drain region knot becomes forward bias, emits the hole in tagma.In the unit that " 1 " data are provided, near the ionization that bumps the drain region is injected and the maintenance excess holes to the tagma.

Figure 12～Figure 15 makes bit line BL be pre-charged to 0V, after word line is selected, to bit line BL supplying electric current, adopts the action waveforms of reading/refreshing and reading when carrying out the 2nd playback mode of discriminating data according to the unit rate of climb of bit line BL/write.

Figure 12 and Figure 13 are respectively reading/refresh activity of " 1 " data and " 0 " data.Make the word line WL of maintenance negative potential rise to positive potential at moment t1.At this moment which of threshold value Vth0, the Vth1 of " 0 ", " 1 " data word line potential as shown in Figure 7, be set in than and all want high value.Perhaps, same with the 1st playback mode, also word line potential can be located between threshold voltage vt h0, the Vth1 of " 0 ", " 1 " data.And, at moment t2 to the bit line supplying electric current.Therefore, during " 1 " data, the conducting of the memory cell degree of depth, the current potential of bit line BL rises little (Figure 12), during " 0 " data, the electric current of memory cell little (or not flowing electric current), the bit line current potential rises rapidly.Thereby judgement " 1 ", " 0 " data.

And, at moment t3, during sense data " 1 ", provide positive potential (Figure 12) to bit line BL, when sense data is " 0 ", provide negative potential (Figure 13) to bit line BL.Therefore, when select storage unit was " 1 " data, leakage current flow through the generation ionization by collision, injected and the maintenance excess holes to the tagma, write " 1 " data once more.During " 0 " data, the drain region knot keeps forward bias, and writing does not once more have " 0 " of excess holes data in the tagma.

At moment t4, word line WL is a reverse bias, finishes to read/refresh activity.

Figure 14 and Figure 15 are according to " 1 " separately data of identical playback mode and reading/write activity of " 0 " data.The action of reading among Figure 14 and Figure 15 at moment t1 and t2, same with Figure 12 and Figure 13 respectively.After reading, when same selected cell writes " 0 " data, supply with negative potential (Figure 14), supply with positive potential (Figure 15) to bit line BL when writing " 1 " data to bit line BL.Therefore, in the unit that " 0 " data are provided, the drain region knot becomes forward bias, emits the excess holes in tagma.In the unit that " 1 " data are provided, big leakage current flows through, and near the ionization that bumps the drain region is injected the maintenance excess holes to the tagma.

As above, the DRAM unit of the 1st embodiment of the present invention is made of the simple MOS transistor with the unsteady tagma that isolates with other unit electricity, can realize 4F ²Cell size.And, float the control of Electric potentials utilization in tagma and the capacitive coupling of gate electrode, and the back of the body grid-control system that need not for example come from the SOI substrate back.Source diffused layer also is a fixed potential.That is, the control of reading/writing is only carried out with word line WL and bit line BL, and simple.And then memory cell is essentially nondestructive read-out, thereby needn't on every bit lines sense amplifier be set, and the layout of sense amplifier just easily.Moreover be the electric current playback mode, even noise is strong, for example also can read to disconnect the bit line mode.And the manufacturing of memory cell is also simple.

And, consider when improving logic LSI performance from now on that the SOI structure will become important technology.The situation that the logic LSI of the DRAM of the present invention the 1st embodiment and such SOI structure loads in mixture also has prospect very much.This is because different with the existing DRAM that adopts electric capacity, does not need the technology different with the technology of logic LSI, and it is simple that manufacturing process becomes.

And then, the SOI structure DRAM of the present invention the 1st embodiment, the situation that makes the SOI structure with existing 1 transistor/1 capacitive based DRAM compares, and the advantage that obtains good storage retention performance is arranged.Even make the SOI structure with existing 1 transistor/1 capacitive based DRAM, then accumulate the hole in the semiconductor body of floating, transistorized threshold value is reduced, transistorized subthreshold current increases.It degenerates the storage retention performance.To this, having only in 1 transistorized memory cell of the 1st embodiment of the present invention, the transistor path, the data retention characteristics that do not reduce stored charge are pure only by the decision of pn junction leakage, and do not have the problem of subthreshold value electric leakage.

In fact, whether reliable the practical aspect of the memory cell of the present invention the 1st embodiment is, judged by the following this criterion of enumerating.

(a) retention performance in hole, tagma whether enough (can reach the retention time about 10 seconds).

(b) can reach enough " 1 " writing speed (can reach 10 nanoseconds of writing speed, write fashionable can reach body electric current above about 20hA).

(c) " 0 " selectivity of writing whether enough (can reach about the difference Δ VB=1V of bulk potential of " 0 " data and " 1 " data).

(d) whether enough the electric capacity between grid and the tagma come greatly compared with the pn junction capacitance, and whether the threshold value of taking-up " 1 " data is big.

Below carry out the checking of these criterions.

[about the electric capacity retention time leakage current of memory cell]

Can think that it is RT=10sec (second) that the mean value of the cell stores of the DRAM of 1G memory cell retention time is arranged.By 0.1 μ m rule, when the gate oxidation thickness of establishing memory cell was tox=2.5nm, gate oxidation films electric capacity was 14fF/cm ², and to establish the grid area be 0.01 μ m ², then gate oxidation films capacitor C ox is Cox=0.14fF.If comprise the pn junction capacitance Cj=0.08fF that illustrates later, then all electric capacity is Ctotal=0.22fF.

During stored charge, during the storage retention time RT=10sec, making each unit leakage current Ileak/node (I electric leakage/node) of potential change Δ V=0.1V is following numerical expression 1 on this gate capacitance

(numerical expression 1) Ileak/node=Ctotal Δ V/RT=2.2 * 10 ^-18A/node

If the silicon layer thickness on the SOI substrate is 100nm, the pn junction area is 0.1 μ m * 0.1 μ m * 2=0.02 μ m ², thereby the leakage current Ileak/area that obtains per unit area is following numerical expression 2.

(numerical expression 2) Ileak/area=2.2 * 10 ^-18/ 0.02=1.1 * 10 ^-16A/ μ m ²

Leakage current when the pn on the SOI substrate ties the reverse bias 2V left and right sides is that this is below horizontal, just guarantees averaging unit storage retention time RT=10sec, just obtains the storage retention performance with the same level of the capacitive based DRAM in 1 transistor/1.By the way, so far,, reported 1～3 * 10 as the pn junction leakage on the SOI substrate ^-17The value (1995Symp.VSLI Tech. P.141) of A/ μ m (the every μ m of word-line direction).Thus, can think that above-mentioned storage retention performance can fully realize.

[" 1 " write time and body electric current]

Write time is by the electric capacity and the body electric current I sub decision of unit node (grid).As mentioned above, gate capacitance is made as Ctotal=0.22fF.The specification of write time as twr=10nsec, is write voltage Δ V=1V to the tagma in this time, and needing the body electric current is numerical expression 3.

(numerical expression 3)

Isub＝Ctotal·ΔV/twr

＝0.22×10 ^-15×1/10×10 ^-9

＝22nA

The leakage current Ids that flows through the cell transistor raceway groove is made as 10 μ A, and above-mentioned body electric current I sub is about 2/1000.Supply with between drain-source about voltage Vds=2V, and when ionization by collision takes place, just can flow through the body electric current of needs.

[selectivity that " 0 " writes and semaphore]

Memory cell C-V curve (voltage Vgb between the grid body and the relation of capacitor C gb) becomes Figure 16.If the acceptor concentration in tagma is NA=10 ¹⁸/ cm ³, flat band voltage VFB=-1.2V.Carry out " 1 " at word line voltage Vwl=1V and write (bulk potential VB=0.6V), after writing, word line potential is descended always, at first because of the shielding of channel inversion layer, capacitor C gb is zero.And the threshold voltage vt h1=0V of supposition " 1 " unit even word line potential drops to 0V, can not make bulk potential VB change yet, and capacitor C gb comes to the surface, and word line potential is threshold voltage vt h1, i.e. the point of Vwl=0V.At this moment, voltage is Vgb=-0.6V between the grid body.

And, at NA=10 ¹⁸/ cm ³, during drain voltage Vd=0V, the electric capacity of pn knot per unit area is 4fF/ μ m ²Junction area is 0.1 μ m * 0.1 μ m * 2=0.02 μ m ²The time, the pn junction capacitance is Cj=0.08fF.In Figure 16, the Cgb/Cox of Vgb=-0.6V is made as 0.8, and during Cox=0.14fF, gate voltage is following numerical expression 4 to the capacitive coupling in tagma than λ.

(numerical expression 4) λ=Cgb/ (Cgb+Cox)

＝0.14×0.8/(0.14×0.8+0.08)

＝0.58

Therefore, word line potential descends, and when the capacitor C gb between grid and the body began to occur, the tagma potential change was about 60% to the ratio of word line potential variation.When word line potential was descended, bulk potential also descended, yet Vgb increases to the more negative side of ratio-0.6V.Capacitor C gb increases like this, reduces because of capacitive coupling makes bulk potential.At last, as shown in figure 16, drop to word line potential Vwl=-1.3V, establishing average capacitance coupling ratio λ is 0.6 always, and the tagma is from initial 0.6V, and the Δ VB=1.3V * 0.6=0.78V that only descends becomes-0.18V.At this moment, Vgb=-1.12V.

That is, by injecting excess holes, carrying out after " 1 " data that bulk potential becomes VB=0.6V write, is can keep data under the Vwl=-1.3V at word line potential, because capacitive coupling, bulk potential remains on-0.18V.Under this state, make the bit line current potential drop to negative potential to certain selected cell and carry out " 0 " when writing and making bulk potential to reduce, become-condition below the 0.18V with bulk potential, though word line potential for the non-selected cell of-1.3V in the hole in tagma also flow into the drain region, destroy data.Therefore, regulation " 0 " data of not destroying data are write fashionable bulk potential minimum value and are-0.18V.The voltage max that writes of " 1 " data is built-in voltage 0.6V, thus the maximum of semaphore become 0.6V-(0.18V)=0.78V.So above-mentioned Δ VB itself is exactly " 0 " data and the semaphore of " 1 " data poor (bulk potential poor).

[affirmation nondestructive read-out]

As described above, the memory cell of the present invention the 1st embodiment is carried out nondestructive read-out in principle.In order in fact to guarantee nondestructive read-out, need to confirm:

(1) make to go out to move, also should not have to the tagma injected hole to the unit weighs of " 0 " data is re-reading,

(2) make the unit to " 1 " data repeat to read action, the tagma should not have the hole yet.

At this moment number of repetition maximum Nmax is equivalent between certain once refreshes and refreshes next time (for example 128msec), same unit is read the situation of action (100nsec) continuously, thereby be Nmax=128msec/100nsec=1.28 * 10 ¹⁶About inferior.Can think that the non-destructive (1) that keeps " 0 " data of tagma hole accumulation state is crucial.So the streaming current when reading also need be read in the linear zone of for example low current about Vds=0.5V.Perhaps, adopt electric current not flow to the mode of the unit of " 0 " data, thereby guaranteeing that on the non-destructive be desirable as the 1st playback mode of front.

More than, carried out the checking of criterion, show the DRAM realization possibility basically of the present invention the 1st embodiment.Secondly, more specifically say, analyzed the DRAM performance of the present invention the 1st embodiment, order illustrates its result.

[the bit line potential change when reading]

At first, checking is with the 2nd playback mode of Figure 12 and Figure 13 explanation, i.e. bit line potential change when bit line is supplied with certain electric current and read.Figure 17 is the equivalent electric circuit that is used for this checking.For the sake of simplicity, the current potential of bit line BL is pre-charged to 0V, the current potential Vwl of word line WL, in t＞0, shown in following numerical expression 5, the value of setting more than the threshold voltage vt h (Vth0, Vth1) that is assumed at memory cell MC.

(numerical expression 5)

Vwl＞Vth

Be located at t＞0 constantly, supply with the constant current that becomes Ic, establish constant this electric current I c to bit line BL, shown in following numerical expression 6, littler than saturation current Idsat at the Vgs=Vwl of cell transistor.

(numerical expression 6)

Ic＜Idsat＝(k/2)(Vwl-Vth) ²

But, k=(W/L) (ε ox/tox) μ eff

At this moment, the variation of the current potential Vb1 of bit line BL is designated as Ids with the leakage current of cell transistor, and with following numerical expression 7 expressions.

(numerical expression 7)

DVbl/dt=(1/Cb1) (Ic-Ids) cell transistor moves in the range of linearity, thereby Vb1＜Vw1-Vth establishment, and at this moment the leakage current Ids of cell transistor is by following numerical expression 8 expressions.

(numerical expression 8) Ids=k[Vw1-Vth-(1/2) Vb1] Vb1 carries out integration to numerical expression 8 substitution numerical expressions 7, can obtain following numerical expression 9

(numerical expression 9) Vb1=α β [1-exp (t/t0)]/[β-α exp (t/t0)] but α=Vw1-Vth+[(Vw1-Vth) ²-2Ic/k] ^1/2

β＝Vw1-Vth-[(Vw1-Vth) ²-2Ic/k] ^1/2

t0＝2Cb1/[k(α-β)]

By supposition numerical expression 5 and numerical expression 6, satisfy α＞β＞0.Therefore, numerical expression 9 is increase functions of relevant projection with time t, and is Vb1 (0)=0, Vb1 (∞)=β.

Figure 18 represents the result of calculation of numerical expression 9.Suppose the threshold value Vth0=0.3V of " 0 " data cell, the threshold value Vth1=-0.3V of " 1 " data cell, the threshold value Vthd=0.05V of dummy cell, bit line capacitance Cb1=100fF, cell current gain coefficient k=2.0 * 10 ^-5(A/V ²), and, adopt Ic=0.9Idsat=13 μ A, Vw1=1.5V, the bit-line voltage Vb11 when each signal voltage Vsig0, Vsig1 and the bit-line voltage Vb10 when representing " 0 " data together, " 1 " data with reference to bit-line voltage Vb1d.The result rises from word line as can be known thus, after 10nsec, obtains the 100mV signal.

As for dummy cell, can use the mode of suitably setting bulk potential with the MOS transistor of memory cell same configuration.This is the threshold value because of memory cell, and self-adjusting ground is with the cause of process variations or temperature change.By selecting the bulk potential of dummy cell at this moment, just can set the semaphore of the best " 0 ", " 1 " data.

[about " 0 " writing speed]

In the 1st embodiment of the present invention, as described above, " 0 " writes is the P type tagma by making memory transistor and the pn knot forward bias in N type drain region, extracts the hole in tagma.As for the speed that this " 0 " writes, utilize the equivalent electric circuit of Figure 19 to discuss below.

At t=0, p layer and the n layer of establishing the pn knot are in poised state simultaneously under 2.2V.In t＞0, when the n side is 0V, calculates tagma (p type layer) current potential and how to change with capacitor C.Suppose that at the p of moment t type layer current potential be V, then following numerical expression 10 is set up.

(numerical expression 10) $t=-C\underset{v0}{\overset{v}{\∫}}\mathrm{dV}/I$

Here, I is the pn junction current, and with following numerical expression 11 expressions.

(numerical expression 11) I=Is[exp (V/ η Vt)-1]

In numerical expression 11, Is is a saturation current, and η is the coefficient between 1～2, and Vt is thermal voltage (ThermalVoltage), and Vt=kT/q.In the numerical expression 11 substitution numerical expressions 10 and carry out integration, obtain following numerical expression 12.

(numerical expression 12) V=η Vtln[1/{1-[1-exp (V0/ η Vt)] exp (t/t0) }]

Here, t0 is the time constant that provides at t0=C η Vt/Is.Use the numerical value of following numerical expression 13, it is Figure 20 that numerical expression 12 is carried out The numerical results.

(numerical expression 13) Is=JsAjJs=6.36 * 10 ^-5A/m ²Aj=0.01 μ m ²T=8.5 ℃ of Vt=0.0309 η=1t0=10.7secV0=2.2V from the numerical result of Figure 20 as can be known, " 0 " is write fashionable, at about 1nsec, bulk potential (P type layer) drops to below the 0.7V.

[about the potential change in tagma]

The front, the selectivity about " 0 " writes with reference to Figure 16, has illustrated the relation of word line potential and bulk potential, yet following with more detailed investigation bulk potential variation.That is, relevant after writing under the positive word line potential Vw1, make word line potential drop to negative potential and keep data, make word line rise to that positive potential is read and in the action that current potential Vr reads, how the current potential that describes the expression tagma in detail changes once more.

The capacitor C gb of per unit area utilizes the potential difference Vgb between grid and tagma between the tagma of the grid of cell transistor and SOI substrate (P type layer), represents with following numerical expression 14.

(numerical expression 14) Cgb/Cox=1/[1+2lD ²(Vgb-δ)/Vt] ^1/2

The capacitor C ox of the per unit area of gate oxidation films utilizes dielectric coefficient ε ox and thickness of oxidation film tox, represents with Cox=ε ox/tox.LD is with the dimensionless number that γ=(ε si/ ε ox) tox carries out normalization with Debye length (DebyeLength) LD, and is provided by following numerical expression 15.

(numerical expression 15) lD=(ε ox/ ε si) LD/tox=(ε ox/ ε si) [kT ε si/ (q ²NA)] ^1/2/ tox

Here, according to following conditional decision parameter δ.That is, derive numerical expression 14 by the depletion layer thickness wp that spreads in the following numerical expression 16 expression tagmas (it is the depletion layer thickness Wp of reality to be carried out the dimensionless number that obtains after the normalization with γ equally).

(numerical expression 16)

wp＝-1+[1+lD ²(Vgb-δ)/Vt] ^1/2

Here, under Vgb=VFB (flat band voltage), become the condition of so-called wp=lD, promptly provide following numerical expression 17.

(numerical expression 17)

lD＝-1+[1+lD ²(Vgb-δ)/Vt] ^1/2

Numerical expression 17 is found the solution, and parameter δ is following numerical expression 18.

(numerical expression 18)

δ＝VFB-(1+2/lD)Vt

By numerical expression 14 and numerical expression 18, obtain the dependence of Cgb, yet it can not cover wide Vgb zone to Vgb.Therefore, when voltage Vgs surpasses transistorized threshold value Vth between the grid source, establish Cgb=0, Cgb/Cox surpasses at 1 o'clock simultaneously, and it is replaced into 1, calculates the Cgb value of corresponding wide Vgb value.

Its result of calculation is shown in Figure 21.It is when word line is the P type polysilicon bar utmost point, obtains cell word lines of " 0 " data and the voltage Vgb between the tagma result to the relation of capacitor C gb.Condition is: tox=2.5nm, NA=5 * 10 ¹⁸/ cm ³, 85 ℃ of temperature, VFB=0.1V, Vth0=1.5V, VB=-0.7V, Cox=0.14fF, Cj=0.08fF.

On the other hand, bulk potential changes delta Vb represents with following numerical expression 19 the changes delta Vg of gate voltage.

(numerical expression 19) Δ Vb=[Cgb/ (Cgb+Cj)] Δ Vg

Here, Cj is the electric capacity (the pn junction capacitance that illustrates previously) that series connection enters body, establishes it and is steady state value, and numerical expression 19 distortion are obtained numerical expression 20,

(numerical expression 20)

ΔVg＝(1+Cgb/Cj)ΔVgb

Numerical expression 20 is carried out integration, just become following numerical expression 21.(numerical expression 21) $\mathrm{Vg}-\mathrm{<figure-callout\; id="0"\; label="Vg"\; filenames="A0114506000541.png,A0114506000551.png"\; state="\{\{state\}\}">Vg</figure-callout>}0=\underset{\mathrm{<figure-callout\; id="0"\; label="Vgb"\; filenames="A0114506000541.png,A0114506000551.png"\; state="\{\{state\}\}">Vgb</figure-callout>}0}{\overset{\mathrm{Vgb}}{\&Integral;}}\&lsqb;1+\mathrm{Cgb}/\mathrm{Cj}\&rsqb;\mathrm{dVgb}$

Rewrite numerical expression 21, become numerical expression 22.(numerical expression 22) $\mathrm{Vgb}-\mathrm{<figure-callout\; id="0"\; label="Vgb"\; filenames="A0114506000541.png,A0114506000551.png"\; state="\{\{state\}\}">Vgb</figure-callout>}0=(\mathrm{Vg}-\mathrm{Vg}0)-\underset{\mathrm{<figure-callout\; id="0"\; label="Vgb"\; filenames="A0114506000541.png,A0114506000551.png"\; state="\{\{state\}\}">Vgb</figure-callout>}0}{\&Integral;}\&lsqb;1+\mathrm{Cgb}/\mathrm{Cj}\&rsqb;\mathrm{dVgb}$

Calculate this numerical expression 22, can obtain the changes delta Vb of bulk voltage VB by the change in voltage Δ Vg of gate voltage Vw1 (word line).For the unit of " 0 " data, result calculated is shown in Figure 22 under will be when front Figure 21 the calculates identical parameter condition.From this result as can be known, carry out " 0 " when for example establishing word line for 2.0V and write, the tagma is-0.7V, and word line is dropped to-2V and when keeping data, and at this moment bulk potential remains on-2.1V.And then when making word line rise to 1.0V to read, the tagma can only rise to pact-0.9V.That is, to the unit of " 0 " data, to write fashionable bulk potential low for ratio when reading, and therefore, becomes and read tolerance limit and enlarge 0.2V.

" 1 " data cell is carried out same result calculated be shown in Figure 23.And at this moment capacitor C gb shown in Figure 24 is to the dependence of voltage Vgb.Used parameter all is identical during with Figure 21 and Figure 22.As seen when " 1 " data, the tagma becomes 0.6V after just having write, and the tagma is-1.0V under the state of word line maintenance-2.0V.Writing of " 0 " data can be up to bulk potential-1.0V on the principle, however " 0 " dropping in writing always-pn junction capacitance coupling (coupling ratio is 18%) when the bit line of 1.5V is got back to 0V makes and rises 0.3V on the tagma, just become-0.7V.Therefore under the situation that " 0 " data of Figure 22 write, regulation has just write later current potential and has been-0.7V.

Situation about writing with " 1 " has the capacitive coupling of coming from bit line too, yet writes differently with " 0 ", flows through body electric current I sub exactly and in the carrying out that writes " 1 " data, rises to current potential V with following numerical expression 23 expressions from built-in voltage 0.6V.(numerical expression 23) Isub=Is[exp{V/ (η Vt)-1}]

Substitution Isub=14nA, Is=6.36 * 10 ^-20A, Vt=0.031V, η=1.2 obtain V=0.96V.Therefore, bulk potential after " 1 " data have just write near 1V, even think that bit line drops to 0V and because coupling decline 0.3V from 1.5V, also more than 0.6V, then, because of the forward current of diode becomes 0.6V.That is, can think in fact that it is 0.6V that " 1 " data have just write later bulk potential.

So far, suppose sometimes in the calculating that flat band voltage is VFB=0.1V.It is corresponding to the situation of the gate electrode (word line) that forms p type polysilicon on the P type silicon layer of SOI substrate.Secondly, about on same SOI substrate, when forming gate electrode, illustrate and carry out same result calculated by n type crystal silicon film.At this moment, flat band voltage is VFB=-1.1V.

Figure 25 is to " 1 " data cell, obtains the result of capacitor C gb-voltage Vgb.Figure 26 is to " 1 " data cell equally, obtains the result who concerns between word line voltage Vwl and the bulk potential VB.Parameter except that flat band voltage is all same with the situation of Figure 21 of front and Figure 22.No matter any situation, all defined threshold Vth1=0V.

From these results, can be used as the threshold value Vth0=1V that guarantees " 0 " data, word line is write the fashionable 1.5V that is, is 0.5V when reading.If the word line voltage-2.5V when data keep, then the body of " 1 " data cell drops to-0.8V.So,, have only 0.2V to become unfavorable to same word line amplitude with the situation comparison of the VFB=0.1V that uses the p type polysilicon bar utmost point.

Figure 27 and Figure 28 are to " 0 " data cell equally, the result of the capacitor C gb-voltage Vgb characteristic when obtaining VFB=-1.1V, word line voltage Vw1-bulk voltage VB characteristic.Threshold setting Vth0=1V." 0 " writes later bulk potential and is-0.8V, yet when bit line was got back near the precharge potential 0V, because the coupling of pn knot, bulk potential is buoyance lift 0.3V only, supposes to become-0.5V.At this moment, writing fashionable word line also is 1.5V, is 0.5V when still reading, so bulk potential is only recovered 0.15V, becomes-0.65V.

Respectively the operation condition of the situation of the situation of the above p type polysilicon bar utmost point and the n type polysilicon bar utmost point being concentrated into table, is exactly following table 1 and table 2.[1]pVw1 ( read ) ＝1VVw1 ( hold ) ＝-2VVw1 ( write ) ＝2VVb1 ( “0”write ) ＝-1.6VVb1 ( “1” write ) ＝1.6VVth0＝1.5VVth1＝0.5V“1”VB＝0.6V“0”VB＝-1V[2]nVw1 ( read ) ＝0.5VVw1 ( hold ) ＝-2.5VVw1 ( write ) ＝1.5VVb1 ( “0”write ) ＝-1.4VVb1 ( “1” write ) ＝1.4VVth0＝1.0VVth1＝0V“1”VB＝0.6V“0”VB＝-0.6V

In addition, in the above table 1,2, " 1 " writes fashionable bit line current potential Vb1 (" 1 " write) should be by the decision of substrate current (hole current) and write time, though uncertain, the set point of supposition is shown.From above very clear, adopt the p type polysilicon bar very favourable.The word line amplitude is any situation no matter, also all is 4V.With regard to making its further reduction voltage, need take following measure.(A) deviation (B) of dwindling threshold value Vth guarantees that memory cell current (C) reduces the ratio of Cj/Cox

About (A) and (B), so far suppose Δ Vth=Vth0-Vth1=1.0V, but it might be strict controlled in about 0.8～0.6V.Realize that it is little of 2 * 1.2V=2.4V just might to suppress the word line amplitude after the Δ Vth=0.6V.

Below, (C) discussed in detail.This is because do not reduce Δ Vth tolerance limit, and can realize the method for the lower voltage of word line amplitude.

With regard to the requirement of (C), the silicon layer thickness Tsi of SOI substrate is thinned to further more estimable 100nm is also thin than hereto.Meanwhile or independently, can be by impurity concentration and its adaptation that reduces n type source, leaks diffusion layer.The former, is by dwindling the pn junction area, corresponding minimizing pn junction capacitance Cj, the latter, therefore the condition that provides depletion layer to stretch to n type diffusion layer one side certainly reduces the source, leaks the junction capacitance Cj in diffusion layer and tagma.

But, about the junction capacitance Cj=0.08fF that need not so far be used to verify, but the situation of half Cj=0.04fF, respectively at Cgb-Vgb curve shown in Figure 29 and Figure 30 and Vw1-VB curve.Condition except that Cj is all identical with Figure 23 and Figure 24, and gate electrode is a p type polysilicon.It is 50nm that Cj=0.04fF is equivalent to set silicon layer thickness.

By this result as can be known, about " 1 " data cell, write after the 0.6V bulk potential, reduce word line when-2.0V, bulk potential just drops to-1.3V.Therefore, bulk potential is dropped to-word line potential that 1V needs, promptly data keep going up required word line potential Vw1 (hold) be Vw1 (hold)=-1.6V.

Equally, about " 0 " data cell, Cgb-Vgb curve and the Vw1-VB curve when adopting Cj=0.04fF shown in Figure 31 and Figure 32 respectively.Condition except that the Cj all situation with front Figure 21 and Figure 22 is identical.

As previously discussed, adopt the SOI substrate of thin silicone layer (Tsi=50nm), the operation condition of the DRAM unit during corresponding with table 1 minimizing Cj puts together, and is exactly following table 3.(table 3) Vw1 (read)=0.8VVw1 (hold)=-1.6VVw1 (write)=1.6VVb1 (" 0 " write)=-bulk potential VB=0.6V " 0 " bulk potential VB=-1V when data cell read of 1.6VVb1 (" 1 " write)=1.6VVth0=1.3VVth1=0.3V " 1 " when data cell is read

By above result as can be known, with silicon layer thickness Tsi, half is 50hm from the 100hm attenuate, reduces after the capacitor C j, just can make the word line amplitude be reduced to 3.2V from 4V.What still should pay attention to is to guarantee the threshold difference Δ Vth of 1V as data " 0 ", " 1 ".

If the silicon layer thickness of SOI substrate is thinned to about 30nm, just can further realize lower voltage.But silicon layer is thin excessively, has silicon layer to exhaust and lose the danger of the function of storage own fully.Therefore, can think that silicon layer thickness is suitable about with 50nm.

Figure 33 represent bulk potential VB-1V and the threshold difference Δ Vth of 0.6V and the relation of silicon layer impurity concentration NA.But gate oxide film thickness is Tox=2.5nm, when temperature is T=85 ℃.This shows,, approximately need NA=1.0 * 10 in order to ensure Δ Vth=1V ¹⁹/ cm ³This makes the impurity concentration overrich slightly, thereby sets NA=8 * 10 ¹⁸/ cm ³, guarantee Δ Vth=0.8V.At this moment, the operation condition of his-and-hers watches 3 is revised a little, is exactly following table 4.(table 4) Vw1 (read)=0.7VVw1 (hold)=-1.6VVw1 (write)=1.4VVb1 (" 0 " write)=-bulk potential VB=0.6V " 0 " bulk potential VB=-1V when data cell read of 1.6VVb1 (" 1 " write)=1.4VVth0=1.1VVth1=0.3V " 1 " when data cell is read

In table 4, " 1 " writes fashionable bit-line levels Vb1 (" 1 " write) by substrate current (hole current) and write time decision, thereby 1.4V is the set point of supposition.Can think that cell transistor is not a LDD structure and as ordinary construction, along with increasing substrate current Isub, can reduce voltage to a certain extent yet.

In the above operation condition, the maximum voltage of cell transistor is 3.0V.Gate oxide film thickness is Tox=2.5nm, therefore, in the moment that " 1 " data write, makes gate oxidation films stand the electric field of about 12MV/cm, exists unstable on the reliability., in order to ensure reliability, increase gate oxide film thickness, the capacitive coupling ratio that can be used in the control volume current potential worsens, thereby improper.So,, can adopt the high Al of dielectric coefficient for gate insulating film ₂O ₃Wait other dielectric film to replace silicon oxide layer.

For the purpose of further reducing voltage, the silicon layer thickness Tsi of SOI substrate is thinned to about 30nm, make the threshold value control of cell transistor good, it is greatly desirable making its mobility simultaneously.After considering these, think and to reduce voltage up to 2.0～2.5V.

Transistorized cell current Ids1 of " 1 " writing unit that can guarantee during respectively the threshold difference Δ Vth shown in Figure 33 and the data readout time Δ t corresponding with it are illustrated among Figure 34 and Figure 35.Obtain cell current with Ids1=(k/2) (Δ Vth/2).And readout time, Δ t was, the word line potential when reading is set in the middle of Vth1 and the Vth0, and the unit of " 1 " data is connected, and obtained the time of bit line from precharge potential to discharge 200mV of capacitor C b1=100fF.

By this result, for NA=6 * 10 ¹⁸/ cm ³, can obtain Ids1=1.4 μ A, Δ t=15nsec.

The result who how to descend is on earth fastened in bulk potential VB when Figure 36 is the maintenance of investigation " 1 " data cell and the pass of threshold value Vth1.Condition is gate oxide film thickness tox=2.5nm, impurity concentration NA=5 * 10 ¹⁸/ cm ³, flat band voltage VFB=0.1V, the bulk potential VB1=0.6V of " 1 " data, gate oxidation films capacitor C ox=0.14fF, junction capacitance Cj=0.04fF.And it is Vw1=Vth1-2V that word line keeps current potential.

By this result, when Vth1=0.5V was above, bulk potential and Vth1 during maintenance rose simultaneously.When Vth1＜0.5V, bulk potential-0.93V is saturated.This means that if word line voltage drops to below Vth1＜0.5V always, then capacitor C gb is in saturated as gate oxidation films capacitor C ox.

Therefore, when flat band voltage VFB=0.1V, when promptly gate electrode is p type polysilicon film, should set Vth1＜0.5V.On the other hand, as you know, in order to ensure Δ Vth=Vth0-Vth1=0.8V, so Vth0＜1.3V.So, we can say Vth0=1.1V, Vth1=0.3V is good a selection.

Above working point is all concluded together, just become following table 5, and device parameters is concluded together, just become table 6.(table 5) Vth0=1.1V, Vth1=0.3VVw1 (read)=0.7VVw1 (hold)=-1.7VVw1 (write)=1.5VVb1 (" 0 " write)=-1.5VVb1 (" 1 " write)=1.5VVB (" 1 " read)=0.6VVB (" 0 " read)=-1.0VVB (" 1 " write)=0.6VVB (" 0 " write)=-0.9VVB (" 1 " hold)=-1.0VVB (" 0 " hold)=-2.4VVmax=3.2V (non-selection WL and " 1 " write the Vds between the BL) (table 6) p type polysilicon bar utmost point NA=5 * 10 ¹⁸/ cm ³Tox=2.5nm channel length L=0.1 μ m, channel width W=0.1 μ mTsi=50nmk=(W/L) (ε ox/tox) μ eff=2.0 * 10 ^-5A/V ²

At this moment the DRAM unit read characteristic, pairs of bit line capacitor C b1=100fF, the time that always is added to the 200mV potential difference is Δ t=15nsec.

Under the situation (that is, the situation of the n type polysilicon bar utmost point) of VFB=-1.1V, the result who how to descend is on earth fastened in bulk potential VB when Figure 37 is the maintenance of investigation " 1 " data cell equally and the pass between the threshold value Vth1.Other condition is all same with Figure 36.At this moment also the hint should think Vth1＜-0.5V.At this moment working point and device parameters corresponding to table 5 and table 6, are exactly following table 7 and table 8.(table 7) Vth0=0.1V, Vth1=-0.7VVw1 (read)=0.3VVw1 (hold)=-2.7VVw1 (write)=0.5VVb1 (" 0 " write)=-1.5VVb1 (" 1 " write)=0.5VVB (" 1 " read)=0.6VVB (" 0 " read)=-1.0VVB (" 1 " write)=0.6VVB (" 0 " write)=-0.9VVB (" 1 " hold)=-1.0VVB (" 0 " hold)=-2.4VVmax=3.2V (non-selection WL and " 1 " write the Vds between the BL) (table 8) n type polysilicon bar utmost point NA=5 * 10 ¹⁸/ cm ³Tox=2.5nm channel length L=0.1 μ m, channel width W=0.1 μ mTsi=50nmk=(W/L) (ε ox/tox) μ eff=2.0 * 10 ^-5A/V ²

At this moment the DRAM unit read characteristic, pairs of bit line capacitor C b1=100fF is Δ t=15nsec up to the time of additional 200mV potential difference.But, if Vb1 (" 1 " write) is 0.5V, have then that to flow through substrate current Isub be enough problems, if it is risen to more than the 0.5V, this part maximum voltage Vmax will rise.This point is favourable to p type polysilicon is used for the gate electrode aspect, promptly, to by the threshold voltage vt h0 that reads the decision of characteristic and " 1 " write diagnostics, fashionable word line level Vw1 (write) is write in decision, yet be exactly will be brought up to by the bit line current potential Vb1 (" 1 " write) of " 1 " write diagnostics decision independently when also higher than word line potential Vw1, Vmax will be by Vb1 (" 1 " write)-Vw1 (hold) decision.If Vw1 (write) 〉=Vb1 (" 1 " write), then Vmax=Vw1 (write)-Vw1 (hold) can make operation voltage reach minimum.

The above end that calculates is DRAM unit to standard.In fact, have the manufacturing process of resulting from batch between, the change of cell transistor threshold value or the change of k between the wafer, in the wafer, in the chip, and, the change of the change of bit line capacitance, the word line level of design etc. is arranged.Also need to consider the coupling noise between the bit line.

In addition, also has the threshold value Vth change that causes by temperature.Use is during near the reference cell of memory cell, and the part that above-mentioned threshold variation factor has is compensated, and just may not exert an influence.

In other words, can think this playback mode, be only limited to basically in the chip of above-mentioned threshold variation factor discrete (deviation).With the threshold variation of temperature change, can systematicness make its elimination fully.

As mentioned above, the memory cell of the 1st embodiment of the present invention is that non-destruction is read on the principle, and is that electric current is read.Figure 39 represents to utilize the example of the sense amplifier layout of this memory cell characteristics.Dispose paired bit line BL, bBL in the both sides of sense amplifier SA, and supposition is the open bit lines less affected by adjacent ones mode.The side of pairs of bit line BL, bBL is when making word line WL activate, and the opposing party just makes and selects the empty word line DWL of dummy cell DC to carry out activate.Dummy cell DC is by constituting with the same MOS transistor of memory cell MC, supposes that its tagma provides the bulk potential in the middle of data " 0 ", " 1 ".

In the legend, 2 bit lines are to BL, bBL, by selecting door SG to select and coupling together with a sense amplifier SA.The bit line that connects a certain sense amplifier SA is disposed alternately with the bit line that is connected adjacent sense amplifier.At this moment, it is 2 to 4 memory cell MC sense amplifiers selecting simultaneously by a word line WL.That is, among the data of 4 memory cell MC of Xuan Zeing, in fact the memory cell data that is detected by sense amplifier SA is two simultaneously, and remaining memory cell data is not given the sense amplifier of reading.In the 1st embodiment of the present invention and since not in DRAM such destructiveness read, so can be this sense amplifier mode.

, regenerate as the DRAM of 0.1 μ m rule and to realize the DRAM of the 1st embodiment of the present invention, two following conditions are all set up and are seemed important.Condition 1: make full use of the substrate bias effect; Condition 2: reduce the pn junction leakage.These two conditions 1,2 are all relevant with the impurity concentration in tagma and require opposite mutually.

Condition 1 is to need by big substrate bias effect, so that enlarge the threshold voltage difference of " 0 ", " 1 " data, so impurity concentration (being led) the NA needs of the p type silicon layer 12 (tagmas) of Fig. 1, for example in NA=5 * 10 ¹⁸/ cm ³More than.With Figure 41 this situation is described.The relation that Figure 41 represents bulk potential VB and the threshold value Vth of nmos pass transistor is different appearance with acceptor concentration NA.

When acceptor concentration was NA1, if the threshold voltage difference of supposition " 0 ", " 1 " data is Δ Vth1, the threshold voltage difference when acceptor concentration NA2 is hanged down in supposition thus was Δ Vth2, and then Δ Vth1＞Vth2 sets up.That is,, just need more than acceptor concentration brings up to a certain degree in order to enlarge the threshold voltage difference of " 0 ", " 1 " data.

In addition, also need NA=5 * 10 ¹⁸/ cm ³Above acceptor concentration works in the fine MOS transistor of the about L=0.1 μ of channel length m really.

On the other hand, condition 2 is required on the assurance data retention characteristics, and at this moment, the impurity concentration in tagma is low certainly a bit good.In the DRAM generation of 0.1 μ m rule,, the pn junction leakage that leak in the source need be controlled at 3 * 10 in order in the tagma, to keep 10 seconds of data ^-17A/cm ²Below.In order to reduce the tunnel current as the leakage current main component, the electric field in the depletion layer that pn knot part forms must be controlled at 2.5 * 10 ⁵Below the V/cm.This is that the acceptor concentration in tagma is in NA=3 * 10 ¹⁷A/cm ³The following value that can realize.Under condition 1 desired above-mentioned acceptor concentration, the electric field in the depletion layer is 1.7 * 10 ⁵V/cm (during the 2V reverse biased) can not satisfy condition 2.

Figure 40 is corresponding with Fig. 1, and expression can be satisfied the structure with the DRAM unit MC of the 2nd embodiment of above this reciprocal condition 1,2.Opposite with the unit structure of Fig. 1, be positioned at the tagma that constitutes by p type silicon layer.Promptly under the situation of embodiment, by the connection source, leak the lower p type diffused layer 12a of the boron concentration (acceptor concentration) of diffusion layer 14,15 and with the source, leak the high P of boron concentration (acceptor concentration) of the middle body configuration of the orientation that diffusion layer opened in 14,15 minutes ⁺ Type diffusion layer 12b constitutes the tagma.P ⁺ Type diffusion layer 12b forms with the degree of depth up to the silicon oxide film 11 of bottom.

This unit structure is equivalent to the form of being seized on both sides by the arms the nmos pass transistor of high threshold voltage by two nmos pass transistors of low threshold voltage.At this moment all threshold voltages are by the P of middle body ⁺ Type diffusion layer 12b domination.On the other hand, the source, leak the pn knot between the p type diffused layer 12a that diffusion layer 14,15 constitutes low concentrations after, and by high concentration P ⁺The situation that the type diffusion layer forms whole tagma compares, and leakage current reduces.Above presentation of results can satisfy above-mentioned reciprocal two conditions 1,2.

Specifically, can obtain and so on effect, need to set what kind of concentration or desired location with the structure of Figure 40, for these, following explanation investigation result.Shown in Figure 42 A, Figure 42 B, tie the intensity distributions of obtaining depletion layer expansion and internal electric field E when adding reversed bias voltage V for the pn of n type diffusion layer (donor concentration ND) and p type diffusion layer (acceptor concentration NA).Suppose that the pn knot is an abrupt junction.Shown in Figure 42 A, Figure 42 B, the direction of traversing the pn knot is defined as X-axis.

At this moment, current potential in n type diffusion layer and the p type diffusion layer is made as φ D, φ A, and the front position in the n type diffusion layer of depletion layer is made as-xn, the front position in the p type diffusion layer, be made as xp, with electric field ED, the EA in numerical expression 24 expression Poisson's equation formulas, the n type diffusion layer p type diffusion layer.ε is the dielectric coefficient of silicon.(numerical expression 24) d ²φ D/dx ²=-(q/2 ε) ND (xn＜x＜0) d ²φ A/dx ²=(q/2 ε) NA (ED=-d φ D/dx (xn＜x＜0) the EA=-d φ A/dx of 0＜x＜xp) (0＜x＜xp)

Built in potential is made as φ bi, and boundary condition is with 25 expressions of following numerical expression.(numerical expression 25) ED (xn)=0 φ D (xn)=φ bi+VED (0)=EA (0) φ D (0)=φ A (0) EA (xp)=0 φ A (xp)=0

These boundary conditions of substitution are untied numerical expression 24, obtain following numerical expression 26.(numerical expression 26) ED=(q/ ε) NDx+A (xn＜x＜0) φ D=-(q/2 ε) NDx ²-Ax+B (xn＜x＜0) EA=-(q/ ε) NAx+C (φ A=(q/2 ε) NAx of 0＜x＜xp) ²(0＜x＜xp) is in numerical expression 26, and A～D is the constant by the boundary condition decision of numerical expression 25 for-Cx+D.After in the boundary condition formula of separating substitution numerical expression 25 of numerical expression 26, obtain following numerical expression 27.(numerical expression 27)-(q/ ε) NDxn+A=0-(q/2 ε) NDxn ²+ Axn+B=φ bi+VA=CB=D-(q/ ε) NAxp+C=0 (q/2 ε) NAxp ²-Cxn+D=0 numerical expression 27 is the equations that determine 6 unknown number xn, xp, A, B, C and D, by it is found the solution, obtains following numerical expression 28.(numerical expression 28) xn={2 ε NA (φ bi+V)/qND (NA+ND) } ^1/2Xp={2 ε ND (φ bi+V)/qNA (NA+ND) } ^1/2And maximum field intensity Emax is the electric field of ordering at x=0, and with following numerical expression 29 expressions.(numerical expression 29) Fmax=A=(q/ ε) NDxn

={ 2qNAND (φ bi+V)/ε (NA+ND) } ^1/2Width W=the xn+xp of whole depletion layer is following numerical expression 30.(numerical expression 30) W={2 ε (NA+ND) (φ bi+V)/qNAND} ^1/2

Electric-field intensity distribution has been shown in Figure 42 B.According to above preparation investigation result, secondly shown in Figure 43 A and Figure 43 B, investigation is divided into high acceptor concentration NA and the two-part situation of low acceptor concentration na to p type diffused layer.This is equivalent to the structure of drain junction one side of the embodiment unit structure of Figure 40.At this moment also abrupt junction is become in supposition.For the result with front preparation investigation compares, distance axis adopts capital X, and without lowercase x.The apical position Xp of the depletion layer of p type diffusion layer expansion surpasses the zone of low acceptor concentration na, is assumed to Xp＞L.

At this moment, Poisson's equation formula and electric field equation formula owing to can consider numerical expression 24, are divided into high acceptor concentration NA zone and low acceptor concentration na zone to p type diffusion layer, just become following numerical expression 31.With respect to current potential φ A, the electric field EA in high acceptor concentration NA zone, current potential, electric field with low acceptor concentration na zone are expressed as φ a, Ea respectively.(numerical expression 31) d ²φ D/dX ²=-(q/2 ε) ND (Xn＜X＜0) d ²φ a/dX ²=(q/2 ε) na (d of 0＜X＜L) ²φ A/dX ²(((boundary condition of L＜X＜Xp) is by 32 expressions of following numerical expression for the EA=-d φ A/dX of 0＜X＜L) for ED=-d φ D/dX (Xn＜X＜0) the Ea=-d φ a/dX of L＜X＜Xp) for=(q/2 ε) NA.(numerical expression 32) ED (Xn)=0 φ D (Xn)=φ bi+VED (0)=Ea (0) φ D (0)=φ a (0) Ea (L)=EA (L) Φ a (L)=φ A (L) EA (Xp)=0 φ A (Xp)=0 unties numerical expression 31, obtains following numerical expression 33.(numerical expression 33) ED=(q/ ε) NDX+A (Xn＜X＜0) φ D=-(q/2 ε) NDX ²-AX+B (Xn＜X＜0) EA=-(q/ ε) naX+C (Φ a=(q/2 ε) naX of 0＜X＜L) ²-CX+D (EA=-(q/ ε) NAX+E of 0＜X＜L) (Φ A=(q/2 ε) NAX of L＜X＜Xp) ²(in the numerical expression 33 of L＜X＜Xp), A～F is the constant by the decision of numerical expression 32 boundary conditions to-EX+F.Equation with the boundary condition of separating substitution numerical expression 32 of numerical expression 33 just can obtain following numerical expression 34.(numerical expression 34)-(q/ ε) NDXn+A=0-(q/2 ε) NDXn ²+ AXn+B=φ bi+VA=CB=D-(q/ ε) naL+C=-(q/ ε) NAL+E (q/2 ε) naL ²-CL+D=(q/2 ε) NAL ²-EL+F-(q/ ε) NAXp+E=0 (q/2 ε) NAXp ²-EXp+F=0 numerical expression 34 is the equations that determine 8 unknown number Xn, Xp, A, B, C, D, E and F.Separate by it, obtain following numerical expression 35.(numerical expression 35) Xn=-L (NA-na)/(NA+ND)

+L·{(NA/ND)(NA-na)(ND+na)

/(NA+ND) ²+(xn/L) ²} ^1/2Xp＝(1/NA)·[NA·Xn+(NA-na)·L]

Here, the xn in the numerical expression 35 represents the pn knot of front Figure 42 is stretched to the depletion layer of the n type diffusion layer of being untied, and is exactly that numerical expression 28 is represented.And maximum field Emax is the electric field at X=0, and with following numerical expression 36 expressions.(numerical expression 36) Emax=A=(q/ ε) NDXn

At this moment electric-field intensity distribution is shown in Figure 43 B.In numerical expression 35, if L is infinitely near 0, or acceptor concentration na is infinitely near NA, then can think Xn=xn.

According to above investigation result, will study the unit structure optimal condition of Figure 40 below particularly.At first, Figure 44 is that the high acceptor concentration of setting p type diffusion layer is NA=5 * 10 ¹⁸/ cm ³, low acceptor concentration is na=1 * 10 ¹⁷/ cm ³, the donor concentration of n type diffusion layer is ND=1 * 10 ²⁰/ cm ³, applied voltage V=2.0V, ambient temperature is 85 ℃, obtain low acceptor concentration zone width L, with depletion layer stretching, extension Xn, Xp between relational result.

In the unit of Figure 40, establishing channel length is 0.1 μ m, if from the source, the depletion layer of leakage stretches symmetry, for punchthrough effect does not take place, requires Xp＜5 * 10 ^-6Cm.In order to satisfy this condition, should be L＜4.0 * 10 by Figure 44 ^-6Cm=0.04 μ m.If estimate certain nargin, serve as suitable just with L=0.02 μ m.As can be known at this moment, the depletion layer Xp that stretches to p type diffusion layer invades high acceptor concentration NA area 0 .01 μ m.

By the condition same with Figure 44, the adjust the distance dependence of L of expression maximum field Enax then becomes Figure 45.During the suitable distance L of obtaining above=0.02 μ m, maximum field intensity is Emax=9.0 * 10 ⁵V/cm.With it and only by high acceptor concentration NA=5 * 10 ¹⁸/ cm ³The zone situation that constitutes whole tagma relatively descended, and maximum field has died down about 1/2.And then it is desirable being reduced to about 1/3 of this electric field.

Here follow, Figure 43 is studied the effect that reduces n type diffused layer donor concentration ND.This is because estimate, also this further stretches to n type diffusion layer depletion layer, makes the maximum field weakened.

Figure 46 is to Figure 44, is reduced to ND=1 * 10 at the donor concentration ND that the n type is expanded several layers ¹⁷/ cm ³The time, obtain the result that low acceptor concentration peak width L and depletion layer stretch Xn, Xp relation.And Figure 47 is corresponding with Figure 45, the adjust the distance dependence of L of expression maximum field intensity Emax.

By this result, source, the concentration one of leaking diffusion layer descend, just can obtain, and for example under L=0.025 μ m, Xp=0.03 μ m, maximum field intensity Emax=3.0 * 10 ⁵The value of V/cm.Figure 48 is illustrated under this optimal condition, the unit structure size of Figure 40 and the stretching, extension mode of depletion layer.

In case reduction source, drain region n type diffusion layer concentration just become problem to the resistance of its contact.Therefore, generally the mode that the bit line contact of DRAM is carried out it is desirable to contact hole is spread once more.Perhaps, adopt the silicide structure that on source, diffusion layer surface, drain region, forms metal silicide film also effective.

, the n type diffusion layer concentration in source, drain region is lower than ND=1 * 10 ¹⁷/ cm ³The time, as shown in figure 48, the depletion layer of the so big width of Xn=0.1 μ m is also in stretching to source, drain region diffusion layer.In order to suppress source, the drain region depletion layer of size like this, it is desirable adopting so-called LDD structure.

To the structure of Figure 40, will adopt the embodiment of the unit structure of LDD structure to be shown in Figure 49.Leak diffusion layer 14 by with the n type diffusion layer 14a of the low donor concentration of channel region adjacency and the n of high donor concentration ⁺ Type diffusion layer 14b constitutes.As for source diffused layer 15 too, by with the n type diffusion layer 15a of the low donor concentration of channel region adjacency and the n of high donor concentration ⁺ Type diffusion layer 15b constitutes.On source, drain region diffusion layer and the gate electrode, form metal silicide film 18 by the silicide operation.

But, also can think among the source of this LDD structure, the drain region, for example to have only drain region one side to be connected with bit line.

Then, discuss the stretching, extension and the electric-field intensity distribution of depletion layer when adopting the unit structure of this LDD structure particularly.Figure 50 A and Figure 50 B are corresponding with Figure 43 A and Figure 43 B, expression emphatically this unit structure for example the pn structure of drain region one side knot make and Electric Field Distribution.N type diffusion layer is made of the zone of low donor concentration nd and the zone of high acceptor concentration ND, and p type diffusion layer is made of the zone of low donor concentration na and the zone of high acceptor concentration NA.The peak width of low donor concentration nd is made as Ln, and the peak width of low acceptor concentration na is made as Lp.Set the zone of high donor concentration ND and the zone of high acceptor concentration NA, have the concentration that needs to limit on the resistance that contacts with the source region line by bit line contact or the transistor characteristic and determine respectively.

Suppose the Xp＞Lp that is stretched to of depletion layer, the reverse bias voltage condition of Xn＞Ln mode.At this moment, for numerical expression 32, the Poisson's equation formula is represented with following numerical expression 37.Regional current potential φ A, electric field EA for high acceptor concentration NA, regional current potential, the electric field of low acceptor concentration na are represented respectively as φ a, Ea, for regional current potential φ D, the electric field ED of high donor concentration ND, regional current potential, the electric field of low donor concentration nd are represented respectively as φ d, Ed.(numerical expression 37) d ²φ D/dX ²=-(q/2 ε) ND (d of Xn＜X＜Ln) ²φ d/dX ²=-(q/2 ε) nd (Ln＜X＜0) d ²φ a/dX ²=(q/2 ε) na (d of 0＜X＜Lp) ²φ A/dX ²=(q/2 ε) NA (the ED=-d φ D/dX of Lp＜X＜Xp) (Xn＜X＜-Ln) Ed=-d φ d/dX (Ln＜X＜0) Ea=-d φ a/dX (the ED=-d φ A/dX (Lp＜X＜Xp) following columns formula 38 expressions of boundary condition of 0＜X＜Lp).(numerical expression 38) ED (Xn)=0 φ D (Xn)=φ bi+VED (Ln)=Ed (Ln) φ D (Ln)=(Ln) Ed (0)=Ea (0) φ d (0)=φ a (0) Ea (Lp)=EA (Lp) φ a (Lp)=φ A (Lp) EA (Xp)=0 φ A (Xp)=0 unties numerical expression 37 to φ d, can obtain following numerical expression 39.(numerical expression 39) ED=(q/ ε) NDX+A (Xn＜X＜-Ln) φ D=-(q/2 ε) NDX ²-AX+B (Xn＜X＜-Ln) Ed=(q/ ε) ndX+C (Ln＜X＜0) Φ d=(q/2 ε) ndX ²-CX+D (Ln＜X＜0) Ea=-(q/ ε) naX+E (Φ a=(q/2 ε) naX of 0＜X＜Lp) ²-EX+F (EA=-(q/ ε) NAX+G of 0＜X＜Lp) (φ A=(q/2 ε) NAX of LP＜X＜Xp) ²(Lp＜X＜Xp) is in numerical expression 39, and A～H is the normal consumption number by the boundary condition decision of numerical expression 38 for-GX+H.The boundary condition formula of separating substitution numerical expression 38 with numerical expression 39 can obtain following numerical expression 40.(numerical expression 40)-(q/ ε) NDXn+A=0-(q/2 ε) NDXn ²+ AXn+B=φ bi+V-(q/ ε) ndLn+C=-(q/ ε) NDLn+A-(q/2 ε) ndLn ²+ CLn+D=-(q/2 ε) NDLn ²+ ALn+BC=ED=F-(q/ ε) naLp+E=-(q/ ε) NALp+G (q/2 ε) naLp ²-ELp+F=(q/2 ε) NALp ²-GLp+H-(q/ ε) NAXp+G=0 (q/2 ε) NAXp ²-GXp+H=0 unties 10 equations of numerical expression 40, obtains 10 parameter Xn, Xp, A～H.Width Ln, the Lp of depletion layer can represent with following numerical expression 41.(numerical expression 41) Xn=[(ND-nd) Ln-(NA-na) Lp]/(NA+ND)+[1/ (NA+ND)] (NA/ND) ^1/2[(NA-na) (ND+na) Lp ²+ (ND-nd) (NA+nd) Ln ²+ 2 (NA-na) (ND-nd) LpLn+ (NA+ND) (2 ε/q) (φ bi+V)] ^1/2Xp=[(NA-na) Lp-(ND-nd) Ln]/(NA+ND)+[1/ (NA+ND)] (NA/ND) ^1/2[(ND-nd) (NA+nd) Ln ²+ (NA-na) (ND+na) Lp ²+ 2 (ND-nd) are LpLn+ (NA+ND) (2 ε/q) (φ bi+V) (NA-na) ^1/2Electric-field intensity distribution becomes Figure 50 B, and maximum field Emax is the electric field that X=0 is ordered, and from the 3rd formula of numerical expression 39, is provided by following numerical expression 42.(numerical expression 42) Emax=C=(q/ ε) { NAXp-(NA-na)/Lp}

Below, illustrate more than the Xp, the Xn that calculate and the concrete numerical value of the substitution result that obtains Emax.

Figure 51 is that the high acceptor concentration of setting p type diffusion layer is NA=5 * 10 ¹⁸/ cm ³, low acceptor concentration is na=1 * 10 ¹⁷/ cm ³, the high donor concentration of n type is ND=1 * 10 ¹⁹/ cm ³, low donor concentration is nd=2 * 10 ¹⁷/ cm ³, and to set applied voltage be V=2.0V, ambient temperature is 85 ℃, when the width in low donor concentration zone is fixed on Lp=0.03 μ m, obtains the result who concerns between stretching, extension Xn, the Xp of low acceptor concentration peak width Lp and depletion layer.

Figure 52 is the result who obtains maximum field Emax by same condition.

From these results, as setting Lp=0.025 μ m, Xp=0.03 μ m then, maximum field intensity is Emax=5.0 * 10 ⁵V/cm.

Figure 53 represents depletion layer expansion one side and each several part size in the unit structure of relevant drain region one side Figure 49 when above-mentioned maximum field intensity.

Above-mentioned maximum field intensity, as analyzing among Figure 43, with the source, leak when not having low concentration layer in the diffusion layer electric field strength relatively, be below 1/3.Therefore, as shown in figure 49,, simultaneously drain region and source region are made the LDD structure, just can suppress maximum field intensity and reduce leakage current, and can give full play to the effect of substrate bias by forming the tagma by high concentration layer and low concentration layer.That is, satisfy the reciprocal condition 1,2 of front, can obtain good DRAM characteristic.

Then, to Figure 57, be illustrated as the concrete manufacture method that realizes memory cell MC structure shown in Figure 49 with reference to Figure 54.The memory cell MC of Figure 49 is in fact as being configured with Fig. 3 and same cell array illustrated in fig. 4.That is, P type silicon layer 12 with the state of the side interface unit isolation insulating film of drawing vertical direction under, form figure as banded device area, and omit its device isolation operation of explanation.

Shown in Figure 54, at first, on the surface of P type silicon layer 12 (for low concentration p type layer 12a), form the mask 31 that device area has opening, and then, form side wall insulating film 32 at the opening sidewalls of this mask 31.Specifically, mask 31 for example makes figure by the silicon oxide deposition film by RIE.And deposition silicon nitride film carries out etching and stays as side wall insulating film 32.Under this state, carry out the boron ion and inject, on P type silicon layer 12, form the p of high concentration ⁺Type layer 12b.

Secondly, shown in Figure 55, after selective etch is removed side wall insulating film 32, form gate insulating film 16 on P type silicon layer 12 surfaces of exposing.Then, the deposit polysilicon film carries out planarization, landfill gate electrode 13.

Then, shown in Figure 56, mask 31 is removed in etching.And, be that mask carries out the arsenic ion injection with gate electrode 13, form source, leakage diffusion layer 14a, the 15a of low concentration.And, shown in Figure 57, on the sidewall of gate electrode 13, form side wall insulating film 33.Then, carry out arsenic ion once more and inject, form source, leakage diffusion layer 14b, the 15b of high concentration.Then, by the silicide operation, as shown in figure 49, on source, leakage diffusion layer 14b, 15b and gate electrode 13, form metal silicide film 18.In addition, make LDD when structure will not leaking diffusion layer 14 and source diffused layer 15, do not need the operation shown in Figure 57.That is, under the state of Figure 56, just obtain the memory cell MC shown in Figure 40.

As described above, be applied to form gate electrode by inlaying (Damascene) method, can with transistorized tagma among under the self aligned state of middle body of orientation, form P ⁺Type layer 12b.

The tagma middle body of cell transistor is made the structure of high concentration layer, be not limited to cell transistor is made the situation of plane structure.Figure 58 A and Figure 58 B represent to adopt columnar semiconductor layers, realize among the 3rd embodiment of 1 transistor/1 unit structure a memory cell MC part and A-A ' profile thereof.

Form column silicon layer 49 on the silicon substrate 40, utilize these column silicon layer 49 lateral circle surfaces to make so-called SGT (Surrounding Gate Trasistor: the ring-shaped gate transistor).N is formed on column silicon layer 49 its bottoms ⁺Type source diffused layer 43 in short transverse, has and is in p type layer 45 and seizes the p of state on both sides by the arms ⁺Type layer 46.Column silicon layer 49 surfaces are gone up and are formed n ⁺Type leaks diffusion layer 44.

Form gate insulating film 41 on column silicon layer 41 lateral circle surfaces, it is surrounded form gate electrode 42.Form gate electrode 42 continuously and become word line WL in a direction.The SGT of Xing Chenging goes up and covers with interlayer dielectric 47 like this, forms bit line (BL) 48 on it.Bit line 48 connects n ⁺ Type diffusion layer 44.

The memory cell of this SGT structure also can be to float in the tagma, the same writing mode of saying according to front embodiment, and by keeping superfluous majority carrier in the tagma, or the action that makes it to emit, carry out dynamic data storage.And, by the high concentration p that the middle body in the tagma is disposed ⁺The impurity concentration or the size of type layer 46 and low concentration p type layer 45 are optimized, and reach enough substrate bias effects of the threshold voltage difference that increases binary data, can reduce leakage current, obtain superior data retention characteristics.

Figure 59 A and Figure 59 B represent the DRAN unit structure of 1 transistor/Unit 1 of another the 4th embodiment.Figure 59 A is represented by dotted lines bit line (BL) 58, the stereogram that the structure under it is distinguished easily, and Figure 59 B represents the profile along bit line direction.

Under the situation of present embodiment, the p type silicon layer 52 (it will become low concentration layer 52a) of being isolated by silicon oxide layer 51 on the silicon substrate 50 forms island on expose and under the state of two sides.And the top and two sides of this silicon layer 52 are situated between with gate insulating film 53 formation gate electrodes 54, formation cell transistor.Gate electrode 54 is made figure continuously and become word line WL along a direction.

On the transistor area of silicon layer 52, form the p of high concentration at the middle body of orientation ⁺Type layer 52b.The LDD structure that source, leakage diffusion layer 55,56 are made of low concentration n type diffusion layer 55a, 56a and high concentration n+ type diffusion layer 55b, 56b.Transistor area is coated with interlayer dielectric 57, the bit line 58 that formation and leakage diffusion layer contact on it.

The memory cell of present embodiment also is to float in the tagma, adopts the same writing mode that illustrates with front embodiment, rely on to keep superfluous majority carrier in the tagma, or the action that makes it to emit, carry out dynamic data storage.And, by to being optimized at the high concentration p+ type layer 52b of the middle body in tagma configuration and impurity concentration or the size of low concentration p type layer 52a, reach enough substrate bias effects of the threshold voltage difference that increases binary data, and can reduce the good data retention characteristics of leakage current acquisition.

The front utilizes Fig. 3 and Fig. 4 simple declaration to have 4F ²The cell array of unit cell area constitute, the following describes the embodiment of cell array structure and manufacture method more specifically.Figure 60 A is the layout of cell array, and Figure 60 is its I-I ' profile, and Figure 60 C is its II-II ' profile.Adopt the dielectric film 102 that forms silicon oxide layer etc. on the substrate silicon 101, the SOI substrate of formation p type silicon layer 103 it on.Silicon layer 103 is imbedded the device isolation dielectric film 109 that produces with the STI method, distinguishes the elongated banded nmosfet formation region of bit line BL direction in the direction of word line WL with certain spacing.

Like this, rectangular on the silicon layer after the device isolation 103 transistor arrangement is got up.Promptly being situated between on silicon layer 103 forms figure with gate insulating film 104, so that connect gate electrode 105 as word line WL.Top and the side of gate electrode 105 is coated with silicon nitride film 106, as the big diaphragm of etching selectivity to the interlayer dielectric 110,115 of later formation.Form the source and leak diffusion layer 107,108 with gate electrode 105 autoregistrations.Make the source, leak the degree of depth that diffusion layer 107,108 forms arrival silicon layer 103 bottom insulating films 102.

Transistor forms face and is covered by the interlayer dielectric 110 of silicon oxide layer etc., and carries out planarization.In this interlayer dielectric 110, open contact hole 111 along the continuous band shape of word line WL direction to source diffused layer 107, imbed the source wiring layer 112 that forms by polysilicon film or WSi etc. here.

On the interlayer dielectric 110 of imbedding source wiring 112, form the interlayer dielectric 115 of silicon oxide layer etc. again and carry out planarization.In this interlayer dielectric 115, open the Lou contact hole 116 of diffusion layer 108, imbed the contact plug 117 of polysilicon film etc. here.And form the bit line (BL) 118 that intersects with word line WL on the interlayer dielectric 115, so that connect contact plug 117 jointly.

The following describes concrete manufacturing process.Figure 61 A, Figure 61 B and Figure 61 C are illustrated in stage plane graph, its I-I ' and the II-II ' profile that forms device isolation dielectric film 109 on the p type silicon layer 103 of SOI substrate.For example, by it being formed the device isolation ditch with RIE method etch silicon layer 103, landfill device isolation dielectric film 109 in this device isolation ditch and obtaining.Therefore, silicon layer 103 can be divided into along the nmosfet formation region of the continuous multi-ribbon shape of bit line direction.

Figure 62 A, Figure 62 B and Figure 62 C arrange on the silicon layer 103 to form transistorized stage plane graph, its I-I ' and II-II ' profile.Promptly being situated between forms figure with gate insulating film 104, so that gate electrode 105 is as word line WL continuously.Top and the side of setting gate electrode 105 is the state that is covered by silicon nitride film 106.This gate electrode diaphragm structure, specifically, by the stack membrane of polysilicon film and silicon nitride film is made figure, so on its sidewall formation silicon nitride film and obtaining.And be that mask carries out ion and injects with gate electrode 105, the formation source, leak diffusion layer 107,108.

Figure 63 A and Figure 64 B are with the substrate behind the interlayer dielectric 110 coverings formation device, imbed the stage plane graph and the I-I ' profile thereof that form source wiring layer 112 in this interlayer dielectric 110.After promptly forming interlayer dielectric 110 planarizations of silicon oxide layer etc., on source diffused layer 107, open and the continuous contact hole 111 of the parallel band shape of word line WL with the RIE method.And, the deposit polysilicon film, carry out etching, give to imbed in the contact hole 111 to form source wiring layer 112.

Figure 64 A and Figure 64 B form interlayer dielectric 115 again on the interlayer dielectric 110 behind the formation source wiring layer 112, imbed stage plane graph and I-I ' profile thereof to the contact plug 117 that leaks diffusion layer 108 in this interlayer dielectric 115.After promptly forming interlayer dielectric 115 planarizations of silicon oxide layer etc., open contact hole 116 leaking on the diffusion layer 108 with the RIE method.And, the deposit polysilicon film, carry out etching, give in the contact hole 116 and imbed and form contact plug 117.Then, shown in Figure 60 B, on interlayer dielectric 115, form bit line 118, so that connect contact plug 117 jointly.

As above, spacing formation word line WL and bit line BL by minimum process rule F shown in Figure 60 A chain-dotted line, obtain having 4, the DRAM cell array of cellar area.When making the device isolation structure shown in Figure 61 A, though source diffused layer 107 is separately to form in word line WL direction, the situation of present embodiment makes its common this source diffused layer 107 that connects by forming source wiring layer 112, obtains low-resistance common source line.

The contact hole 111 of source wiring layer 112 all forms with gate electrode 105 autoregistrations of silicon nitride film 106 protections with the contact hole 116 that is used for bit line contact plug 117.Therefore, in the RIE operation of contact hole processing, the state owing to doing mask open greatlyyer than F is not subjected to the influence of mask fit deviation, can form contact hole.

The situation of the foregoing description shown in Figure 64 A, is only being leaked formation bit line contact hole 116 on the diffusion layer 108.Therefore, shown in Figure 65, also can be same with the contact hole 111 in source region, form the contact hole 116b of bit line in the continuous band shape of word line WL direction.At this moment, the also banded contact plug 117 of imbedding bit line, however it is stayed under the bit line BL.Also can be for example, form after the bit line BL figure, with bit line BL as mask etching contact plug 117.

In the above-described embodiments, if use the top and side that covers source wiring layer 112 with gate electrode 105 same diaphragms, then the fit nargin of bit line contact becomes bigger.The following describes this embodiment.

Device formation operation up to Figure 62 B is all same with the embodiment of front, only utilizes and the corresponding section of Figure 62 B section, and operation after this is described.At first, shown in Figure 66, the interlayer dielectric 201 of deposit silicon oxide-film etc. on the substrate after forming device, and carry out etching and make its planarization., the silicon nitride film 106 of covering grid electrode 105 is carried out etching as the barrier layer here, interlayer dielectric 201 is imbedded in the grid gap.

Then, shown in Figure 67, on interlayer dielectric 201, open contact hole,, imbed contact hole 202,203 respectively by the deposit and the interior etching (etching back) of polysilicon to source and leakage diffusion layer 107,108.When the contact hole window carries out RIE, have mask as utilization at the continuous banded window of bit line BL direction, just form the self aligned contact hole in gap with gate electrode 105.But, the contact plug 202 on the source diffused layer 107, same with the embodiment of front, also can be parallel continuous contact plug with word line WL.

Then, shown in Figure 68, form source wiring layer 204 figure of contact plug 202 on the common connection source diffused layer 107 in word line WL direction.Top and the side of source wiring layer 204 will cover with the silicon nitride film 205 as diaphragm.Specifically, form the lamination figure of polysilicon film and silicon nitride film and form source wiring layer 204, and then form silicon nitride film on its side, just obtain this protection structure.

Secondly, shown in Figure 69, the interlayer dielectric 206 of deposit silicon oxide-film etc. and carry out planarization once more.And with dual damascene (Dual Damascene) method, ditch and contact hole are imbedded in the wiring that forms bit line on interlayer dielectric 206, imbed bit line 207 shown in Figure 70.

According to present embodiment, because with around the silicon nitride film 205 protection source wiring layers 204, so can fully increase the bit line direction width of bit line contact.Therefore, be not subjected to the influence of position fit deviation, can reach low-resistance bit line contact.

In two above-mentioned embodiment, shown in Figure 61 A, distinguish banded continuous device and form the district.Therefore on word-line direction, it is discontinuous that each device forms the district.Shown in Figure 71, banded device forms the district thus, also can distinguish device in the position that forms source diffused layer and form the district, makes it continuous at word-line direction.At this moment, this forms source diffused layer continuously in word-line direction, and keeps himself common source line, but at this moment also as the foregoing description, relies on the low resistanceization of common source line, and it is effective forming source wiring layer 112.

The invention is not restricted to the foregoing description.Though adopt the N-channel MOS transistor that forms on the p type silicon layer among the embodiment, the P channel MOS transistor that forms on n type silicon layer is as memory cell, principle can dynamic memory too.

And, though adopt the SOI substrate in an embodiment, isolate the M0S transistor that makes unsteady semiconductor layer by using with the pn knot, also can constitute the memory cell of same principle.

As previously discussed,, make memory cell, just can provide a kind of holding wire few, semiconductor storage that can the dynamic memory binary data with simple transistor configurations according to each embodiment of the present invention.

Claims (59)

1, a kind of semiconductor storage comprises:

Have the transistor that constitutes memory cell, this transistor is equipped with semiconductor layer, and this semiconductor layer is the 1st conduction type, isolates with other memory cell electricity, and becomes quick condition;

Leak diffusion layer, this leakage diffusion layer is the 2nd conduction type, is formed on the semiconductor layer of above-mentioned the 1st conduction type, and is connected with bit line;

Source diffused layer, this source diffused layer are the 2nd conduction types, isolate being formed on the semiconductor layer of above-mentioned the 1st conduction type with above-mentioned leakage diffusion layer, and are connected with the source line; And

Gate electrode, this gate electrode are on the above-mentioned semiconductor layer between above-mentioned leakage diffusion layer and the above-mentioned source diffused layer, and being situated between forms with gate insulating film, and is connected with word line;

It is characterized in that

Above-mentioned transistor has the 1st data mode that keeps the 1st threshold voltage of superfluous majority carrier in the above-mentioned semiconductor layer and emits the 2nd data mode of the 2nd threshold voltage of the superfluous majority carrier of above-mentioned semiconductor layer.

2, semiconductor storage according to claim 1 is characterized in that

Above-mentioned the 1st data mode is, causes near the ionization by collision drain junction along with making above-mentioned transistor action, and keeps the state of the superfluous majority carrier that generated by this ionization by collision in above-mentioned semiconductor layer,

Above-mentioned the 2nd data mode is that to providing forward bias between above-mentioned semiconductor layer and the above-mentioned leakage diffusion layer, the superfluous majority carrier of extracting out in the above-mentioned semiconductor layer is given the state that leaks diffusion layer.

3, semiconductor storage according to claim 1 is characterized in that

Above-mentioned semiconductor layer is to be situated between with the film formed silicon layer that insulate on the silicon substrate.

4, semiconductor storage according to claim 3 is characterized in that

Above-mentioned silicon layer is a p type layer, and above-mentioned transistor is the N-channel MOS transistor.

5, semiconductor storage according to claim 1 is characterized in that

The current potential of above-mentioned source line is fixed.

6, semiconductor storage according to claim 5 is characterized in that

Data are write fashionable,

With above-mentioned source line is reference potential,

1st current potential higher than said reference current potential is provided for selected transistor word line,

2nd current potential lower than said reference current potential is provided for non-selected transistor word line,

When writing above-mentioned the 1st data mode, provide 3rd current potential higher to bit line than said reference current potential, when writing above-mentioned the 2nd data mode, provide 4th current potential lower than said reference current potential.

7, semiconductor storage according to claim 1, when it is characterized in that data are read,

With above-mentioned source line is reference potential,

Provide for selected transistorized word line and be between above-mentioned the 1st threshold voltage and above-mentioned the 2nd threshold voltage, and, than the 5th high current potential of said reference current potential, detect selected transistorized conduction/non-conduction.

8, semiconductor storage according to claim 7 is characterized in that

Above-mentioned semiconductor layer comprises:

The 1st impurity Adding Area.Above-mentioned in succession leakage diffusion layer in the 1st impurity Adding Area and above-mentioned source diffused layer; And

The 2nd impurity Adding Area, above-mentioned leakage diffusion layer is left in the 2nd impurity Adding Area and above-mentioned source diffused layer is configured, and above-mentioned in succession the 1st impurity Adding Area is configured, and, have than the high impurity concentration in above-mentioned the 1st impurity Adding Area.

9, semiconductor storage according to claim 1 is characterized in that

When data are read,

With above-mentioned source line is reference potential,

Provide than the above-mentioned the 1st and the 2nd threshold voltage height for the transistorized word line of selecting, and, than the 5th high current potential of said reference current potential, detect the transistorized conducting degree of selecting.

10, semiconductor storage according to claim 9 is characterized in that

Above-mentioned semiconductor layer comprises:

The 1st impurity Adding Area, above-mentioned in succession leakage diffusion layer in the 1st impurity Adding Area and above-mentioned source diffused layer; And

The 2nd impurity Adding Area, above-mentioned leakage diffusion layer is left in the 2nd impurity Adding Area and above-mentioned source diffused layer is configured, and above-mentioned in succession the 1st impurity Adding Area is configured, and, have than the high impurity concentration in above-mentioned the 1st impurity Adding Area.

11, semiconductor storage according to claim 1 is characterized in that

Above-mentioned semiconductor layer comprises:

The 1st impurity Adding Area, above-mentioned in succession leakage diffusion layer in the 1st impurity Adding Area and above-mentioned source diffused layer; And

The 2nd impurity Adding Area, above-mentioned leakage diffusion layer is left in the 2nd impurity Adding Area and above-mentioned source diffused layer is configured, and above-mentioned in succession the 1st impurity Adding Area is configured, and, have than the high impurity concentration in above-mentioned the 1st impurity Adding Area.

12, semiconductor storage according to claim 11 is characterized in that

At least leaking diffusion layer among above-mentioned leakage diffusion layer and the above-mentioned source diffused layer has

The 3rd impurity Adding Area, above-mentioned in succession the 1st impurity Adding Area constitute the pn knot; And

The 4th impurity Adding Area is left above-mentioned the 1st impurity Adding Area and is formed, and, have than the high impurity concentration in above-mentioned the 3rd impurity Adding Area.

13, semiconductor storage according to claim 1 is characterized in that

When data were read, after making word line rise to than above-mentioned the 2nd threshold voltage height, certain electric current that flows in bit line detected the potential difference that presents on the bit line.

14, semiconductor storage according to claim 1 is characterized in that

When data are read, after making word line rise to, bitline clamp is arrived certain voltage and the needed electric current that flows, detect its difference between current than above-mentioned the 2nd threshold voltage height.

15, semiconductor storage according to claim 13 is characterized in that

Above-mentioned semiconductor layer comprises:

The 1st impurity Adding Area, above-mentioned in succession leakage diffusion layer in the 1st impurity Adding Area and above-mentioned source diffused layer; And

The 2nd impurity Adding Area, above-mentioned leakage diffusion layer is left in the 2nd impurity Adding Area and above-mentioned source diffused layer is configured, and above-mentioned in succession the 1st impurity Adding Area is configured, and, have than the high impurity concentration in above-mentioned the 1st impurity Adding Area.

16, semiconductor storage according to claim 14 is characterized in that

Above-mentioned semiconductor layer comprises:

The 1st impurity Adding Area, above-mentioned in succession leakage diffusion layer in the 1st impurity Adding Area and above-mentioned source diffused layer; And

The 2nd impurity Adding Area, above-mentioned leakage diffusion layer is left in the 2nd impurity Adding Area and above-mentioned source diffused layer is configured, and above-mentioned in succession the 1st impurity Adding Area is configured, and, have than the high impurity concentration in above-mentioned the 1st impurity Adding Area.

17, semiconductor storage according to claim 1 is characterized in that

A sense amplifier is set on each bar of multiple bit lines, and a bit lines of selecting among this bit line of many connects above-mentioned sense amplifier.

18, a kind of semiconductor storage comprises:

SOI substrate, this SOI substrate are to be situated between to form silicon layer with dielectric film on silicon substrate;

A plurality of transistors form these a plurality of transistors on above-mentioned silicon layer, per 2 transistors of shared leakage diffusion layer carry out device isolation in channel width dimension, and rectangular arrangement;

Many word lines, these many word lines are connected with transistorized gate electrode arranged side by side jointly in the 1st direction;

Multiple bit lines, this bit line is configured in the 2nd direction of intersecting with above-mentioned the 1st direction, and is connected with above-mentioned transistorized leakage diffusion layer; And

The common source line disposes this common source line by disposing transistorized source diffused layer arranged side by side continuously in above-mentioned the 1st direction;

It is characterized in that

Above-mentioned transistor has the 1st data mode that keeps the 1st threshold voltage of superfluous majority carrier in the above-mentioned silicon layer and emits the 2nd data mode of the 2nd threshold voltage of the superfluous majority carrier of above-mentioned silicon layer.

19, semiconductor storage according to claim 18 is characterized in that

When regulation minimum process size rule was F, a transistor carried out arranged by the cell size of 2F * 2F.

20, semiconductor storage according to claim 18 is characterized in that

Above-mentioned leakage diffusion layer and above-mentioned source diffused layer are formed with the degree of depth that arrives the above-mentioned dielectric film that is positioned at above-mentioned silicon layer below.

21, semiconductor storage according to claim 18 is characterized in that

Above-mentioned the 1st data mode is, causes near the ionization by collision drain junction along with making above-mentioned transistor action, and keeps the state of the superfluous majority carrier that generated by this ionization by collision in above-mentioned silicon layer,

Above-mentioned the 2nd data mode is that to providing forward bias between above-mentioned silicon layer and the above-mentioned leakage diffusion layer, the superfluous majority carrier of extracting out in the above-mentioned silicon layer is given the state that leaks diffusion layer.

22, semiconductor storage according to claim 21 is characterized in that

Above-mentioned silicon layer is the p type, and above-mentioned transistor is the N-channel MOS transistor.

23, semiconductor storage according to claim 18 is characterized in that

The current potential of above-mentioned common source line is fixed.

24, semiconductor storage according to claim 23 is characterized in that

Data are write fashionable,

With above-mentioned common source line is reference potential,

1st current potential higher than said reference current potential is provided for selected transistor word line,

2nd current potential lower than said reference current potential is provided for non-selected transistor word line,

When writing above-mentioned the 1st data mode, provide 3rd current potential higher to bit line than said reference current potential, when writing above-mentioned the 2nd data mode, provide 4th current potential lower than said reference current potential.

25, semiconductor storage according to claim 18 is characterized in that

When data are read,

With above-mentioned common source line is reference potential,

Provide for selected transistorized word line and be between above-mentioned the 1st threshold voltage and above-mentioned the 2nd threshold voltage, and, than the 5th high current potential of said reference current potential, detect selected transistorized conduction/non-conduction.

26, semiconductor storage according to claim 18 is characterized in that

When data are read,

With above-mentioned common source line is reference potential,

Provide than the above-mentioned the 1st and the 2nd threshold voltage height for the transistorized word line of selecting, and, than the 5th high current potential of said reference current potential, detect the transistor turns degree of selecting.

27, semiconductor storage according to claim 25 is characterized in that

Above-mentioned silicon layer comprises:

The 1st impurity Adding Area, above-mentioned in succession leakage diffusion layer in the 1st impurity Adding Area and above-mentioned source diffused layer; And

The 2nd impurity Adding Area, above-mentioned leakage diffusion layer is left in the 2nd impurity Adding Area and above-mentioned source diffused layer is configured, and above-mentioned in succession the 1st impurity Adding Area is configured, and, have than the high impurity concentration in above-mentioned the 1st impurity Adding Area.

28, semiconductor storage according to claim 26 is characterized in that

Above-mentioned silicon layer comprises:

The 1st impurity Adding Area.Above-mentioned in succession leakage diffusion layer in the 1st impurity Adding Area and above-mentioned source diffused layer; And

The 2nd impurity Adding Area.Above-mentioned leakage diffusion layer is left in the 2nd impurity Adding Area and above-mentioned source diffused layer is configured, and above-mentioned in succession the 1st impurity Adding Area is configured, and, have than the high impurity concentration in above-mentioned the 1st impurity Adding Area.

29, semiconductor storage according to claim 18 is characterized in that

When data were read, after the transistorized word line that makes selection rose to than above-mentioned the 2nd threshold voltage height, certain electric current that flows in bit line detected the potential difference that presents on the transistorized bit line of selecting.

30, semiconductor storage according to claim 18 is characterized in that

When data are read, after making selected transistor word line rise to,, detect its difference between currents with the selected transistorized bitline clamp needed electric current that flows in certain voltage than above-mentioned the 2nd threshold voltage height.

31, semiconductor storage according to claim 29 is characterized in that

Above-mentioned silicon layer comprises:

The 1st impurity Adding Area, above-mentioned in succession leakage diffusion layer in the 1st impurity Adding Area and above-mentioned source diffused layer; And

The 2nd impurity Adding Area, above-mentioned leakage diffusion layer is left in the 2nd impurity Adding Area and above-mentioned source diffused layer is configured, and above-mentioned in succession the 1st impurity Adding Area is configured, and, have than the high impurity concentration in above-mentioned the 1st impurity Adding Area.

32, semiconductor storage according to claim 30 is characterized in that

Above-mentioned silicon layer comprises:

The 1st impurity Adding Area, above-mentioned in succession leakage diffusion layer in the 1st impurity Adding Area and above-mentioned source diffused layer; And

The 2nd impurity Adding Area, above-mentioned leakage diffusion layer is left in the 2nd impurity Adding Area and above-mentioned source diffused layer is configured, and above-mentioned in succession the 1st impurity Adding Area is configured, and, have than the high impurity concentration in above-mentioned the 1st impurity Adding Area.

33, semiconductor storage according to claim 24 is characterized in that

When data were read, after the transistorized word line that makes selection rose to than above-mentioned the 2nd threshold voltage height, certain electric current that flows in the transistorized bit line of selecting detected the potential difference that presents on the bit line.

34, semiconductor storage according to claim 24 is characterized in that

When data are read, after making selected transistor word line rise to,, detect its difference between currents with the selected transistorized bitline clamp needed electric current that flows in certain voltage than above-mentioned the 2nd threshold voltage height.

35, semiconductor storage according to claim 33 is characterized in that

Above-mentioned silicon layer comprises:

The 1st impurity Adding Area, above-mentioned in succession leakage diffusion layer in the 1st impurity Adding Area and above-mentioned source diffused layer; And

The 2nd impurity Adding Area, above-mentioned leakage diffusion layer is left in the 2nd impurity Adding Area and above-mentioned source diffused layer is configured, and above-mentioned in succession the 1st impurity Adding Area is configured, and, have than the high impurity concentration in above-mentioned the 1st impurity Adding Area.

36, semiconductor storage according to claim 34 is characterized in that

Above-mentioned silicon layer comprises:

The 1st impurity Adding Area, above-mentioned in succession leakage diffusion layer in the 1st impurity Adding Area and above-mentioned source diffused layer; And

The 2nd impurity Adding Area.Above-mentioned leakage diffusion layer is left in the 2nd impurity Adding Area and above-mentioned source diffused layer is configured, and above-mentioned in succession the 1st impurity Adding Area is configured, and, have than the high impurity concentration in above-mentioned the 1st impurity Adding Area.

37, semiconductor storage according to claim 18 is characterized in that

A sense amplifier is set on each bar of multiple bit lines, and 1 bit line selecting among this multiple bit lines is connected with above-mentioned sense amplifier.

38, a kind of semiconductor storage comprises:

Be situated between on the silicon substrate and form the SOI substrate of silicon layer with dielectric film;

Form the gate electrode of figure and the source that forms with this self-aligned with grid electrode under the state that a plurality of transistors that rectangular arrangement forms on above-mentioned silicon layer, above having and side cover with diaphragm as a continuous word line of direction and leak diffusion layer;

Cover above-mentioned a plurality of transistorized the 1st interlayer dielectric;

Form the source wiring layer of imbedding in the 1st continuous band-shaped contact hole that walks abreast with above-mentioned word line on above-mentioned the 1st interlayer dielectric on above-mentioned each transistorized source diffused layer;

The 2nd interlayer dielectric that forms on above-mentioned the 1st interlayer dielectric:

The bit line contact plug of in the 2nd contact hole that above-mentioned the 2nd interlayer dielectric is opened, imbedding on above-mentioned each transistorized leakage diffusion layer;

On above-mentioned the 2nd interlayer dielectric with above-mentioned word line cross-over configuration, the bit line that the above rheme line contact plug that is situated between is connected with above-mentioned transistorized leakage diffusion layer,

It is characterized in that

Above-mentioned transistor dynamic memory has the 1st data mode that keeps the 1st threshold voltage of superfluous majority carrier in the tagma and emits 2nd data mode of the superfluous majority carrier in above-mentioned tagma to the 2nd threshold voltage that leaks diffusion layer.

39, according to the described semiconductor storage of claim 38, it is characterized in that

The silicon layer of above-mentioned SOI substrate by means of the device isolation dielectric film, will carry out subregion at above-mentioned word-line direction with the interval of regulation at the continuous banded nmosfet formation region of above-mentioned bit line direction.

40, according to the described semiconductor storage of claim 38, it is characterized in that

Above-mentioned the 1st state is, causes near the ionization by collision drain junction along with making above-mentioned transistor action, and keeps the state of the superfluous majority carrier that generated by this ionization by collision in above-mentioned silicon layer,

Above-mentioned the 2nd state is that to providing forward bias between above-mentioned silicon layer and the above-mentioned leakage diffusion layer, the superfluous majority carrier of extracting out in the above-mentioned silicon layer is given the state that leaks diffusion layer.

41, according to the described semiconductor storage of claim 38, it is characterized in that

Above-mentioned silicon layer is the p type, and above-mentioned transistor is the N-channel MOS transistor.

42, according to the described semiconductor storage of claim 38, it is characterized in that

The current potential of above-mentioned source wiring layer is fixed.

43, according to the described semiconductor storage of claim 38, it is characterized in that

When data are read,

With above-mentioned source wiring layer is reference potential,

Provide for selected transistorized word line and be between above-mentioned the 1st threshold voltage and above-mentioned the 2nd threshold voltage, and, than the high current potential of said reference current potential, detect selected transistorized conduction/non-conduction.

44, according to the described semiconductor storage of claim 38, it is characterized in that

When data are read,

With above-mentioned source wiring layer is reference potential,

Provide than the above-mentioned the 1st and the 2nd threshold voltage height for the transistorized word line of selecting, and, than the high current potential of said reference current potential, detect the transistor turns degree of selecting.

45, according to the described semiconductor storage of claim 38, it is characterized in that

When data were read, after making word line rise to than above-mentioned the 2nd threshold voltage height, certain electric current that flows in bit line detected the potential difference that presents on the bit line.

46, according to the described semiconductor storage of claim 38, it is characterized in that

When data are read, after making word line rise to,, detect its difference between currents with the bitline clamp needed electric current that flows in certain voltage than above-mentioned the 2nd threshold voltage height.

47, according to the described semiconductor storage of claim 38, it is characterized in that

A sense amplifier is set on each bar of multiple bit lines, and a bit lines of selecting among this bit line of many connects above-mentioned sense amplifier.

48, a kind of semiconductor storage comprises:

Be situated between on the silicon substrate and form the SOI substrate of silicon layer with dielectric film;

Form the gate electrode of figure and source and the leakage diffusion layer that forms with this self-aligned with grid electrode under the state that a plurality of transistors that rectangular arrangement forms on above-mentioned silicon layer, above having and side cover with the 1st diaphragm as a continuous word line of direction;

Cover above-mentioned a plurality of transistorized the 1st interlayer dielectric;

On above-mentioned each transistorized source diffused layer of above-mentioned interlayer dielectric, imbed the source contact plug in the formed contact hole;

On above-mentioned each transistorized leakage diffusion layer of above-mentioned interlayer dielectric, imbed the drain contact plug in the formed contact hole;

Be connected the direction above-mentioned source contact plug arranged side by side of above-mentioned word line jointly, cover the source wiring layer of top and side simultaneously with the 2nd diaphragm;

Cover the 2nd interlayer dielectric of this source wiring layer;

On above-mentioned the 2nd interlayer dielectric with above-mentioned word line cross-over configuration, the bit line that is situated between and is connected with above-mentioned transistorized leakage diffusion layer with above-mentioned drain contact plug,

It is characterized in that

Above-mentioned transistor dynamic memory has the 1st data mode that keeps the 1st threshold voltage of superfluous majority carrier in the tagma and has the 2nd data mode that the superfluous majority carrier of emitting above-mentioned tagma arrives the 2nd threshold voltage that leaks diffusion layer.

49, according to the described semiconductor storage of claim 48, it is characterized in that

The silicon layer of above-mentioned SOI substrate by means of the device isolation dielectric film, will carry out subregion at above-mentioned word-line direction with the interval of regulation at the continuous banded nmosfet formation region of above-mentioned bit line direction.

50, according to the described semiconductor storage of claim 48, it is characterized in that

Above-mentioned the 1st data mode is, causes near the ionization by collision drain junction along with making above-mentioned transistor action, and keeps the state of the superfluous majority carrier that generated by this ionization by collision in above-mentioned silicon layer,

Above-mentioned the 2nd data mode is that to providing forward bias between above-mentioned silicon layer and the above-mentioned leakage diffusion layer, the superfluous majority carrier of extracting out in the above-mentioned silicon layer is given the state that leaks diffusion layer.

51, according to the described semiconductor storage of claim 48, it is characterized in that

Above-mentioned silicon layer is the p type, and above-mentioned transistor is the N-channel MOS transistor.

52, according to the described semiconductor storage of claim 48, it is characterized in that

The current potential of above-mentioned source wiring layer is fixed.

53, according to the described semiconductor storage of claim 48, it is characterized in that

When data are read,

With above-mentioned source wiring layer is reference potential,

Provide for selected transistorized word line and be between above-mentioned the 1st threshold voltage and above-mentioned the 2nd threshold voltage, and, than the high current potential of said reference current potential, detect selected transistorized conduction/non-conduction.

54, according to the described semiconductor storage of claim 48, it is characterized in that

When data are read,

With above-mentioned source wiring layer is reference potential,

Provide than the above-mentioned the 1st and the 2nd threshold voltage height for the transistorized word line of selecting, and, than the high current potential of said reference current potential, detect the transistorized conducting degree of selecting.

55, according to the described semiconductor storage of claim 48, it is characterized in that

When data were read, after making word line rise to than above-mentioned the 2nd threshold voltage height, certain electric current that flows in bit line detected the potential difference that presents on the bit line.

56, according to the described semiconductor storage of claim 48, it is characterized in that

When data are read, after making word line rise to,, detect its difference between currents with the bitline clamp needed electric current that flows in certain voltage than above-mentioned the 2nd threshold voltage height.

57, according to the described semiconductor storage of claim 48, it is characterized in that

A sense amplifier is set on each bar of multiple bit lines, and a bit lines of selecting among this bit line of many connects above-mentioned sense amplifier.

58, a kind of manufacture method of semiconductor storage comprises:

On Semiconductor substrate, form dielectric film;

On above-mentioned dielectric film, form the semiconductor layer of the 1st conduction type;

On above-mentioned semiconductor layer, form grid and form the mask that has window on the zone;

On the window sidewall of aforementioned mask, form side wall insulating film;

By the above-mentioned window of aforementioned mask, add impurity to above-mentioned semiconductor layer, form the 1st conductive type impurity interpolation layer that has than the impurity concentration of above-mentioned semiconductor floor height;

Remove after the above-mentioned side wall insulating film, give in the above-mentioned window of aforementioned mask and imbed and form gate insulating film and gate electrode; And

Remove after the aforementioned mask, add impurity, form the leakage diffusion layer and the source diffused layer of the 2nd conduction type to above-mentioned semiconductor layer.

59, a kind of manufacture method of semiconductor storage comprises:

On Semiconductor substrate, form dielectric film;

On above-mentioned dielectric film, form the semiconductor layer of the 1st conduction type;

On above-mentioned semiconductor layer, form grid and form the mask that has window on the zone;

On the window sidewall of aforementioned mask, form the 1st side wall insulating film;

By the above-mentioned window of aforementioned mask, add impurity to above-mentioned semiconductor layer, the 1st impurity that formation has than the 1st conduction type of the impurity concentration of above-mentioned semiconductor floor height adds layer;

Remove after above-mentioned the 1st side wall insulating film, give in the above-mentioned window of aforementioned mask and imbed and form gate insulating film and gate electrode;

Remove after the aforementioned mask, add impurity to above-mentioned semiconductor layer, the 2nd impurity that forms the 2nd conduction type in drain region and source region adds layer;

On the sidewall of above-mentioned gate electrode, form the 2nd side wall insulating film;

Add impurity to above-mentioned semiconductor layer, in above-mentioned drain region and source region, the 3rd impurity that formation has than the 2nd conduction type of the impurity concentration of above-mentioned the 2nd impurity interpolation floor height adds layer.

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