511165 7 8 3 9twf1. doc/0 0 6 A7 B7 五、發明說明（(） 本發明係有關於一種雙載子連接電晶體（Bipolar Junction Transistor，BJT)的製造方法，且特別是有關於一 種自行對準（self-aHgned)雙載子電晶體的製造方法。 雙載子電晶體是一種同時利用電子和電洞（hole)這兩 種載子（earners)來傳導電流的電子元件。雙載子電晶體的 結構是由兩組緊密的pn連接所組成的三接點（three terminal)元件。這三個接點分別爲射極(emitter)、基極(base) 與集極（collector)。然而，一般的雙載子電晶體，其射極 與基極係以相同的材質接合，在電流增益（current gain)以 及射極效率（emitter efficiently)的提升上具有其極限，爲了 改善上述的問題，因此採用了一種異質接合雙載子電晶 體。 經濟部智慧財產局員工消費合作社印製 異質接合雙載子電晶體係指異質接合所形成的雙載子 電晶體，此處所謂的異質接合係指射極與基極使用不同的 材質相接合而形成。而異質接合雙載子電晶體在開關 (switch)的應用上具有高電流增益以及具有極筒的切斷頻 率（cut-off frequency)等優點，並且在微波放大（microwave amplifier)的應用上具有局電能增：63： (high power gain)以及 高電能密度(high Power density)等優點。 第1A圖至第1E圖所繪示爲習知一種異質接合雙載子 電晶體的製造方法。 首先，請參照第1A圖，在具有集極端之基底1〇〇上 沈積一層非選擇性（n〇n-sflective)的矽化鍺（SiGe)磊晶層 102，再於矽化鍺磊晶層1〇2上沈積一層絕緣層104。 3 本紙張尺度適用中國國家標準（CNS)A4規格（210 x 297公釐） 511165 7839twfl·doc/006 A7 B7 五、發明說明（之） 接著，請參照第1B圖，以微影蝕刻的方法去除部份 的絕緣層104以形成絕緣層l〇4a，再於基底100上依序沈 積多晶砂導體層106以及絕緣層108。接著，以微影蝕刻 的方法去除部份的絕緣層10 8以及多晶政導體層10 6，形 成露出絕緣層l〇4a的開口 110。 接著，請參照第1C圖，在基底100上沈積一層共形 的絕緣層112,然後，在開口 110的兩側壁形成間隙壁114。 接著，請參照第1D圖，以間隙壁114爲罩幕，蝕刻 去除開口 110中的絕緣層112以露出矽化鍺磊晶層102。 然後，在基底1〇〇上沈積一層多晶矽導體層116。 接著，請參照第1E圖，以微影蝕刻的方法定義多晶 矽導體層116、絕緣層112以及絕緣層108，以形成異質 接合雙載子電晶體的射極116a以及基極106a。 然而，依上述方法所形成的異質接合雙載子電晶體有 下述的缺點： 經濟部智慧財產局員工消費合作社印製 在上述的製程中，由於射極與基極必須經由數道微影 蝕刻的步驟形成，因此製程的裕度（windows)並不寬裕， 使得在第1E圖的磊晶層1〇4中，射極與基極的間距120 的大小並不容易控制。此間距120過小的話，則會由於射 極與基極的摻雜濃度很大而產生接面漏電流（junction leakage)的現象，此間距120過大的話，則會產生釋生電 阻(parasite resistance)而降低元件的高頻特性的效能。 而且，如同一般所了解的，在微影製程中包含了一些 前置以及後續的處理步驟而製程較爲繁複。然而在上述的 4 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公爱） 511165 B39twfl.doc/006 A7 B7 五、發明說明（>) 製程中，完成至如同第1E圖所示的結構至少需要三道微 影蝕刻的製程，因此使得上述的製程變得相當的繁複’並 且製造所耗費的時間以及成本較高。 因此，本發明的目的在提供一種自行對準雙載子電晶 體的製造方法與結構，能夠使用自行對準的方法形成射極 與基極，而具有較寬裕的製程裕度。 本發明的另一目的在提供一種自行對準雙載子電晶體 的製造方法與結構，能夠減少微影製程的數目，以簡化製 程且降低製造的時間以及成本。 經濟部智慧財產局員工消費合作社印製 爲了達成上述的目的，本發明提出一種自行對準雙載 子電晶體的製造方法，此方法係首先提供一具有集極端之 基底，且在基底上形成磊晶層以作爲基極。接著，在磊晶 層上依序形成第一介電層、第二介電層，再於第二介電層 中形成開口。然後，在開口側壁形成導體間隙壁，再以第 二介電層以及導體間隙壁爲罩幕，去除開口中之第一介電 層。其後，在開口中形成導體層以作爲射極，再完全去除 第二介電層。此後對射極進行第一摻雜製程，並以射極與 導體間隙壁爲罩幕，去除邰份第一介電層，再以射極與導 體間隙壁爲罩幕，對磊晶層進行第二摻雜製程，以使部份 磊晶層成爲基極接觸區。 本發明提出一種自行對準雙載子電晶體的結構，此結 構至少包括具有集極端之基底、基極、基極接觸區、射極 以及導體間隙壁。其中基極係設置基底上，基極接觸區係 設置於基極兩側之基底上，且射極係設置於基極上，而導 5 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公 511165 7839twf1.doc/006 A7 B7 五、發明說明（q) 體間隙壁係設置於射極上部的側壁位置。 經濟部智慧財產局員工消費合作社印製 本發明提供另一種自行對準雙載子電晶體的製造方 法，此方法係提供一具有集極端之基底，且在基底上已形 成晶晶層以作爲基極，再於晶晶層上依序形成第一介電 層、第二介電層、第三介電層以及第四介電層。接著，在 第四介電層中形成開口，並於開口側壁形成導體間隙壁， 再以第四介電層與導體間隙壁爲罩幕，去除開口中之第三 介電層、第二介電層以及第一介電層。然後，在第三介電 層以及開口中形成共形的第一導體層，並對第一導體層進 行第一摻雜製程，再於第一導體層上形成第二導體層，接 著去除開口之外的第一導體層以及第二導體層，以在開口 中形成第三導體層以作爲射極。其後，完全去除第四介電 層，並對射極進行第二摻雜製程，再以射極與導體間隙壁 爲罩幕，去除部份第三介電層。之後，以射極與導體間隙 壁爲罩幕，對磊晶層進行第三摻雜製程，以使部份磊晶層 成爲基極接觸區，再於射極以及殘留之第三介電層側壁形 成間隙壁。最後，以射極、導體間隙壁以及間隙壁爲罩幕， 去除部份第二介電層以及部份第一介電層，以露出氧化間 隙壁兩側之基極接觸區，再於射極、導體間隙壁以及基極 接觸區上形成金屬矽化物層。 本發明提出另一種自行對準雙載子電晶體的結構，此 結構至少包括具有集極端之基底、基極、基極接觸區、射 極、導體間隙壁、第一介電層、第二介電層以及第三介電 層。其中基極係設置基底上，基極接觸區係設置於基極兩 6 本紙張尺度適用中國國家標準（CNS)A4規格（21〇 X 297公釐） 經濟部智慧財產局員工消費合作社印製 511165 7839twf1.d〇c/〇〇6 A7 B7 五、發明說明（<) 側之基底上’射極係設置於基極上，導體間隙壁係設置於 射極上部的側壁位置。第一介電層係設置射極兩側之基極 上，並且第一介電層延伸至部份之基極接觸區上’第二介 電層係設置第一介電層上以及第三介電層係設置導體間隙 壁與介電層之間的射極側壁，並且第三介電層的端部分別 與基極的兩端部略爲對齊。 由上述製造方法可知，本發明的特徵係在於以自行對 準的方式形成雙載子電晶體的射極以及基極接觸區’因此 具有較寬裕的製程裕度，並且對於射極以及基極接觸區在 磊晶層間距的大小，亦能夠藉由自行對準製程而得到良好 的控制。 而且，本發明在形成射極以及基極的製程中，僅有在 形成開口的製程必須使用微影蝕刻製程，與習知的方法相 比，本發明至少能夠減少一道至二道的微影製程，因此能 夠降低在微影製程所耗費的時間與成本支出，有效的簡化 製程。 此外’本發明之雙載子電晶體亦可搭配習知之互補式 金氧半導體 (Complementary Metal Oxide Semiconductor, CMOS)元件’而形成雙載子電晶體-互補式金氧半導體 (bipolar CMOS, BiCMOS)元件。 爲讓本發明之上述目的、特徵、和優點能更明顯易懂， 下文特舉一較佳實施例，並配合所附圖式，作詳細說明如 下。 7 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -----------裝---- (請先閱讀背面之注音心事項再填寫本頁) 訂.. 511165 7839twfl.doc/006 A7 _B7 _ 五、發明說明（έ ) 圖式之簡單說明： 第1A圖至第1E圖所繪示爲習知一種異質接合雙載子 電晶體的製造流程的剖面示意圖； 第2A圖至第2G圖所繪示爲本發明之一種自行對準 雙載子電晶體的製造流程的剖面示意圖；以及 第3A圖至第31圖所繪示爲本發明之一種自行對準雙 載子電晶體的製造流程的剖面示意圖。 圖式之標示說明： 100、200、300 ··基底 102、202、302 :磊晶層 104、104a、108、112 :絕緣層 106、116、212、218、316、316a、318、318a ··導體 層 經濟部智慧財產局員工消費合作社印制衣 106a、222 :基極 110、208、312 ·•開口 114 :間隙壁 118、212a、319 ··射極 120 ··間距 204、206、304、306、308、310 ··介電層 210、314 ··導體間隙壁 214、216、320、321 :摻雜製程 218、322 :基極接觸區 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 511165 A7 B7 7; 經濟部智慧財產局員工消費合作社印製 7839twf1.doc/006 發明說明（q) 324 :間隙壁 326 :金屬矽化物 第一實施例 第2A圖至第2G圖所繪示爲本發明之一種自行對準 雙載子電晶體的製造流程的剖面示意圖。 首先，請參照第2A圖，提供一個具有集極端之基底 200，其中基底200的材質例如是選自矽化鍺、砂、矽化 鎵、磷化銦所組成之族群，且在基底200上形成有一層磊 晶層202。接著’在晶晶層202上依序形成介電層204、 介電層206。其中此磊晶層202係作爲雙載子電晶體的基 極’其材質例如是選自矽化鍺、矽、砷化鎵、磷化絪、鋁 砷化鎵合金(AlxGa^xAs，1)、銦砷化鎵合金(ij^GahAs, X ‘1)所組成之族群，形成的方法例如是使用化學氣相沈積 法’分子束幕晶成長等。介電層204的材質例如是氧化石夕， 其形成的方法例如是化學氣相沈積法，介電層2〇6的材質 爲習用之介電層材質例如是氮化矽、氧化矽、氮氧化矽或 碳化矽等，形成方法例如是化學氣相沈積法。 接著，請參照第2B圖，在介電層206中形成開口 208 ’ 且在開口 208的底部露出介電層204。其中形成開口 208 的方法例如是在介電層206上形成圖案化的罩幕層（未圖 示），並以罩幕層爲罩幕，蝕刻去除罩幕層未覆蓋之介電 層206至露出介電層204表面，再去除罩幕層。然後，在 開口 208的兩側壁形成導體間隙壁210。其中導體間隙壁 本紙張尺度適用中國國豕標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁)511165 7 8 3 9twf1. Doc / 0 0 6 A7 B7 V. Description of the invention (() The present invention relates to a method for manufacturing a bipolar junction transistor (BJT), and in particular to a self-propelled transistor. A method for manufacturing a self-aHgned bipolar transistor. A bipolar transistor is an electronic component that uses two types of carriers, electrons and holes, to conduct electrical current. Bicarriers The structure of the transistor is a three terminal element composed of two sets of tight pn connections. These three contacts are the emitter, base and collector. However, In general bipolar transistors, the emitter and base are joined with the same material, which has its limits on the improvement of current gain and emitter efficiency. In order to improve the above problems, Therefore, a heterojunction bipolar transistor is used. Heterojunction bipolar transistor system printed by the consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs refers to the heterojunction bimorph transistor formed here, so-called heterogeneity Bonding means that the emitter and the base are formed by joining different materials. The heterojunction bipolar transistor has a high current gain and a cut-off frequency of the pole tube in the application of a switch. ) And other advantages, and in the application of microwave amplifier (microwave amplifier) with local power increase: 63: (high power gain) and high power density (high power density) and other advantages. Figures 1A to 1E are shown as A method for manufacturing a heterojunction bipolar transistor is known. First, referring to FIG. 1A, a layer of non-sflective germanium silicide (SiGe) is deposited on a substrate 100 having a collector terminal. The epitaxial layer 102, and then an insulating layer 104 is deposited on the germanium silicide epitaxial layer 102. 3 This paper size applies to the Chinese National Standard (CNS) A4 specification (210 x 297 mm) 511165 7839twfl · doc / 006 A7 B7 V. Description of the Invention (Part 1) Next, referring to FIG. 1B, a part of the insulating layer 104 is removed by lithographic etching to form an insulating layer 104a, and a polycrystalline sand conductor layer 106 is sequentially deposited on the substrate 100. As well as the insulating layer 108. Then A part of the insulating layer 108 and the polycrystalline conductive layer 106 are removed by lithographic etching to form an opening 110 exposing the insulating layer 104a. Next, referring to FIG. 1C, a layer of conformal is deposited on the substrate 100 Then, an insulating layer 112 is formed on the two sidewalls of the opening 110. Next, referring to FIG. 1D, using the spacer 114 as a mask, the insulating layer 112 in the opening 110 is etched and removed to expose the germanium silicide epitaxial layer 102. Then, a polycrystalline silicon conductor layer 116 is deposited on the substrate 100. Next, referring to FIG. 1E, a polysilicon conductor layer 116, an insulating layer 112, and an insulating layer 108 are defined by a lithographic etching method to form an emitter 116a and a base 106a of a heterojunction bipolar transistor. However, the heterojunction bipolar transistor formed according to the above method has the following disadvantages: printed by the consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs in the above process, because the emitter and base must be etched through several lithography The steps are formed, so the margin of the manufacturing process (windows) is not marginal, so that in the epitaxial layer 104 of FIG. 1E, the distance between the emitter and the base 120 is not easy to control. If the distance 120 is too small, junction leakage will occur due to the large doping concentration of the emitter and base. If the distance 120 is too large, parasite resistance will be generated. Reduce the effectiveness of the high frequency characteristics of the device. Moreover, as is generally understood, the lithography process includes some pre-processing and subsequent processing steps, and the process is more complicated. However, in the above 4 paper sizes, the Chinese National Standard (CNS) A4 specification (210 X 297 public love) is applied 511165 B39twfl.doc / 006 A7 B7 V. Description of the invention (>) The process is completed as shown in Figure 1E The structure shown requires at least three lithography processes, so that the above processes become quite complicated 'and the time and cost of manufacturing are high. Therefore, an object of the present invention is to provide a method and a structure for manufacturing a self-aligned bipolar transistor, which can form an emitter and a base using a self-aligned method, and has a relatively wide process margin. Another object of the present invention is to provide a method and structure for manufacturing a self-aligned bipolar transistor, which can reduce the number of lithography processes, simplify the process, and reduce the manufacturing time and cost. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs In order to achieve the above-mentioned object, the present invention proposes a method for manufacturing self-aligned bipolar transistor. The crystal layer is used as a base. Then, a first dielectric layer and a second dielectric layer are sequentially formed on the epitaxial layer, and openings are formed in the second dielectric layer. Then, a conductor gap wall is formed on the side wall of the opening, and the second dielectric layer and the conductor gap wall are used as a mask to remove the first dielectric layer in the opening. Thereafter, a conductor layer is formed in the opening as an emitter, and the second dielectric layer is completely removed. Thereafter, a first doping process is performed on the emitter, and the gap between the emitter and the conductor is used as a screen to remove the first dielectric layer. Then, the gap between the emitter and the conductor is used as a screen to perform the first epitaxial layer. A two-doping process, so that part of the epitaxial layer becomes a base contact region. The invention proposes a structure for self-aligning a bipolar transistor. The structure includes at least a base having a collector terminal, a base, a base contact region, an emitter, and a conductor gap. The base is set on the base, the base contact area is set on the base on both sides of the base, and the emitter is set on the base. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 male 511165 7839twf1.doc / 006 A7 B7 V. Description of the invention (q) The body gap wall is located on the side wall of the upper part of the emitter. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs This invention provides another self-aligned dual load A method for manufacturing a sub-electron crystal. This method is to provide a substrate with a collector and a crystal layer has been formed on the substrate as a base, and then a first dielectric layer and a second dielectric layer are sequentially formed on the crystal layer. An electrical layer, a third dielectric layer, and a fourth dielectric layer. Next, an opening is formed in the fourth dielectric layer, and a conductor gap wall is formed on the side wall of the opening, and the fourth dielectric layer and the conductor gap wall are used as a cover. , Removing the third dielectric layer, the second dielectric layer, and the first dielectric layer in the opening. Then, a conformal first conductor layer is formed in the third dielectric layer and the opening, and the first conductor layer is processed. First doping process, then on the first conductor A second conductor layer is formed thereon, and then the first conductor layer and the second conductor layer outside the opening are removed to form a third conductor layer in the opening as an emitter. Thereafter, the fourth dielectric layer is completely removed, and The emitter is subjected to a second doping process, and the third dielectric layer is removed by using the emitter-conductor spacer as a mask. After that, the emitter and conductor spacer is used as a mask to perform a third epitaxial layer. Doping process, so that part of the epitaxial layer becomes the base contact area, and then a gap wall is formed on the emitter and the remaining third dielectric layer side wall. Finally, the emitter, the conductor gap and the gap are used as a screen. A portion of the second dielectric layer and a portion of the first dielectric layer are removed to expose the base contact areas on both sides of the oxidation spacer, and a metal silicide layer is formed on the emitter, the conductor spacer, and the base contact area. The present invention proposes another structure of self-aligned bipolar transistor. This structure includes at least a substrate with a collector terminal, a base, a base contact area, an emitter, a conductor gap, a first dielectric layer, and a second dielectric. Electrical layer and third dielectric layer, wherein the base electrode It is set on the base, and the base contact area is set on the two bases. 6 This paper size is applicable to the Chinese National Standard (CNS) A4 (21 × 297 mm). Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs and Consumer Cooperatives. 〇c / 〇〇6 A7 B7 V. The substrate on the side of the description of the invention ('emitter' is set on the base and the conductor gap is placed on the upper side of the emitter. The first dielectric layer is set on the base. On the bases on both sides of the electrode, and the first dielectric layer extends to a part of the base contact area, the second dielectric layer is provided on the first dielectric layer and the third dielectric layer is provided on the conductive spacer and the dielectric. The emitter sidewalls between the electrical layers, and the ends of the third dielectric layer are slightly aligned with the two ends of the base, respectively. As can be seen from the above manufacturing method, the present invention is characterized by forming a double layer in a self-aligning manner. The emitter and base contact areas of the carrier transistor have a wider process margin, and the gap between the emitter and base contact areas in the epitaxial layer can also be obtained by self-aligning the process. control. Moreover, in the process of forming the emitter and the base of the present invention, only the process of forming the opening must use the lithographic etching process. Compared with the conventional method, the present invention can reduce at least one to two lithographic processes. Therefore, it can reduce the time and cost spent in the lithography process and effectively simplify the process. In addition, 'the bipolar transistor of the present invention can also be matched with a conventional complementary metal oxide semiconductor (CMOS) element' to form a bipolar transistor-complementary bipolar CMOS (BiCMOS) element . In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below in conjunction with the accompanying drawings for detailed description as follows. 7 This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) ----------- installation ---- (please read the note on the back first and then fill out this page) Order: 511165 7839twfl.doc / 006 A7 _B7 _ V. Brief description of the invention () Figures 1A to 1E show the conventional manufacturing process of a heterojunction bipolar transistor. Sectional schematic diagrams; FIGS. 2A to 2G are schematic cross-sectional schematic diagrams of the manufacturing process of a self-aligned bipolar transistor of the present invention; and FIGS. 3A to 31 are schematic self-aligned bipolar transistor crystals. A schematic cross-sectional view of a manufacturing process of an aligned bipolar transistor. Description of the drawings: 100, 200, 300 · · substrates 102, 202, 302: epitaxial layers 104, 104a, 108, 112: insulating layers 106, 116, 212, 218, 316, 316a, 318, 318a ·· Conductor layer Intellectual Property Bureau of the Ministry of Economy Employees' clothing cooperatives Printed garments 106a, 222: Base 110, 208, 312 · · Opening 114: Spacer 118, 212a, 319 · · Emitter 120 · · Pitch 204, 206, 304, 306, 308, 310 ·· Dielectric layer 210 · 314 ·· Conductor spacers 214, 216, 320, 321: Doping process 218, 322: Base contact area This paper applies the Chinese National Standard (CNS) A4 specification ( (210 X 297 mm) 511165 A7 B7 7; printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 7839twf1.doc / 006 Description of the invention (q) 324: partition wall 326: metal silicide First Embodiment Figures 2A to 2G The drawing shows a schematic cross-sectional view of a manufacturing process of a self-aligned bipolar transistor according to the present invention. First, referring to FIG. 2A, a substrate 200 with a collector terminal is provided. The material of the substrate 200 is, for example, a group selected from the group consisting of germanium silicide, sand, gallium silicide, and indium phosphide, and a layer is formed on the substrate 200. Epitaxial layer 202. Next, a dielectric layer 204 and a dielectric layer 206 are sequentially formed on the crystalline layer 202. The epitaxial layer 202 is used as the base of a bipolar transistor. Its material is selected from, for example, germanium silicide, silicon, gallium arsenide, thorium phosphide, aluminum gallium arsenide alloy (AlxGa ^ xAs, 1), indium. A group consisting of a gallium arsenide alloy (ij ^ GahAs, X'1) is formed by, for example, chemical vapor deposition 'molecular beam curtain crystal growth. The material of the dielectric layer 204 is, for example, oxidized stone, and the method for forming it is, for example, chemical vapor deposition. The material of the dielectric layer 206 is a conventional dielectric layer, such as silicon nitride, silicon oxide, and oxynitride. The formation method of silicon, silicon carbide, or the like is, for example, a chemical vapor deposition method. Next, referring to FIG. 2B, an opening 208 'is formed in the dielectric layer 206, and a dielectric layer 204 is exposed at the bottom of the opening 208. The method for forming the opening 208 is, for example, forming a patterned mask layer (not shown) on the dielectric layer 206, and using the mask layer as a mask, etching to remove the uncovered dielectric layer 206 from the mask layer to expose On the surface of the dielectric layer 204, the mask layer is removed. Then, a conductor gap 210 is formed on both side walls of the opening 208. Among them, the conductor gap wall This paper size applies to China National Standard (CNS) A4 specification (210 X 297 mm) (Please read the precautions on the back before filling this page)
經濟部智慧財產局員工消費合作社印製 511165 7839twfl.doc/006 A7 B7 五、發明說明（& ) 210的材質例如是多晶型導體材料，形成的方法例如是在 介電層206以及開口 208中被覆一層導體層(未圖示），再 以回蝕刻的方法去除開口 208之外的導體層’其中導體層 的形成方法例如是化學氣相沈積法。 接著，請參照第2C圖，以介電層206以及導體間隙 壁210爲罩幕，去除開口 208中的介電層204至露出磊晶 層202的表面。其中去除介電層204的方法例如是非等向 性蝕刻法。然後，去除開口 312中的介電層304至露出磊 晶層202。 由於在此步驟中，導體間隙壁210與介電層204、介 電層206具有不同的蝕刻選擇性，因此能夠以介電層206 以及導體間隙壁210爲罩幕，直接進行蝕刻以形成後續形 成的射極與磊晶層202接觸用的開口 208，因此形成開口 208的製程爲一自行對準的製程，而並不須使用微影製程。 接著，請參照第2D圖，在基底200上被覆一層導體 層212，其中導體層212的材質例如是多晶矽，形成的方 法例如是化學氣相沈積法。 接著，請參照第2E圖，以介電層206爲蝕刻終止層， 回蝕刻去除部份的導體層212至露出介電層206的表面， 所殘留的導體層212則成爲雙載子電晶體的射極212a。 接著，請參照第2F圖，完全去除介電層206，其中去 除介電層206的方法例如是使用熱磷酸浸蝕的濕式蝕刻 法。然後以一摻雜製程214對射極212a進行摻雜，其中 摻雜製程214例如是使用離子植入法，所使用的摻質例如 10 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注音？事項再填寫本頁) 裝 · 經濟部智慧財產局員工消費合作社印製 511165 7839twfl.doc/006 B7 五、發明說明（q) 是η型摻質，且此η型摻質包括砷。 接著，請參照第2G圖，以射極212a以及導體間隙壁 210爲罩幕，去除部份的介電層204至露出磊晶層202的 表面。其中去除部份介電層308的方法例如是非等向性蝕 刻法。然後，以射極212a以及導體間隙壁210爲罩幕’ 對磊晶層202進行摻雜製程216，以於磊晶層202中以形 成基極接觸區218，其中所使用的摻質例如是P型摻質’ 且此P型摻質包括硼。 本發明第一實施例之自行對準雙載子電晶體的結構請 參照第2G圖。 如第2G圖所示，此自行對準雙載子電晶體的結構至 少包括具有集極端之基底200，射極212a、導體間隙壁 210、基極202以及基極接觸區218。 其中基極202係設置於基底200上，其中基底200的 材質例如是選自矽化鍺、矽、矽化鎵、磷化銦所組成之族 群，基極202的材質例如是選自矽化鍺、矽、砷化鎵、磷 化銦、銘砷化鎵合金（AlxGapxAs，1)、銦砷化鎵合金 (InxGaNxAS5 x‘l)所組成之族群，其形成的方法例如是以 化學氣相沈積法，分子束磊晶成長等形成於基底200上。 基極接觸區218係設置於基極202兩側之基底上，其 中基極接觸區218的材質例如是選自矽化鍺、矽、砷化鎵、 磷化銦、鋁砷化鎵合金(AlxGahAs, xS 1)、銦砷化鎵合金 (InxGa1-xAs5 x^l)所組成之族群，其形成的方法例如是以 化學氣相沈積法，分子束磊晶成長等形成於基底200上， 11 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注音3事項再填寫本頁) 裝 訂！ 經濟部智慧財產局員工消費合作社印製 511165 7839twf1.doc/006 A7 B7 五、發明說明（p) 其中基極202與基極接觸區218的摻雜形態相同，且基極 接觸區218的摻雜濃度高於基極202的摻雜濃度。 射極212a係設置於基極202上，其中射極212a的材 質例如是多晶矽，形成射極212a的方法例如是化學氣相 沈積法。其中射極212a的摻雜形態與作爲集極的基底200 的摻雜形態相同，與基極202以及基極接觸區218的摻雜 形態相反。在本發明第一實施例中，射極212a與基底200 的摻雜形態爲η型，基極202與基極接觸區218的摻雜形 態爲Ρ型。 導體間隙壁210係設置於射極212a上部的側壁，其 中導體間隙壁210的材質例如是多晶型導體材料，並且其 摻雜形態與射極212a的摻雜形態相同。 並且，亦可將介電層204設置於導體間隙壁210與基 極202之間的側壁，介電層204的材質例如是氧化矽。 在上述本發明第一實施例中，介電層204的材質爲氧 化砂、介電層206的材質爲氮化砂，然而，本發明的介電 層204、206並不限於此，可以使用具有不同蝕刻選擇性 的材質。更加的，介電層204、206亦可以藉由適當的蝕 刻製程控制，而使用相同的材質。 尙且，於本發明第一實施例中，所形成的自行對準雙 載子電晶體係爲npn型式，然而本發明並不限定於此，亦 可以應用於pnp型式的雙載子電晶體。 更進一步的，本發明之自行對準雙載子電晶體能夠應 用於結合雙載子電晶體與互補式金氧半電晶體於同一晶片 12 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注音？事項再填寫本頁) 裝 訂： 經濟部智慧財產局員工消費合作社印製 511165 7 8 3 9twf1. doc/ 00 6 A7 B7 五、發明說明（ί() 上的雙載子電晶體-互補式金氧半導體（BiCMOS)製程，而 在晶片上形成P型金氧半電晶體以及η型金氧半電晶體的 同時，於晶片上形成本發明之自行對準雙載子電晶體。 第二實施例 第3Α圖至第31圖所繪示爲本發明之另一種自行對準 雙載子電晶體的製造流程的剖面示意圖。 首先，請參照第3Α圖，提供一個具有集極端之基底 300，其中基底300的材質例如是選自矽化鍺、矽、矽化 鎵、磷化銦所組成之族群，且在基底300上形成有一層的 磊晶層302，其中此磊晶層302係作爲雙載子電晶體的基 極，其材質例如是選自矽化鍺、矽、砷化鎵、磷化銦、鋁 砷化鎵合金(AlxGapxAs，1)、銦砷化鎵合金(Ii^GakAs，x ‘1)所組成之族群，形成的方法例如是使用化學氣相沈積 法，分子束磊晶成長等。。接著，在磊晶層302上依序形 成介電層304、介電層306、介電層308、介電層310。其 中介電層304的材質例如是氧化矽，形成方法例如是低溫 氧化法（low temperature oxidation)，且其形成的厚度爲1〇〇 埃至500埃左右。介電層306的材質爲習用之介電層材質 例如是氮化矽、氧化矽、氮氧化矽或碳化矽等，形成方法 例如是化學氣相沈積法，且其形成的厚度爲100埃至500 埃左右。介電層308的材質例如是氧化矽，形成方法例如 是化學氣相沈積法，且其形成的厚度爲1000埃至3000埃 左右。介電層310的材質例如是氮化矽，形成方法例如是 13 表紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注音？事項再填寫本頁) 裝 訂·- 經濟部智慧財產局員工消費合作社印製 511165 7^39twf1.doc/〇〇6 A7 -------__B7__ 五、發明說明（/^) 化學氣相沈積法，且其形成的厚度爲1000埃至3000埃左 右。 在本發明第二實施例中，形成介電層304以及介電層 306的目的係用以保護磊晶層3〇2，並且亦可以作爲蝕刻 終止層，以精確的控制後續的蝕刻製程。 接著，請參照第3B圖，在介電層310中形成開口 312， 且在開口 312的底部露出介電層308。其中形成開口 312 的方法例如是在介電層310上形成圖案化的罩幕層（未圖 示），並以罩幕層爲罩幕，蝕刻去除罩幕層未覆蓋之介電 層310至露出介電層308表面，再去除罩幕層。然後，在 開口 312的兩側壁形成導體間隙壁314。其中導體間隙壁 314的材質例如是多晶型導體材料，形成的方法例如是在 介電層310以及開口 312中被覆一層導體層(未圖示），再 以回蝕刻的方法去除開口 312之外的導體層。 接著，請參照第3C圖，以介電層310以及導體間隙 壁314爲罩幕，去除開口 312中的介電層308以及介電層 306至露出介電層304的表面。其中去除介電層308以及 介電層306的方法例如是非等向性蝕刻法。然後，去除開 口 312中的介電層304至露出磊晶層302的表面。其中去 除介電層304的方法例如是使用緩衝氧化物蝕刻液(buffer oxide etchant, BOE)浸蝕的濕式浸蝕法。 由於在此步驟中，能夠以介電層310以及導體間隙壁 314爲罩幕，直接進行蝕刻以形成後續形成的射極與矽化 鍺磊晶層302接觸的開口 312，因此形成開口 312的製程 14 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁)Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 511165 7839twfl.doc / 006 A7 B7 V. & Description 210 The material of the 210 is, for example, a polycrystalline conductor material, and the forming method is, for example, the dielectric layer 206 and the opening 208 A conductive layer (not shown) is coated in the middle, and the conductive layer outside the opening 208 is removed by an etch-back method. The method for forming the conductive layer is, for example, a chemical vapor deposition method. Next, referring to FIG. 2C, using the dielectric layer 206 and the conductive spacer 210 as a mask, the dielectric layer 204 in the opening 208 is removed to expose the surface of the epitaxial layer 202. The method in which the dielectric layer 204 is removed is, for example, an anisotropic etching method. Then, the dielectric layer 304 in the opening 312 is removed to expose the epitaxial layer 202. In this step, the conductive spacer wall 210 has different etching selectivity from the dielectric layer 204 and the dielectric layer 206, so the dielectric layer 206 and the conductive spacer wall 210 can be used as a mask to directly etch to form a subsequent formation. The opening 208 for the emitter to contact the epitaxial layer 202, so the process of forming the opening 208 is a self-aligning process, and the lithography process is not required. Next, referring to FIG. 2D, a conductive layer 212 is coated on the substrate 200. A material of the conductive layer 212 is, for example, polycrystalline silicon, and a method of forming the conductive layer 212 is, for example, chemical vapor deposition. Next, referring to FIG. 2E, the dielectric layer 206 is used as an etch stop layer. Part of the conductor layer 212 is etched back to expose the surface of the dielectric layer 206, and the remaining conductor layer 212 becomes a bipolar transistor. Emitter 212a. Next, referring to FIG. 2F, the dielectric layer 206 is completely removed. The method for removing the dielectric layer 206 is, for example, a wet etching method using hot phosphoric acid etching. Then, the emitter 212a is doped by a doping process 214, wherein the doping process 214 is, for example, an ion implantation method, and the dopant used is, for example, 10 paper standards that are applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) (Please read the phonetic on the back? Matters before filling out this page) Equipment · Printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 511165 7839twfl.doc / 006 B7 V. Invention Description (q) is η-type dopant, And this n-type dopant includes arsenic. Next, referring to FIG. 2G, with the emitter 212a and the conductive spacer 210 as a mask, a part of the dielectric layer 204 is removed to expose the surface of the epitaxial layer 202. A method of removing a portion of the dielectric layer 308 is, for example, an anisotropic etching method. Then, the dopant process 216 is performed on the epitaxial layer 202 with the emitter 212a and the conductive spacer 210 as a mask, so as to form a base contact region 218 in the epitaxial layer 202. The dopant used is, for example, P 'Type dopant' and this P-type dopant includes boron. Please refer to FIG. 2G for the structure of the self-aligned bipolar transistor of the first embodiment of the present invention. As shown in FIG. 2G, the structure of the self-aligned bipolar transistor includes at least a substrate 200 having a collector terminal, an emitter electrode 212a, a conductor spacer 210, a base electrode 202, and a base contact region 218. The base 202 is disposed on the substrate 200. The material of the base 200 is selected from the group consisting of germanium silicide, silicon, gallium silicide, and indium phosphide. The material of the base 202 is selected from germanium silicide, silicon, A group consisting of gallium arsenide, indium phosphide, indium gallium arsenide alloy (AlxGapxAs, 1), and indium gallium arsenide alloy (InxGaNxAS5 x'l). The formation method is, for example, chemical vapor deposition, molecular beam Epitaxial growth and the like are formed on the substrate 200. The base contact region 218 is disposed on the substrate on both sides of the base 202. The material of the base contact region 218 is, for example, selected from the group consisting of germanium silicide, silicon, gallium arsenide, indium phosphide, and aluminum gallium arsenide alloy (AlxGahAs, xS 1), a group consisting of indium gallium arsenide alloy (InxGa1-xAs5 x ^ l), which is formed on the substrate 200 by, for example, chemical vapor deposition, molecular beam epitaxial growth, etc. 11 papers Standards are applicable to China National Standard (CNS) A4 specifications (210 X 297 mm) (Please read the note 3 on the back before filling this page) Binding! Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 511165 7839twf1.doc / 006 A7 B7 V. Description of the invention (p) Where the base 202 has the same doping pattern as the base contact region 218, and the doping of the base contact region 218 The concentration is higher than the doping concentration of the base electrode 202. The emitter electrode 212a is disposed on the base electrode 202. The material of the emitter electrode 212a is, for example, polycrystalline silicon. The method for forming the emitter electrode 212a is, for example, chemical vapor deposition. The doping configuration of the emitter 212a is the same as that of the substrate 200 as the collector, and is opposite to the doping configuration of the base 202 and the base contact region 218. In the first embodiment of the present invention, the doping state of the emitter 212a and the substrate 200 is n-type, and the doping state of the base 202 and the base contact region 218 is P-type. The conductor gap wall 210 is provided on the upper side wall of the emitter 212a. The material of the conductor gap wall 210 is, for example, a polycrystalline conductor material, and its doping form is the same as that of the emitter 212a. In addition, a dielectric layer 204 may be provided on a sidewall between the conductive spacer 210 and the base 202. The material of the dielectric layer 204 is, for example, silicon oxide. In the above-mentioned first embodiment of the present invention, the material of the dielectric layer 204 is oxidized sand and the material of the dielectric layer 206 is nitrided sand. However, the dielectric layers 204 and 206 of the present invention are not limited to this. Materials with different etch selectivity. Furthermore, the dielectric layers 204 and 206 can also be controlled by an appropriate etching process and use the same material. Moreover, in the first embodiment of the present invention, the self-aligned bipolar transistor system formed is an npn type, but the present invention is not limited to this, and can also be applied to a pnp type bipolar transistor. Furthermore, the self-aligned bipolar transistor of the present invention can be applied to the combination of the bipolar transistor and the complementary metal-oxide semiconductor on the same wafer. 12 The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) (Please read the phonetic on the back? Matters before filling out this page) Binding: Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 511165 7 8 3 9twf1. Doc / 00 6 A7 B7 V. Description of the Invention (ί ( ) On the wafer, the P-type metal-oxide semiconductor and the n-type metal-oxide semiconductor are formed on the wafer, and the self-formation of the present invention is formed on the wafer. Alignment of the bipolar transistor. Figures 3A to 31 of the second embodiment are cross-sectional schematic diagrams of the manufacturing process of another self-aligned bipolar transistor of the present invention. First, please refer to Figure 3A Provide a substrate 300 having a collector terminal. The material of the substrate 300 is, for example, a group selected from the group consisting of germanium silicide, silicon, gallium silicide, and indium phosphide, and an epitaxial layer 302 is formed on the substrate 300. Epitope The 302 series is used as the base of a bipolar transistor. Its material is selected from, for example, germanium silicide, silicon, gallium arsenide, indium phosphide, aluminum gallium arsenide alloy (AlxGapxAs, 1), indium gallium arsenide alloy (Ii ^ The group formed by GakAs, x '1) is formed by, for example, chemical vapor deposition, epitaxial growth of molecular beams, etc. Then, a dielectric layer 304 and a dielectric layer are sequentially formed on the epitaxial layer 302. 306, a dielectric layer 308, and a dielectric layer 310. The material of the dielectric layer 304 is, for example, silicon oxide, and the formation method is, for example, low temperature oxidation, and the thickness of the dielectric layer 304 is 100 angstroms to 500 angstroms. The material of the dielectric layer 306 is a conventional dielectric layer material such as silicon nitride, silicon oxide, silicon oxynitride, or silicon carbide, and the formation method is, for example, chemical vapor deposition, and the thickness thereof is 100 angstroms. To about 500 angstroms. The material of the dielectric layer 308 is, for example, silicon oxide, and the formation method is, for example, chemical vapor deposition, and the thickness of the dielectric layer 308 is about 1000 to 3,000 angstroms. The material of the dielectric layer 310 is, for example, silicon nitride. The forming method is, for example, 13 sheets National Standard (CNS) A4 Specification (210 X 297 mm) (Please read the phonetic on the back? Matters before filling out this page) Binding ·-Printed by the Employees' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 511165 7 ^ 39twf1.doc / 〇〇 6 A7 -------__ B7__ 5. Description of the Invention (/ ^) The chemical vapor deposition method has a thickness of about 1000 angstroms to about 3000 angstroms. In the second embodiment of the present invention, a dielectric layer is formed. The purpose of 304 and the dielectric layer 306 is to protect the epitaxial layer 302, and it can also be used as an etch stop layer to precisely control subsequent etching processes. Next, referring to FIG. 3B, an opening 312 is formed in the dielectric layer 310, and a dielectric layer 308 is exposed at the bottom of the opening 312. The method for forming the opening 312 is, for example, forming a patterned mask layer (not shown) on the dielectric layer 310, and using the mask layer as a mask, the dielectric layer 310 not covered by the mask layer is etched to be exposed. On the surface of the dielectric layer 308, the mask layer is removed. Then, conductor gaps 314 are formed on both side walls of the opening 312. The material of the conductor spacer 314 is, for example, a polycrystalline conductor material, and the formation method is, for example, coating a conductive layer (not shown) in the dielectric layer 310 and the opening 312, and then removing the outside of the opening 312 by an etch-back method. Conductor layer. Next, referring to FIG. 3C, using the dielectric layer 310 and the conductive spacer 314 as a mask, the dielectric layer 308 and the dielectric layer 306 in the opening 312 are removed to expose the surface of the dielectric layer 304. The method of removing the dielectric layer 308 and the dielectric layer 306 is, for example, an anisotropic etching method. Then, the dielectric layer 304 in the opening 312 is removed to expose the surface of the epitaxial layer 302. The method for removing the dielectric layer 304 is, for example, a wet etching method using buffer oxide etchant (BOE) etching. In this step, the dielectric layer 310 and the conductive spacer 314 can be used as a mask to directly etch to form a subsequently formed opening 312 where the emitter contacts the germanium silicide epitaxial layer 302, so the process of forming the opening 312 14 This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) (Please read the precautions on the back before filling this page)
511165 7 8 3 9twf1. doc/Ο Ο 6 A7511165 7 8 3 9twf1. Doc / Ο Ο 6 A7
五、發明說明（丨^) 爲一自行對準的製程，而並不須使用微影製程。 而且，此處使用溼式浸蝕法剝除介電層304係因爲濕 式浸蝕法對於介電層304以及磊晶層302具有高蝕刻選擇 比’因此能夠避免蝕刻製程傷害到磊晶層302而使其中的 矽流失。 接著，請參照第3D圖，在基底300上被覆一層共形 的導體層316，再以對導體層316進行摻質的摻雜。其中 導體層316的材質例如是多晶矽，且摻質例如是η型摻質 並包括砷。然後，在導體層316上被覆一層導體層318， 其中導體層318的材質例如是多晶矽。 在此處於形成導體層318之前，先形成共型的導體層 316並進行摻雜的目的，係用以確保後續所形成的射極在 底部的摻雜濃度能夠均勻。 接著，請參照第3Ε圖，以介電層310爲蝕刻終止層， 回蝕刻去除部份的導體層318以及部份的導體層316至露 出介電層310的表面，所殘留的導體層318a以及導體層 316a則合倂成爲雙載子電晶體的射極319。 接著，請參照第3F圖，完全去除介電層31〇，其中去 除介電層310的方法例如是使用熱磷酸浸蝕的濕式蝕刻 法。然後，對射極319進行摻雜製程320，其中摻雜製程 320例如是使用離子植入法，所使用的摻質例如是n型摻 質，且此η型摻質包括砷。 接著，請參照第3G圖，以射極320與導體間隙壁314 爲罩幕，去除部份的介電層308至露出介電層306的表面。 15 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注音？事項再填寫本頁) 裝 . 經濟部智慧財產局員工消費合作社印製 511165 7839twfl.doc/006 A7 ________ B7 五、發明說明（丨+) 其中去除部份介電層308的方法例如是非等向性蝕刻法。 然後’以射極319與導體間隙壁314爲罩幕，對矽化鍺磊 晶層302進行摻雜製程321，以將部份磊晶層（基極）形成 基極接觸區322。其中摻雜製程321例如是使用離子植入 法，所使用的摻質例如是p型摻質，且此p型摻質包括硼。 接著，請參照第3H圖，在射極319以及殘留的介電 層308的側壁形成間隙壁324。其中間隙壁324的材質例 如是氧化矽，形成間隙壁324的方法例如是在基底300上 被覆一層絕緣層（未圖示），再回蝕絕緣層以去除射極319、 導體間隙壁314以及基極322上的絕緣層而形成間隙壁 324。然後，以射極319、導體間隙壁314以及間隙壁324 爲罩幕，去除介電層306至露出介電層304的表面。其中 去除介電層306的方法例如是非等向性蝕刻法。其後，去 除介電層304至露出基極322的表面。其中剝除介電層304 的方法例如是使用緩衝氧化物蝕刻液浸蝕的濕式浸蝕法。 同樣的，在第3F圖至3H圖的步驟中，對於介電層310 以及介電層304的去除係使用濕式浸蝕法，並且對於介電 層308以及介電層306的去除係使用射極319與導體間隙 壁314爲罩幕所進行的非等向性蝕刻，並不須要使用微影 製程，因此爲一自行對準製程。尙且，射極319與基極322 的間距能夠藉由導體間隙壁314的厚度做適當的調整，因 此能夠相當容易的控制射極319與基極接觸區322的間 距，使得製程具有較寬裕的裕度。 接著，請參照第31圖，在射極320以及基極接觸區322 16 本紙張尺度適用中國國家標準（CNS>A4規格（210 X 297公釐） -------— II —Αν--裝--- (請先閱讀背面之注意事項再填寫本頁) . · 經濟部智慧財產局員工消費合作社印製 5 6 7 8 3 9 twf1. do c/Ο Ο β 發明說明（/<) 上形成自行對準金屬矽化物層326 °其中自行對準金屬砂 化物層326的材質例如是矽化鎳、矽化鈷或是矽化鈦等’ 形成的方法例如是在基底300上被覆一層金屬層（未圖 示），再將此基底300進行回火製程，以使射極319與基 極接觸區322與金屬層接觸的位置反應產生自行對準金屬 矽化物層326，然後再去除未反應的金屬層。 本發明第二實施例之自行對準雙載子電晶體的結構請 參照第31圖。 如第31圖所示，此自行對準雙載子電晶體的結構至 少包括具有集極端之基底300,射極319、導體間隙壁314、 基極302以及基極接觸區322。 基極302係設置於基底300上，其中基底300的材質 例如是選自砂化鍺、砂、砂化鎵、磷化銦所組成之族群， 且基極3 0 2的材質例如是選自砂化鍺、敬、神化嫁、鱗化 銦、鋁砷化鎵合金（AlxGai_xAs，X $ 1)、銦砷化鎵合金 (InxGa卜xAs，x$l)戶斤組成之方矣君羊’其形成的方法例如是以 化學氣相沈積法，分子束磊晶成長等形成於基底300上。 基極接觸區322係設置於基極202兩側之基底上，其 中基極接觸區322的材質例如是選自矽化鍺、矽、砷化鎵、 磷化銦、鋁砷化鎵合金(ALGakAs，xg 1)、絪砷化鎵合金 (InxGa卜xAs，x‘l)所組成之族群，其形成的方法例如是以 化學氣相沈積法’分子束晶晶成長等形成於基底300上， 其中基極302與基極接觸區322的摻雜形態相同，且基極 接觸區322的摻雜濃度高於基極302的摻雜濃度。 17 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閲讀背面之注意事項再填寫本頁) 裝 經濟部智慧財產局員工消費合作社印製 511165 7839twfl.doc/006 A7 B7 五、發明說明（/έ) 射極319係設置於基極302上，其中射極319的材質 例如是多晶矽，形成射極319的方法例如是化學氣相沈積 法。其中射極319的摻雜形態與作爲集極的基底3〇〇的摻 雜形態相同，與基極302以及基極接觸區322的摻雜形態 相反。在本發明第二實施例中，射極319與基底300的摻 雜形態爲η型，則基極302與基極接觸區322的摻雜形態 爲Ρ型。 導體間隙壁314係設置於射極319上部的側壁，其中 導體間隙壁314的材質例如是多晶型導體材料，並且其摻 雜形態與射極319的摻雜形態相同。 在上述的結構中，更包括有： 介電層304係設置射極319兩側之基極302上，並且 延伸至部份之基極接觸區322上，其材質例如是氧化矽， 形成的方法例如是低溫氧化法。 介電層306係設置介電層304上，其材質例如是氮化 矽、氧化矽、氮氧化矽或碳化矽等，形成的方法例如是化 學氣相沈積法。 介電層308設置於導體間隙壁210與介電層306之間 的射極側壁，其材質例如是氧化矽，形成的方法例如是化 學氣相沈積法，並且介電層308的端部分別與基極302的 兩端部略爲對齊。 間隙壁324係設置於導體間隙壁314與介電層308的 側壁，其材質例如是氧化矽，並且間隙壁314的端部分別 與介電層306的兩端部略爲對齊。 18 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注咅？事項再填寫本頁) 裝 經濟部智慧財產局員工消費合作社印製 511165 7839twfl.doc/006 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（q) 金屬層326係設置於射極319、導體間隙壁314、基 極接觸區322上，其材質例如是矽化鎳、矽化鈷或是砂化 鈦等。 在上述本發明第二實施例中，介電層304的材質爲氧 化矽、介電層306的材質爲氮化矽、介電層308的材質爲 氧化矽且介電層310的材質爲氮化矽，然而，本發明的介 電層304、306、308、310並不限於此，可以使用使介電 層彼此之間具有不同蝕刻選擇性的材質。更加的，介電層 310、308、306、304亦能夠藉由適當的蝕刻製程控制，而 使用相同的材質，甚或是於開始沈積介電層之前，即不沈 積介電層304、306。 尙且，於本發明第二實施例中，所形成的自行對準雙 載子電晶體係爲npn型式，然而本發明並不限定於此，亦 可以應用於pnp形式的雙載子電晶體。 同樣的，本發明第二實施例之自行對準雙載子電晶 體’亦能夠應用於結合雙載子電晶體與互補式金氧半電晶 體於同一晶片上的雙載子電晶體-互補式金氧半導體 (BiCMOS)製程。 綜上所述，由上述第一實施例與第二實施例可知，本 發明的重要特徵係在於能夠使用自行對準的方式形成雙載 子電晶體的射極以及基極，並且對於射極以及基極接觸區 的間距的大小，亦能夠藉由自行對準製程而得到良好的控 制’因此本發明具有較寬裕的製程裕度。 而且，在形成射極以及基極的製程中，本發明僅有在 19 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注音？事項再填寫本頁)5. Description of the Invention (丨 ^) is a self-aligning process, and the lithography process is not required. Moreover, the wet etching method is used to strip the dielectric layer 304 here because the wet etching method has a high etching selectivity ratio for the dielectric layer 304 and the epitaxial layer 302. Therefore, the etching process can be prevented from damaging the epitaxial layer 302. The silicon is lost. Next, referring to FIG. 3D, a conformal conductive layer 316 is coated on the substrate 300, and then the conductive layer 316 is doped with a dopant. The material of the conductive layer 316 is, for example, polycrystalline silicon, and the dopant is, for example, an n-type dopant and includes arsenic. Then, a conductive layer 318 is coated on the conductive layer 316, and the material of the conductive layer 318 is, for example, polycrystalline silicon. Before forming the conductor layer 318 here, the purpose of forming a common conductor layer 316 and performing doping is to ensure that the doping concentration of the emitter formed later on the bottom can be uniform. Next, referring to FIG. 3E, the dielectric layer 310 is used as an etch stop layer. Part of the conductive layer 318 and part of the conductive layer 316 are etched back to expose the surface of the dielectric layer 310. The remaining conductive layer 318a and The conductor layer 316a is combined into an emitter 319 of a bipolar transistor. Next, referring to FIG. 3F, the dielectric layer 31 is completely removed. The method for removing the dielectric layer 310 is, for example, a wet etching method using hot phosphoric acid etching. Then, a doping process 320 is performed on the emitter 319. The doping process 320 is, for example, an ion implantation method. The dopant used is, for example, an n-type dopant, and the n-type dopant includes arsenic. Next, referring to FIG. 3G, with the emitter 320 and the conductive spacer 314 as a mask, a part of the dielectric layer 308 is removed to expose the surface of the dielectric layer 306. 15 This paper size is in accordance with Chinese National Standard (CNS) A4 (210 X 297 mm) (Please read the phonetic on the back? Matters before filling out this page). Packing. Printed by the Intellectual Property Bureau Staff Consumer Cooperative of the Ministry of Economic Affairs 511165 7839twfl.doc / 006 A7 ________ B7 V. Description of the Invention (丨 +) The method for removing part of the dielectric layer 308 is, for example, anisotropic etching. Then, the doping process 321 is performed on the germanium silicide epitaxial layer 302 with the emitter 319 and the conductor spacer 314 as a mask to form a part of the epitaxial layer (base) to form a base contact region 322. The doping process 321 uses, for example, an ion implantation method. The dopant used is, for example, a p-type dopant, and the p-type dopant includes boron. Next, referring to FIG. 3H, a spacer 324 is formed on the sidewalls of the emitter 319 and the remaining dielectric layer 308. The material of the spacer 324 is, for example, silicon oxide. The method of forming the spacer 324 is, for example, coating an insulating layer (not shown) on the substrate 300, and then etching back the insulating layer to remove the emitter 319, the conductor spacer 314, and the substrate. The insulating layer on the electrode 322 forms a partition wall 324. Then, using the emitter 319, the conductor spacer 314, and the spacer 324 as a mask, the dielectric layer 306 is removed to expose the surface of the dielectric layer 304. The method of removing the dielectric layer 306 is, for example, an anisotropic etching method. Thereafter, the dielectric layer 304 is removed to expose the surface of the base electrode 322. The method for removing the dielectric layer 304 is, for example, a wet etching method using a buffer oxide etching solution. Similarly, in the steps of FIGS. 3F to 3H, the wet etching method is used for the removal of the dielectric layer 310 and the dielectric layer 304, and the emitter is used for the removal of the dielectric layer 308 and the dielectric layer 306. The anisotropic etching performed by 319 and the conductor gap wall 314 for the mask does not require the use of a lithography process, so it is a self-alignment process. In addition, the distance between the emitter 319 and the base 322 can be appropriately adjusted by the thickness of the conductor gap wall 314, so the distance between the emitter 319 and the base contact area 322 can be easily controlled, so that the manufacturing process has a wider margin. Margin. Next, please refer to Figure 31, the emitter 320 and the base contact area 322 16 This paper size applies the Chinese national standard (CNS > A4 specification (210 X 297 mm) --------- II —Αν- -Install --- (Please read the precautions on the back before filling this page). · Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 5 6 7 8 3 9 twf1. Do c / Ο Ο β Description of the invention (/ < ) A self-aligned metal silicide layer 326 is formed thereon. The material of the self-aligned metal sand layer 326 is, for example, nickel silicide, cobalt silicide, or titanium silicide. The formation method is, for example, coating a metal layer on the substrate 300 ( (Not shown), and then subject the substrate 300 to a tempering process so that the position where the emitter 319 and the base contact region 322 contact the metal layer reacts to generate a self-aligned metal silicide layer 326, and then remove the unreacted metal The structure of the self-aligned bipolar transistor according to the second embodiment of the present invention is shown in FIG. 31. As shown in FIG. 31, the structure of the self-aligned bipolar transistor includes at least a substrate having a collector terminal. 300, emitter 319, conductor spacer 314, base 302, and base The electrode contact region 322. The base electrode 302 is disposed on the substrate 300, wherein the material of the substrate 300 is, for example, a group selected from the group consisting of germanized sand, sand, gallium sand, and indium phosphide, and the material of the base electrode 302 is For example, it is selected from the group consisting of germanium sand, Jing, Shenhua, indium, aluminum gallium arsenide alloy (AlxGai_xAs, X $ 1), indium gallium arsenide alloy (InxGa, xAs, x $ l) Jun Yang's formation method is, for example, chemical vapor deposition, molecular beam epitaxial growth, etc. formed on the substrate 300. The base contact region 322 is disposed on the substrate on both sides of the base 202, wherein the base contact region The material of 322 is, for example, a group consisting of germanium silicide, silicon, gallium arsenide, indium phosphide, aluminum gallium arsenide alloy (ALGakAs, xg 1), thallium gallium arsenide alloy (InxGa, xAs, x'l) The formation method is, for example, a chemical vapor deposition method for forming molecular beam crystal growth on the substrate 300, wherein the base 302 and the base contact region 322 have the same doping form, and the doping of the base contact region 322 is the same. The impurity concentration is higher than the doping concentration of the base 302. 17 This paper size applies to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) (Please read the notes on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 511165 7839twfl.doc / 006 A7 B7 V. Description of the invention (/ έ) Emitter 319 series settings On the base 302, the material of the emitter 319 is, for example, polycrystalline silicon, and the method of forming the emitter 319 is, for example, chemical vapor deposition. The doping configuration of the emitter 319 and the doping of the substrate 300 as the collector are The morphology is the same as the doping morphology of the base 302 and the base contact region 322. In the second embodiment of the present invention, the doping configuration of the emitter 319 and the substrate 300 is n-type, and the doping configuration of the base 302 and the base contact region 322 is P-type. The conductor spacer 314 is provided on the upper side wall of the emitter 319. The material of the conductor spacer 314 is, for example, a polycrystalline conductor material, and its doped form is the same as that of the emitter 319. In the above structure, the method further includes: the dielectric layer 304 is provided on the base 302 on both sides of the emitter 319, and extends to a part of the base contact area 322. The material is, for example, silicon oxide. For example, a low-temperature oxidation method. The dielectric layer 306 is disposed on the dielectric layer 304. The material of the dielectric layer 306 is, for example, silicon nitride, silicon oxide, silicon oxynitride, or silicon carbide. The formation method is, for example, a chemical vapor deposition method. The dielectric layer 308 is disposed on the side wall of the emitter between the conductive spacer 210 and the dielectric layer 306. The material of the dielectric layer 308 is, for example, silicon oxide. The formation method is, for example, chemical vapor deposition, and the ends of the dielectric layer 308 are respectively Both ends of the base 302 are slightly aligned. The spacer 324 is disposed on the side walls of the conductor spacer 314 and the dielectric layer 308. The material is, for example, silicon oxide, and the ends of the spacer 314 are slightly aligned with the two ends of the dielectric layer 306, respectively. 18 This paper size is in accordance with Chinese National Standard (CNS) A4 (210 X 297 mm) (Please read the note on the back? Matters before filling out this page.) Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs, Consumer Cooperatives 511165 7839twfl.doc / 006 A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the Invention (q) The metal layer 326 is provided on the emitter 319, the conductor gap 314, and the base contact area 322. The material is, for example, nickel silicide, Cobalt silicide or titanium sand. In the second embodiment of the present invention, the material of the dielectric layer 304 is silicon oxide, the material of the dielectric layer 306 is silicon nitride, the material of the dielectric layer 308 is silicon oxide, and the material of the dielectric layer 310 is nitride. Silicon, however, the dielectric layers 304, 306, 308, and 310 of the present invention are not limited to this, and a material that allows the dielectric layers to have different etching selectivities from each other can be used. Furthermore, the dielectric layers 310, 308, 306, and 304 can also be controlled by an appropriate etching process, and the same material is used, or the dielectric layers 304, 306 are not deposited before the dielectric layer is started to be deposited. Moreover, in the second embodiment of the present invention, the self-aligned bipolar transistor system formed is an npn type, but the present invention is not limited to this, and can also be applied to a pnp bipolar transistor. Similarly, the self-aligned bipolar transistor of the second embodiment of the present invention can also be applied to a bipolar transistor-complementary type that combines a bipolar transistor and a complementary metal-oxide semiconductor on the same wafer. Metal Oxide Semiconductor (BiCMOS) process. In summary, according to the first and second embodiments described above, it is known that the important feature of the present invention is that the emitter and base of a bipolar transistor can be formed in a self-aligned manner. The size of the pitch of the base contact region can also be well controlled by the self-alignment process. Therefore, the present invention has a wider process margin. In addition, in the process of forming the emitter and base, the present invention is only applicable to the Chinese national standard (CNS) A4 specification (210 X 297 mm) on 19 paper sizes. (Please read the note on the back? Matters before filling in this page)
511165 7839twf1.doc/〇〇6 A7 _ _____ B7 五、發明說明（/^) 形成開口的製程必須使用微影蝕刻製 m習知 比，本發明至少能夠減少一道至二道的微影製程，因此本 發明產夠降低在微影製程所耗費的時間與成本支出，而有 效的簡化製程。 並且，本發明在第二實施例中去除磊晶層上的介電 層，以形成與射極以及基極的接觸時，由於採用介電層與 嘉晶層之間具有良好蝕刻選擇比的濕式蝕刻法，以將嘉晶 層上的介電層剝除，因此能夠避免磊晶層中矽材質的流 失。 更加的，由於本發明在射極以及基極上形成自行對準 金屬矽化物層，因此能夠降低射極與基極的阻値，進而提 高雙載子電晶體的操作速度。 雖然本發明已以一較佳實施例揭露如上，然其並非用 以限定本發明，任何熟習此技藝者，在不脫離本發明之精 神和範圍內，當可作些許之更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者爲準。 (請先閱讀背面之注意事項再填寫本頁) 裝 訂- 經濟部智慧財產局員工消費合作社印製 ο 2 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）511165 7839twf1.doc / 〇〇6 A7 _ _____ B7 V. Description of the Invention (/ ^) The process of forming the opening must use the lithographic etching process. The present invention can reduce at least one to two lithographic processes, so The invention can reduce the time and cost spent in the lithography process, and effectively simplify the process. In addition, in the second embodiment of the present invention, when the dielectric layer on the epitaxial layer is removed to form contact with the emitter and the base, the wet layer having a good etching selection ratio between the dielectric layer and the Jiajing layer is used. The etching method is used to peel off the dielectric layer on the Jiajing layer, so that the silicon material in the epitaxial layer can be prevented from being lost. Furthermore, since the self-aligned metal silicide layer is formed on the emitter and the base according to the present invention, the resistance between the emitter and the base can be reduced, thereby increasing the operation speed of the bipolar transistor. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make some modifications and retouching without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application. (Please read the precautions on the back before filling this page) Binding-Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs ο 2 This paper size applies to China National Standard (CNS) A4 (210 X 297 mm)