508786 五、發明說明（1) 本發明係有關於積體電路之抗靜電放電，特別是有關 種靜電放電保護裝置及其製造方法，能夠於狹小之摻 内形成靜電放電保護裝置，特別是適用於S0I結構 形成之靜電放電保護裝置。 半導體在絕緣層（semiconducto卜〇n_insulat〇r，下 文以SOI稱之）技術，係將-半導體層覆於基底上方，而以 ΐίΠ設ΐ於半導體層和基底間’並將積體電路形成於 +導體層之技術。若將M0S電晶體製於s〇I結構之半導體声 ，較之製於基底者，具有抗短通道效應較佳、次導通曰 (subtheshold)斜率較高、電流驅動增加、封裝密度 、寄生電容值降低、及製程步驟較為簡易等優點。门 參閱第1圖，第1圖係顯示傳統靜電放電保護裝置之 ，圖。如第1圖所示’傳統靜電放電保護裝置包括一; 區（P-well)l〇〇p型并區in白紅 、広』 汁 12上述源極區η以及沒極區12皆為推雜N型雜 區，源極⑽係麵接於接受外部信號之接合塾13、1雜 區1 2係耦接至接地電位，而疊層結構丨5為閘極。 降 汲極區12舒型井區1()接面之崩潰電M，傳統技術係了於降低 極區12與P型井區10接面處形成一p型摻雜區“，藉以使 汲極區1 2與P型井區i 〇之接面能夠較曰于 當_件發生於接合墊時，大量之二 放電保護裝置電Μ崩潰，並經由靜電放電保護裝置传引導電至 基底並排除，藉以避免大量之ESD電流損壞内部電路。 然而，基於前述之理_，S〇I技術已廣；乏運用於現a 第4頁 0503-6722TW ； TSMC2001-0672 ； ROBERT.ptd508786 V. Description of the invention (1) The present invention relates to the anti-static discharge of integrated circuits, in particular to an electrostatic discharge protection device and a manufacturing method thereof, which can form an electrostatic discharge protection device in a narrow mixture, especially suitable for Electrostatic discharge protection device formed by S0I structure. The technology of semiconductor in the insulation layer (semiconductobuon_insulat〇r, hereinafter referred to as SOI) is to cover the -semiconductor layer over the substrate, and to set it between the semiconductor layer and the substrate, and to form the integrated circuit at + Conductor technology. If the M0S transistor is made of a semiconductor sound with a soI structure, it has better resistance to short channel effects, a higher sub-shold slope, increased current drive, package density, and parasitic capacitance compared to those made on a substrate. Reduce, and the process steps are relatively simple and so on. Door Refer to Figure 1. Figure 1 shows a conventional electrostatic discharge protection device. As shown in FIG. 1, the traditional electrostatic discharge protection device includes a P-well 100p type parallel region in white red and ytterbium. The above-mentioned source region η and the non-electrode region 12 are all dopants. In the N-type miscellaneous region, the source electrode is connected to the junction receiving external signals, and the miscellaneous region 12 and 1 are coupled to the ground potential, and the stacked structure 5 is a gate electrode. The breakdown voltage M at the junction of the drain region 12 and the Shu-type well region 1 (), the traditional technique is to lower the junction of the electrode region 12 and the P-type well region 10 to form a p-type doped region. The interface between the area 12 and the P-type well area 〇 can be compared to when a _piece occurs on the bonding pad, a large number of two discharge protection devices are destroyed, and the electricity is guided to the substrate and eliminated through the electrostatic discharge protection device. In order to avoid a large amount of ESD current to damage the internal circuit. However, based on the foregoing principles, S0I technology has been widely used; it is not used in the present a page 0503-6722TW; TSMC2001-0672; ROBERT.ptd
以下將介紹形成於s〇i結構之M〇s電晶體結 之半導體技術 構。 ^圖係顯示形成·丨結構之咖電晶體結構之 d w圖。 形成於SOI結構之M0S電晶體於基底2〇之表面具有一絕 緣層21，接著，絕緣層21上具有__p型井區（p_wen ) 22 :P型井區22包括一源極區23以及汲極區24，上述源極區 23 Μ及沒極區24皆為摻雜N型雜質之摻雜區，源極區“係 耦接於接文外部信號之接合墊25，而汲極區24係耦接至接 地電位，而疊層結構26為閘極。 然而，在上述SO I結構中，因為絕緣層2丨之存在，使 得P型井區22顯得相當狹小，故無法以上述傳統技術所採 用之方法形成靜電放電保護裝置，即為於汲極區24之下方 另外再形成一 P型摻雜區以降低汲極端之崩潰電壓。此因 在於絕緣層21與汲極區24之間的空間並不足以容納設置適 當體積之摻雜區，將影響降低接面崩潰電壓之效果。因此 以傳統技術無法於具有SOI結構之M〇s電晶體上形成具有良 好抗靜電能力之靜電放電保護裝置。 有鑑於此，為了解決上述問題，本發明主要目的在於 k供一種靜電放電保護裝置及其製造方法，其内部具有 SO I結構，或者是因為特定之設計而具有狹小之摻雜區。 根據本發明之設計，能夠於具有例如SOI結構之M0S電 晶體形成一靜電放電保護裝置，有效的解決傳統技術之問 題。The semiconductor technology structure of the MOS transistor structure formed on the SiO structure will be described below. ^ The figure is a d w diagram showing the structure of a coffee crystal that forms a structure. The MOS transistor formed in the SOI structure has an insulating layer 21 on the surface of the substrate 20, and then, the insulating layer 21 has a __p-type well region (p_wen) 22: the P-type well region 22 includes a source region 23 and a drain The electrode region 24, the above-mentioned source region 23M and the non-electrode region 24 are all doped regions doped with N-type impurities. The source region is "coupled to the bonding pad 25 for receiving external signals, and the drain region 24 is It is coupled to the ground potential, and the stacked structure 26 is the gate. However, in the above SO I structure, the presence of the insulating layer 2 丨 makes the P-type well region 22 quite small, so it cannot be adopted by the conventional technology. The method of forming an electrostatic discharge protection device is to form a P-type doped region under the drain region 24 to reduce the breakdown voltage of the drain terminal. This is because the space between the insulating layer 21 and the drain region 24 is also reduced. It is not enough to accommodate a doped region with an appropriate volume, which will affect the effect of reducing the breakdown voltage of the junction. Therefore, it is impossible to form an electrostatic discharge protection device with good antistatic ability on a Mos transistor with an SOI structure by conventional techniques. In view of this, in order to solve the above problems, The main object of the invention is to provide an electrostatic discharge protection device and a manufacturing method thereof, which have an SO I structure inside or have a narrow doped region because of a specific design. According to the design of the present invention, it is possible to use an SOI structure for example. The MOS transistor forms an electrostatic discharge protection device, which effectively solves the problems of traditional technology.
0503-6722TWF ； TSMC2001-0672 ； ROBERT.ptd 第5頁 508786 五、發明說明（3) 為獲致上述之目 置，設置於耦接於第 包括下列元件。覆蓋 層之第一型井區。第 係形成於第一型井區 準。疊層結構係設置 發明提出一種靜電放電保護裝 之接合墊以及第二位準之間， 表面之絕緣層以及形成於絕緣 型摻雜區及第二第二型摻雜區 分別耦接於第一位準及第二位 型井區之表面，並位於第一第 雜區之間。另外，第一型摻雜 並位於第一型井區與第二第二 靜電放電保護裝置製造方法， 第一型井區於基底，接著形成 型井區，並耦接於一第一位準 雜區於第一型井區，並耦接於 一型摻雜區於第一型井區與第 最後，於上述第一型井區之 疊層結構係位於上述第一第二 區之間。 的，本 一位準 於基底 一第二 中，並 於第一 二型摻 區中， 二型摻 區係形 型摻雜 另 包括下 一第一 。接著 一第二 —* 梦 — —βρ 表面形 型摻雜 圖式之 為 下文特 下： 雜區及第二第 成於第一型井 區之接面附近。 外，本發明提出一種 列步驟：首先形成一 第二型摻雜區於第一 ’形成第二第二型摻 位準。另外，形成第 型摻雜區之接面附近 成一疊層結構，上述 區及第二第二型摻雜 簡單說明： 使本發明之上述目的、特徵和優點能更明顯易懂， 舉一較佳實施例，並配合所附圖式，作詳細說明如 圖不說明： 第1圖係顯示傳統靜電放電保護裝置之剖面圖。 第2圖係顧示形成於SO I結構之m〇s電晶體結構之妙構0503-6722TWF; TSMC2001-0672; ROBERT.ptd page 5 508786 V. Description of the invention (3) In order to achieve the above purpose, it is arranged to be coupled to the first component including the following components. The first well area of the overburden. The series is formed in the first type well area. The laminated structure is provided by the invention, which proposes an electrostatic discharge protection device between the bonding pad and the second level, and an insulating layer on the surface and the insulating type doped region and the second and second type doped region are respectively coupled to the first The level and the surface of the second type well area are located between the first and second miscellaneous areas. In addition, the manufacturing method of the first type doped and located in the first type well region and the second second electrostatic discharge protection device, the first type well region is on the substrate, and then the type well region is formed, and is coupled to a first quasi-type impurity. The first type well region is coupled to the first type well region and the first type well region is coupled to the first type well region and the last one. The stacked structure in the first type well region is located between the first and second regions. Yes, this bit is in the first, second, and first-type doped regions, and the second-type doped region includes the next first. Then a second — * dream — —βρ surface shape doping pattern is as follows: The impurity region and the second region are formed near the interface of the first type well region. In addition, the present invention proposes a series of steps: firstly forming a second type doped region at the first 'to form a second second type doped level. In addition, a layered structure is formed near the interface where the first type doped region is formed, and the above-mentioned region and the second and second type doped are simply explained: The above-mentioned objects, features, and advantages of the present invention can be more clearly and easily understood. The embodiment will be described in detail in conjunction with the attached drawings, but will not be illustrated in the figure: FIG. 1 is a cross-sectional view showing a conventional electrostatic discharge protection device. Figure 2 shows the wonderful structure of the MOS transistor structure formed on the SO I structure.
明實施例所 述之靜電 第3 A圖至第3 £圖係顯示根據本發 放電保護裝置之製造流程圖。 符號說明： 10、 22、32〜p型井區； 11、 2 3〜源極區； 1 2、2 4〜汲極區； 13、25、37〜接合墊； 14〜P型摻雜區； 15、26、35〜疊層結構； 2 0、3 0〜基底； 21、31〜絕緣層； 33、34〜N型摻雜區； 35A〜介電層； 35B〜導電層； SIGNAL〜外部信號； GND〜接地電位。 實施例： 第3;A圖至第3E圖係顯示根據本發明實施例所述之 放電保護裝置之製造流程圖。 參閱第3A圖，根據本發明實施例所述之靜電放電 裝置，具有一基底30，其表面覆蓋一絕緣層31。接下 參閱第3β圖，於上述絕緣層31上形成p型井區32，其深度 範園约為135ΠΙΠ至165nm之間。接著，參閱第扎圖，於 508786The static electricity according to the embodiment is shown in Figs. 3A to 3 £, which show the manufacturing flow of the discharge protection device according to the present invention. Explanation of symbols: 10, 22, 32 ~ p-type well region; 11, 2 3 ~ source region; 1 2, 2 4 ~ drain region; 13, 25, 37 ~ bonding pad; 14 ~ P type doped region; 15, 26, 35 ~ laminated structure; 20, 30 ~ substrate; 21, 31 ~ insulating layer; 33, 34 ~ N-type doped region; 35A ~ dielectric layer; 35B ~ conductive layer; SIGNAL ~ external signal ; GND ~ ground potential. Examples: Figures 3; A through 3E are flowcharts showing the manufacturing of a discharge protection device according to an embodiment of the present invention. Referring to FIG. 3A, the electrostatic discharge device according to the embodiment of the present invention has a substrate 30 whose surface is covered with an insulating layer 31. Next, referring to FIG. 3β, a p-type well region 32 is formed on the above-mentioned insulating layer 31, and its depth range is between about 135 and 165 nm. Next, refer to Zazatu on 508786
井區32中形成N型摻雜區33 (源極區）型摻雜區^ 極區）。接著，參閱第3D圖，於p型井區32中另外以^及 佈植法形成一P型摻雜區36，其位於p型井區32與^^型摻 區34之接面附近，範圍可介於p型井區32與N型摻雜區=之 接面以及P型井區32與N型摻雜區33之接面之間。在本眘A 例中，P型摻雜區36之摻雜離子為硼離子（B)，其離 = 雜劑 s 約為 lel3 atom/cm2 〜3el3 atom/cm2，而離子換 量約為35KeV〜40KeV。 #卞^雜月匕 最後，參閱第3E圖，於P型井區32之表面形成疊層結 構35，其位於N型摻雜區33&N型摻雜區34之間，疊層曰結° 35之侧壁形成侧壁間隔物35人。舉例而言，其可先&形曰成'"一 覆蓋該疊層結構3 5之絕緣層，例如以低壓化學氣相沈 程（LPCVD)形成之氧化層，接著再對該氧化層進行回蝕刻 步驟，以於疊層結構35之側壁形成側壁絕緣間隔物35A。 另外，N型摻雜區33&N型摻雜區34係分別耦接於接收 外部信號SIGNAL之接合墊37及接地電位gnd。 藉由P型摻雜區36之形成，能夠降低p型井區32與n型 摻雜區34之接面以及p型井區32與N型摻雜區33之接/面的崩 潰電壓，因此，當ESD事件出現於接合墊37時，此高電壓 f導致P型井區32與N型摻雜區34之接面電壓崩潰，由於先 刚所形成之P型摻雜區36，能夠降低p型井區32與n型摻雜 區34之接面以及p型井區32與N型摻雜區33之接面之崩潰電 壓，故較易電壓崩潰，因此得以提早導通，並將大量之 ESD電流引導至外部，藉以避免大量之ESD電流損壞内部電An N-type doped region 33 (source region) -type doped region (a polar region) is formed in the well region 32). Next, referring to FIG. 3D, a p-type doped region 36 is additionally formed in the p-type well region 32 by the ^ and implantation method, which is located near the interface between the p-type well region 32 and the ^ -type doped region 34. It may be between the interface between the p-type well region 32 and the N-type doped region = and the interface between the P-type well region 32 and the N-type doped region 33. In this example of A, the dopant ions of the P-type doped region 36 are boron ions (B), and the ion = dopant s is about lel3 atom / cm2 to 3el3 atom / cm2, and the ion exchange amount is about 35KeV ~ 40KeV. # 卞 ^ 杂 月 刀 Finally, referring to FIG. 3E, a layered structure 35 is formed on the surface of the P-type well region 32, which is located between the N-type doped region 33 and the N-type doped region 34. The side wall of 35 forms a side wall spacer of 35 persons. For example, it can be & shaped " an insulating layer covering the laminated structure 35, such as an oxide layer formed by low pressure chemical vapor deposition (LPCVD), and then the oxide layer In the etch-back step, a sidewall insulation spacer 35A is formed on a sidewall of the stacked structure 35. In addition, the N-type doped region 33 & the N-type doped region 34 are respectively coupled to the bonding pad 37 and the ground potential gnd which receive the external signal SIGNAL. By forming the P-type doped region 36, the breakdown voltage of the junction between the p-type well region 32 and the n-type doped region 34 and the junction / surface of the p-type well region 32 and the N-type doped region 33 can be reduced. When the ESD event occurs on the bonding pad 37, this high voltage f causes the junction voltage of the P-type well region 32 and the N-type doped region 34 to collapse. Due to the P-type doped region 36 formed just before, the p The breakdown voltage of the junction between the well region 32 and the n-type doped region 34 and the junction between the p-type well region 32 and the N-type doped region 33 makes the voltage breakdown easier, so it can be turned on earlier and a large amount of ESD will be turned on. The current is directed to the outside to avoid damaging the internal current by a large amount of ESD current
508786 五、發明說明（6) 路。 根據本發明實施例所揭露之制 :方法’能夠於具細結構之M0S電晶體=置 電保護裝[不會受限於s〇 體中：成-靜電放 統技術之問題。 °冓工間’有效的解決傳 本發明雖以較佳每 本發明的範圍，任何‘‘二:露如上，然其並非用以限定 精神和範圍内，當可^歧=技藝者，在不脫離本發明之 之 保護範圍當視後附之申；專利2與潤飾，因此本發 寻利圍所界定者為準。Θ 0503-6722TWF ； TSMC2001-0672 ； ROBERT.ptd508786 V. Description of Invention (6) Road. According to the system disclosed in the embodiments of the present invention, the method: can be used in a MOS transistor with a fine structure = an electric protection device [will not be limited to the body: the problem of the electrostatic-electrostatic system technology. ° Effective work. Although the present invention is preferred to the scope of the present invention, any `` two: exposed as above, but it is not intended to limit the spirit and scope. Departure from the scope of protection of the present invention shall be regarded as the attached application; patent 2 and retouching, so the definition of the profit margin of this hair shall prevail. Θ 0503-6722TWF; TSMC2001-0672; ROBERT.ptd