507377 72 78twf. doc/006 A7 B7 五、發明說明（/ ) 本發明是有關於一種半導體元件的製造方法，且特別 是有關於一種垂直型電晶體（Vertical Transistor)的製造方 法。 通常形成一電晶體之標準製程，包括在基底上沈積一 _氧化層與多晶矽層後，以微影蝕刻法圖案化閘氧化層與 $晶矽層以形成閘極，再於閘極兩側之基底中植入離子以 形成源極/汲極。 隨著半導體技術發展至高積集度，而需縮小元件之尺 寸。而當電晶體之通道縮小之後，除了會造成啓始電壓的 下降與閘極對MOS電晶體的控制發生問題之外，另一種 熱電子效應(Hot Electron Effects)的現象也會隨著通道長度 的縮短而影響MOS電晶體的操作。此外，當閘極之關鍵 尺寸低於0.13微米以下時，以習知之方法於定義閘極時， 將無法精確控制閘極之關鍵尺寸，且所形成之閘極亦較不 均勻。 因此本發明之目的爲提供一種電晶體的製造方法，& .降低元件運作時之電場強度，以削減熱電子效應。 經濟部智慧財產局員工消費合作钍印製 (請讀背面之注意事項再填寫本頁) 本發明之另一目的爲提供一種電晶體的製造方法，％ 使閘極之關鍵尺寸低於〇·13微米以下時，仍可容易的控制 其關鍵尺寸。 本發明之再一目的爲提供一種電晶體的製造方法，可 減少電晶體之面積，以有效提高積極度。 一種電晶體的製造方法，此方法係先提供一基底，_ 在基底中形成一溝渠，之後，在基底上形成--共形材料層 3507377 72 78twf. Doc / 006 A7 B7 V. Description of the Invention (/) The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a vertical transistor. A standard process for forming a transistor usually includes depositing an oxide layer and a polycrystalline silicon layer on a substrate, and then patterning the gate oxide layer and the polycrystalline silicon layer by lithography to form a gate electrode, and then forming a gate electrode on both sides of the gate electrode. Ions are implanted in the substrate to form a source / drain. With the development of semiconductor technology to a high degree of integration, the size of components needs to be reduced. When the transistor's channel shrinks, in addition to causing a drop in the starting voltage and the control of the MOS transistor by the gate, another phenomenon of Hot Electron Effects will also follow the channel length. Shortening affects the operation of the MOS transistor. In addition, when the critical size of the gate is below 0.13 micrometers, the critical size of the gate cannot be accurately controlled when the gate is defined by a conventional method, and the formed gate is also less uniform. Therefore, the object of the present invention is to provide a method for manufacturing a transistor, which reduces the electric field intensity during the operation of the device to reduce the thermionic effect. Printed by employees of the Intellectual Property Bureau of the Ministry of Economic Affairs for consumer cooperation (please read the notes on the back and then fill out this page) Another object of the present invention is to provide a method for manufacturing a transistor, so that the critical size of the gate is less than 0.13 Below micron, its critical dimensions can still be easily controlled. Another object of the present invention is to provide a method for manufacturing a transistor, which can reduce the area of the transistor to effectively increase the enthusiasm. A method for manufacturing a transistor. This method first provides a substrate. A trench is formed in the substrate, and then a conformal material layer is formed on the substrate. 3
經濟部智慧財產局員工消費合作社印製 507377 7278twf.doc/006 B7 五、發明說明（l) 後，去除部分共形材料層，以形成一材料層間隙壁，接著， 進行一熱製程，以使材料層間隙壁中之離子擴散至溝渠之 側壁中，而形成一通道，之後，去除材料層間隙壁後，在 基底上形成一共形氧化層，接著，去除部分共形氧化層， 以在溝渠側壁形成一閘氧化層，然後，進行一離子植入步 驟，以形成一源極/汲極區，接著，在基底上形成一多晶砂 層並塡滿該溝渠，圖案化多晶矽層以形成一閘極多晶砍 層，而完成電晶體之製作。 . 本發明所形成之垂直型電晶體，其通道中之離子濃度 由源極往汲極之方向逐漸變淡，因此，可降低通道中之電 場強度，以消減熱電子效應，而提高元件之可靠度。 本發明利用溝渠深度以形成閘極多晶矽層，可解決當 閘極關鍵尺寸低於0.13微米以下後，對於關閘關鍵尺寸不 易控制的問題，且較習知以微影定義閘極的方法更加簡單 且所形成之閘極較爲均句。 本發明之垂直型電晶體之面積較習知平面式電晶體 小，因此可有效提高積極度。 爲讓本發明之上述和其他目的、特徵和優點能更明顯 易懂，下文特與一較佳實施例，並配合所附圖示，做詳細 說明如下： 圖示之簡單說明： 第1A圖至第1G圖爲依照本發明一較佳實施例之電晶 體的製造流程剖面圖。 標記之簡單說明： 4 (請先閱讀背面之注意事項再填寫本頁) 訂---------線！ 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 278twf. doc/006Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 507377 7278twf.doc / 006 B7 V. Description of the invention (l) After removing part of the conformal material layer to form a material layer gap, then, a thermal process is performed to make Ions in the gap between the material layer diffuse into the sidewall of the trench to form a channel. After removing the gap between the material layer, a conformal oxide layer is formed on the substrate, and then a part of the conformal oxide layer is removed to form a channel on the sidewall of the trench. A gate oxide layer is formed, and then an ion implantation step is performed to form a source / drain region. Then, a polycrystalline sand layer is formed on the substrate and fills the trench, and the polycrystalline silicon layer is patterned to form a gate. The polycrystalline layer is cut to complete the production of the transistor. In the vertical transistor formed by the present invention, the ion concentration in the channel gradually fades from the source to the drain. Therefore, the strength of the electric field in the channel can be reduced to reduce the thermal electron effect and improve the reliability of the device. degree. The invention uses the trench depth to form a gate polycrystalline silicon layer, which can solve the problem that the key size of the gate is not easy to control when the key size of the gate is less than 0.13 microns, and is simpler than the conventional method of defining the gate by lithography And the gates formed are more even. The area of the vertical transistor of the present invention is smaller than that of the conventional planar transistor, and thus the enthusiasm can be effectively improved. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, the following specifically describes a preferred embodiment in conjunction with the accompanying drawings to make a detailed description as follows: A brief description of the drawings: FIG. 1A to FIG. 1G is a sectional view of a manufacturing process of a transistor according to a preferred embodiment of the present invention. Brief description of the mark: 4 (Please read the precautions on the back before filling this page) Order --------- line! This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) 278twf.doc / 006
、發明說明（多） 100 102 104 106 108 110 110a 111 : 基底 溝渠 共形材料層 間隙壁 通道 共形氧化層 :閘氧化層 離子植入步驟 112a/112b ·源極/级 114 :多晶矽層 極區 經濟部智慧財產局員工消費合作社印製 lUa :閘極多晶矽層 116 :光組層 118 :淺溝渠隔離區 120 :垂直型電晶體 實施例 ^ 第1A圖至第1G _， — 例之電晶體的製造流程1面、繪7^爲依照本發明一較佳實施 質例如爲P型矽基底。之/、基底10〇，其中基底1〇〇之材 形成溝渠102的方法例力後在基底1〇0中形成一·溝渠102， 上形成—共形材_ ln嗔微影咖法。接著在基底100 ,n^ rr?n iU4 ’其中共形材料層]〇4之材質例 砂玻璃(Bor〇silicate G丨咖），其厚度例如爲5〇〇埃至 1000 埃。 之後，請參照第1B圖，在形成共形材料層104之後， 本紙張尺度適用中國國家標準（CNS)A4規格（21〇 X 297公釐） (請先閱讀背面之注意事項再填寫本頁)Description of the invention (multiple) 100 102 104 106 108 110 110a 111: Conformal oxide layer on the substrate trench conformal material layer: conformal oxide layer on the gate channel: gate oxide layer ion implantation step 112a / 112b · source / level 114: polycrystalline silicon layer polar region Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 1Ua: Gate Polycrystalline Silicon Layer 116: Light Group Layer 118: Shallow Trench Isolation Area 120: Vertical Transistor Example ^ Figure 1A to 1G _, — Examples of the transistor The manufacturing process is shown in FIG. 1 and FIG. 7 is a preferred embodiment according to the present invention, such as a P-type silicon substrate. The method of forming the trench 102 in the substrate 100 is as follows. A trench 102 is formed in the substrate 100, and a conformal material is formed on the substrate. Next, on the substrate 100, n ^ rr? N iU4 ', a material example of the conformal material layer] 04, the thickness of the glass is about 500 angstroms to 1000 angstroms. After that, please refer to Figure 1B. After the conformal material layer 104 is formed, the paper size applies the Chinese National Standard (CNS) A4 specification (21 × 297 mm) (Please read the precautions on the back before filling this page)
507377 7278twf·doc/006 A7 ____B7 五、發明說明（年） 去除部分共形材料層104,以形成材料層間隙壁1〇6，而 去除部分共形材料層104之方法例如爲乾式蝕刻法。 接著，請參照第1C圖，進行一熱製程，其溫度例如 爲攝氏900度至攝氏11〇〇度，以使材料層間隙壁1〇6中之 離子擴散至溝渠102之側壁中，而形成通道ι〇8。其中材 料層間隙壁106中之離子例如爲硼離子。之後，去除材料 層間隙壁106，而去除材料層間隙壁1〇6之方法例如爲濕 式蝕刻法。接著，在基底1〇〇上形成一共形氧化層11〇。 然後’請參照第1D圖，去除部分共形氧化層11〇，以 在溝渠102之側壁形成閘氧化層110a，其中去除部分閘氧 化層110之方法例如爲乾式蝕刻法。接著，進行一離子植 入步驟111，以形成源極/汲極區l〇2a/l〇2b，其中所植入之 離子例如爲N型離子。 接著，請參照第1E圖，在基底100上形成一多晶矽 層114，並塡滿溝渠1〇2，之後在多晶矽層114上形成一圖 案化光阻層116，以形成閘極多晶矽層。 之後，請參照第1F圖，圖案化多晶矽層114，以形成 閘極多晶矽層114a。即完成以源極/汲極102a/102b、閘氧 化層110a、斜通道108、以及閘極多晶矽層114a所組成之 垂直型電晶體120。 利用溝渠深度以形成閘極多晶矽層114a之方法，可 解決當閘極關鍵尺寸低於0.13微米以下後，對於關閘關鍵 尺寸不易控制的問題，且較習知以微影定義閘極的方法更 加簡單且所形成之閘極較爲均勻。而此垂直型電晶體120 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注音？事項再填寫本頁) ·ΜΜ i I wa Μ· 一 δ，a 1 n 1 n ϋ ϋ 1 I ^ 經齊部智慧財產局員工消費合作社印製 507377 7278twf. doc/〇〇6 A7 B7 五 經濟部智慧財產局員工消費合作社印製 發明說明（t) --------------裝·-- (請先閱讀背面之注意事項再填寫本頁) 之通道108中之棚離子濃度由源極112a往汲極112b逐漸 變淡’因此’可降低通道108中之電場強度，以降低熱電 子效應，而提高元件之可靠度。再者，垂直型電晶體12〇 之面積較習知平面式電晶體小，因此可有效提高積極度。 之後，請參照第1G圖，可接著於此垂直式電晶體12〇 側邊形成淺溝渠隔離區118,其中形成淺溝渠隔離區n8 之方法例如先定義一溝渠，再於溝渠中塡入氧化層。 綜合以上所述，本發明具有下列優點·· 1. 本發明所形成之垂直型電晶體，其通道中之硼離子 濃度由源極往汲極逐漸變淡，因此，可降低通道中之電場 強度，以消減熱電子效應，而提高元件之可靠度。 2. 本發明利用溝渠深度以形成閘極多晶矽層，可解決 當閘極關鍵尺寸低於0.Π微米以下後，對於關閘關鍵尺寸 不易控制的問題，且較習知以微影定義閘極的方法更加簡 單且所形成之閘極較爲均勻。 線»_ 3·本發明之垂直型電晶體之面積較習知平面式電晶體 小，因此可有效提高積極度。 雖然本發明已以一較佳實施例揭露如上，然其並非用 以限定本發明，任何熟習此技藝者，在不脫離本發明之精 神和範圍內，當可作些許之更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者爲準。 7 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）507377 7278twf · doc / 006 A7 ____B7 V. Description of the Invention (year) The part of the conformal material layer 104 is removed to form a material layer gap 106, and the method of removing the part of the conformal material layer 104 is, for example, a dry etching method. Next, referring to FIG. 1C, a thermal process is performed, the temperature of which is, for example, 900 degrees Celsius to 1100 degrees Celsius, so that the ions in the material layer gap wall 106 can diffuse into the sidewall of the trench 102 to form a channel. ι〇8. The ions in the material layer spacer 106 are, for example, boron ions. Thereafter, the material layer spacers 106 are removed, and the method of removing the material layer spacers 106 is, for example, a wet etching method. Next, a conformal oxide layer 11 is formed on the substrate 100. Then, referring to FIG. 1D, a part of the conformal oxide layer 110 is removed to form a gate oxide layer 110a on the sidewall of the trench 102. A method of removing a part of the gate oxide layer 110 is, for example, a dry etching method. Next, an ion implantation step 111 is performed to form a source / drain region 102a / 102b, where the implanted ions are, for example, N-type ions. Next, referring to FIG. 1E, a polycrystalline silicon layer 114 is formed on the substrate 100, and the trenches 102 are filled. Then, a patterned photoresist layer 116 is formed on the polycrystalline silicon layer 114 to form a gate polycrystalline silicon layer. After that, referring to FIG. 1F, the polycrystalline silicon layer 114 is patterned to form a gate polycrystalline silicon layer 114a. That is, the vertical transistor 120 composed of the source / drain 102a / 102b, the gate oxide layer 110a, the inclined channel 108, and the gate polycrystalline silicon layer 114a is completed. The method of using the trench depth to form the gate polycrystalline silicon layer 114a can solve the problem that the key size of the gate is not easy to control when the key size of the gate is less than 0.13 microns, and is more than the conventional method of defining the gate by lithography. Simple and uniformly formed gates. And this vertical transistor 120 paper size is applicable to Chinese National Standard (CNS) A4 specification (210 X 297 mm) (Please read the note on the back? Matters before filling out this page) · Μ i i wa Μ · δ, a 1 n 1 n ϋ ϋ 1 I ^ Printed by the Ministry of Economic Affairs Intellectual Property Bureau employee consumer cooperative 507377 7278twf. doc / 〇〇6 A7 B7 Five Ministry of Economic Affairs Intellectual Property Bureau employee consumer cooperative printed invention description (t) --- ----------- Installation --- (Please read the precautions on the back before filling this page) The ion concentration in the channel 108 gradually fades from the source 112a to the drain 112b 'hence' The electric field strength in the channel 108 can be reduced to reduce the thermionic effect and improve the reliability of the device. Furthermore, the area of the vertical transistor 120 is smaller than that of the conventional planar transistor, so the enthusiasm can be effectively improved. Then, referring to FIG. 1G, a shallow trench isolation region 118 can be formed on the side of the vertical transistor 120. The method for forming the shallow trench isolation region n8 is, for example, defining a trench first, and then injecting an oxide layer into the trench. . To sum up, the present invention has the following advantages: 1. The boron ion concentration in the vertical transistor formed by the present invention gradually fades from the source to the drain, so the electric field strength in the channel can be reduced. To reduce the thermal electron effect and improve the reliability of the component. 2. The present invention uses the trench depth to form a gate polycrystalline silicon layer, which can solve the problem that the key size of the gate is not easy to control when the key size of the gate is less than 0.1 μm, and the gate is more commonly defined by lithography. The method is simpler and the gates formed are more uniform. Line »_ 3 · The vertical transistor of the present invention has a smaller area than the conventional planar transistor, and therefore can effectively increase the enthusiasm. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make some modifications and retouching without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application. 7 This paper size applies to China National Standard (CNS) A4 (210 X 297 mm)