TW506035B - Probe set and the manufacturing method thereof - Google Patents
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506035 A7 —-— B7_ 五、發明説明() 發明領域: ί請先閱讀背面之注意事項再填寫本頁) 本發明係有關於一種探針組(Probe Set)及其製造方 法’特別是有關於一種利用半導體製程技術來製造探針級 之方法。 發明背景: 在積體電路(Ic)的製造過程中,為使製程良率(Yield) 以及元件品質能夠達到最佳水準,因此在製程的不同階段 皆會進行產品測試。並同時利用精密的分析儀器在整個製 程中作各種不同有關品質管制的檢驗,藉以檢測積體電路 在製造過程中所發生的瑕疵,以及找出造成瑕疵的原因, 而確保產品品質符合標準,更進一步地提高生產良率。因 此’在積體電路的製造過程中,產品測試是確保積體電路 元件之產品良率,並建立有效的資料以提供工程分析的重 要步驟。 經濟部智慧財產局員工消費合作社印製 以測試所進行之時機來區分,積體電路產品之測試主 要有晶片針測(Chip Probe ; CP,又稱Wafer Sort)與成品 測試(F i n a 1 T e s t ’又稱p a c k a g e T e s t)兩個階段。晶片針測 在晶圓形式時執行,係在進行積體電路晶片封裝之前先區 分晶粒(Die)的良莠,以避免不必要的浪費。而成品測試 本紙張尺度適用中國國家標準(CNS)A4規格(210X297公釐) 五、發明説明( 貝J在積體電路曰曰片封裝之後執行,藉以確定在封裝過程之 後,此積體電路晶片仍符合規格。 更進一步來說’晶片針測步驟之主要功能係檢測出積 體電路在製造過程中所發生之瑕疲並找出原因,以確保產 品良率,並提供測試資料作為積體電路設計及製造分析之 用。晶片針測係對餐Μ θ圓、在 了 ®月B曰圓進行檢測,並藉以篩選晶圓上 晶粒之良品與不良品。因此,在測試記憶體晶圓時,可針 對尚可被修復之不良品予以雷射修補(Laser Repairing), 以南晶片良率。 由於’晶片針測係在積體電路晶片進行封裝之前 對晶片作電性功能上的測試,而先行過滤出電性 的晶片’以降低不良品對製造成本所造成的負擔。因^佳 晶片針㈣主要目的是測試晶圓巾每—顆晶粒 性以及線路的連接’檢查其是否為不良品,若為不^特 則點上一點墨水,作為識別之用。除此之外,另一個:、 是測試產品的良率,依良率的高低來判斷晶圓製造^ 是否有誤。產品良率高時,表示晶圓製造過程一切 若良品率過低,則表示在晶圓製造的過程中,有某些步驟 出現問題’必須儘快進行檢查。 進行積體電路晶片之測試時,先利用測試機發出待測 本紙張尺度適用中國國家標準(CNs)A4規格(21〇χ297公楚) (請先閲讀背面之注意事項再填寫本頁) 裝· 、rrv 經濟部智慧財產局員工消費合作社印製 506035 五、發明說明( 片所需的電性訊號,並透 上的探鉦收 過與測試機電性連接之測試頭 片接收測試施& #令 u傳輪至待測晶片上。當待測晶 』式機所傳來之電性 的電性句胁 ° ’u後’待測晶片會產生回應 訊铲值s 頌上的探針,而將回應的電性 訊唬傳至測試機。測試機 作屮客σ 很據所傳回之回應電性訊號, ®屋〇口電性測試結果的 銘,仏β j斷其中在測試機内的控制細 即,均是由針對此待測晶片 來控制 厅寫之測试程式(Test Program) 、$ '積體電路之測试非常依賴測試設備,而這些測 試設備大都由測試設備商所提供,且測試設備商提供之測 試機台以及配備皆相當昂責。而且,隨著積體電路產品生 op週期的縮紐’再加上積體電路功能的漸趨複雜化,都使 得積體電路測試設備的價格愈來愈昂責。 發明目的及概述: (請先閱讀背面之注意事項再填寫本頁) 裝· 、1T· 經濟部智慧財產局員工消費合作社印製 雲於積體電路晶片之測試機台過於昂貴,造成製程成 本的極大負擔。因此,本發明之主要目的為提供一種利用 半導體製程所製造之探針組,以取代測試設備供應商所提 供之昂貴測試探針。由於,製造本發明之探針組所需進行 之半導體製程’其花費遠低於向設備廠商購置探針的花 費。因此,可大幅降低製程成本。 506035506035 A7 —-— B7_ V. Description of the invention () Field of the invention: Please read the notes on the back before filling out this page) The present invention relates to a probe set and its manufacturing method, and particularly to A method for manufacturing probe level using semiconductor process technology. BACKGROUND OF THE INVENTION: In the manufacturing process of integrated circuit (Ic), in order to achieve the best yield and component quality, product testing is performed at different stages of the process. At the same time, we use precision analysis equipment to conduct various quality control inspections throughout the manufacturing process to detect defects in the integrated circuit during the manufacturing process and find out the causes of the defects, so as to ensure that the product quality meets the standards. Further improve production yield. Therefore, in the manufacturing process of integrated circuits, product testing is an important step to ensure the product yield of integrated circuit components and to establish effective data to provide engineering analysis. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs to distinguish the timing of the testing. The testing of integrated circuit products mainly includes Chip Probe (CP, also known as Wafer Sort) and finished product testing (F ina 1 T est 'Also known as package T est) two phases. Wafer probing is performed when the wafer is in the form, and the good and bad of the die are distinguished before the integrated circuit chip packaging, so as to avoid unnecessary waste. The paper size of the finished product test is in accordance with the Chinese National Standard (CNS) A4 specification (210X297 mm). 5. Description of the invention (Beijing is implemented after the integrated circuit chip is packaged to determine the integrated circuit chip after the packaging process. It still meets the specifications. Furthermore, the main function of the 'wafer pin test' step is to detect the defects in the integrated circuit during the manufacturing process and find out the reason to ensure the product yield and provide test data as the integrated circuit For design and manufacturing analysis. Wafer pin testing is used to test the M θ circle and the ® month B circle, and to screen the good and bad products on the wafer. Therefore, when testing the memory wafer Laser repairing can be performed on defective products that can still be repaired, to the south of the wafer yield. Because the 'wafer pin test is the electrical function test of the chip before the integrated circuit chip is packaged, and Filter out electrical wafers in advance to reduce the burden of defective products on manufacturing costs. Because the main purpose of a good wafer pin is to test the crystallinity of each wafer and the Then, check whether it is a defective product. If it is not, use a little ink for identification. In addition, the other one is: test the yield of the product, and judge the wafer based on the yield. Manufacturing ^ Is there a mistake. When the product yield is high, it means that everything in the wafer manufacturing process is too low, it means that there are problems in some steps during the wafer manufacturing process. 'It must be checked as soon as possible. When testing the chip, first use the tester to send out the paper to be tested. The paper size is applicable to Chinese National Standards (CNs) A4 specifications (21〇χ297 公 楚) (Please read the precautions on the back before filling this page). Printed by the Intellectual Property Bureau Employee Cooperative Cooperative 506035 V. Description of the invention (The electrical signals required for the tablet, and the test probe received the test head connected to the test electromechanical connection Acceptance test application &# 令 u 传 轮到On the chip under test. When the electrical test result from the "test crystal" type machine is used, the chip under test will generate a probe with a response value of s, and the response will be electrical. News passed to the test machine. Test machine The customer σ is very responsive to the electrical signals returned, ® the inscription of the electrical test results of the port 0, and the control details in the testing machine, which are all written by the control agency for the chip under test. The test program and test of integrated circuits are very dependent on test equipment, and most of these test equipment are provided by test equipment manufacturers, and the test equipment and equipment provided by test equipment manufacturers are quite responsible. Moreover, with the shrinkage of the integrated circuit product's op cycle, and the increasing complexity of integrated circuit functions, the price of integrated circuit test equipment has become more and more responsible. The purpose and summary of the invention: (Please Read the precautions on the back before filling this page.) Test equipment for printing cloud-on-chip ICs printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs and the Ministry of Economic Affairs is too expensive, resulting in a huge burden on process costs. Therefore, the main object of the present invention is to provide a probe set manufactured by using a semiconductor manufacturing process instead of an expensive test probe provided by a test equipment supplier. Because the semiconductor process' required to manufacture the probe set of the present invention costs much less than the cost of purchasing a probe from an equipment manufacturer. As a result, process costs can be significantly reduced. 506035
五、發明説明() 發明之另一目的為提供一種探針組之製造方法,其 (請先閱t謂背面之注意事項再填寫本頁) 係利用I導體製程在尺寸略大於待測晶片戶斤在之晶圓的基 材上’形成以探針組。由於,半導體製程技術已臻成熟, 且圖案尺寸已可控制在A等級。因此,可依需求來調整並 控制製程參數,而獲得精密度以及均句度皆相當高的探針 組。此外,由於本發明屬晶圓級尺寸製造,而可在一片基 材上,同時製造出大量的探針組。因此,可大幅降低製造 成本。 本發明的再一目的就是因為藉由本發明之探針組的製 造方法,可獲得晶圓級尺寸的探針組。由於,本發明之晶 圓級尺寸的探針組,其探針的位置係對應至晶圓上之每一 晶片的每一個銲墊。因此,在進行晶片測試時,僅需進行 一次對準,便可使探針對準晶圓上的全部晶片,並不須逐 對準不僅可降低晶片測試的繁靖,更可大幅縮減晶片 測試的時程。 經濟部智慧財產局員工消費合作社印製 根據以上所述之目的,本發明更提供了 一種探針組, 適用於探測一晶片,其中此探針組與一外部測試系統電性 連接,且此探針組至少,包括:一基材,其中此基材為絕緣 材料;一第一金屬層位於基材上;一第一氧化層位於第一 金屬層上,且此第一金屬層上至少包括複數個第一開口以 5ΐ紙張尺度適用中國國家標準(CNS)A4規格(210X297公楚) 506035 A7 B7 五、發明説明( (請先閲讀背面之注意事項再填寫本頁} 及複數個第三開口,而暴露出部分之第-金屬層;-第二 金屬層覆蓋部分之第一氧化層、全部的第一開口、以及這 些第開口所暴露之第一金屬層的部分上;一第三氧化層 覆蓋第二金屬層’且此第三氧化層至少包括複數個第二開 口以及複數個錐狀結構,其中這些第二開口暴露出部分之 第一金屬層;以及一第三金屬層覆蓋部分之第三氧化層、 全部的第二開口、全部的第三開口、以及上述的錐狀結構, 其中每一個錐狀結構與覆蓋在其上之第三氧化層則構成本 發明之探針組的一個探針。此外,為了獲得錐狀結構,因 此利用尚密度化學氣相沉積的技術形成第三氧化層。另一 方面,為了降低探針的耗損率,以及強化探針的結構,第 三金屬層之材料係選用堅硬的金屬或金屬化合物,例如鎢 (W)或氮化鈦(TiN)。 經濟部智慧財產局員工消費合作社印製 根據以上所述之其它目的,本發明更提供了一種探針 組之製造方法,至少包括:提供一基材,而此基材之材料 絕緣,其中此基材上已覆蓋有依序堆疊之一第一金屬層以 及一第一氧化層;形成複數個第一開口於上述之第一氧化 層中,並約暴露出部分之第一金屬層;形成一第二金屬層 覆蓋部分之第一氧化層、第一金屬層所暴露出之部分、以 及第一開口;進行一高密度電漿化學氣相沉積步驟,藉以 形成一第三氧化層覆蓋第二金屬層以及第一氧化層之另 一部分’並在第二金屬層上形成複數個錐狀結構;形成複 6 本紙張尺度適用中國國家標準(CNS)A4規格(210X297公釐) 506035 Α7 B7 五、發明説明( 數個第二開口於第三氧化層中,並約暴露出部分之 屬層,形成複數個第三開口於第一氧化層被第三氧 覆蓋之部分以及第三氧化層中,並約暴露出第一金 另一部分;以及形成一第三金屬層覆蓋部分之第 層、錐狀結構、第一金屬層所暴露出之部分、第二 所暴露出之部分、全部的第二開口、以及全部的 口,並填滿這些第二開口以及這些第三開口。其中 成第二氧化層之步驟前,更至少包括先形成一第二 覆蓋在第二金屬層上,再定義第二氧化層而在第二 上形成複數個凸塊◎而且,第三氧化層更包括覆蓋 凸塊’而使得上述之錐狀結構在這些凸塊上形成。 圖式簡單說明: $二金 化層所 屬層之 三氣化 金屬層 $三開 ’在形 氧化層 金屬層 &這4b C請先閱讀背面之注意事项、再填、寫本頁> 經濟部智慧財產局員工消費合作社印製 本發明的較佳實施例將於往後之說明文字中辅以下 圖形做更詳細的闡述,其中: 第1圖至第ό圖為繪示本發明之一較佳實施例之探 組的製造剖面流程圖;以及 衣針 第7圖為繪示運用本發明之一較佳實施例之探針組 行晶片測試的示意圖。 " 圖號對照說明: 本紙張尺度適用中國國家標準(CNS)A4規格(21〇χ297公^ 506035 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明説明() 100 基材 102 第一金屬層 104 第一氧化層 106 第一開口 108 第二金屬層 110 凸塊 112 第三氧化層 114 錐狀結構 116 第二開口 118 第三開口 120 第三金屬層 121 接觸區 122 探針 124 探針組 200 待測晶圓 202 晶片 204 銲塾(Bonding Pad) 206 保護層(Passivation Layer) 發明詳細說明: 本發明揭露一種探針組及其製造方法,其係採用半導 體技術製造而得。利用成熟的半導體技術,可在相當低成 本下,大量製作出具有極佳精密度以及均勻度的探針組。 為了使本發明之敘述更加詳盡與完備,可參照下列插述並 配合第1圖至第7圖之圖示。 為了降低購置積體電路晶片之測試設備的成本,本發 明運用半導體製程技術來製造測試用之探針組。請參照第! 圖至第6圖,其係繪示本發明之一較佳實施例之探針組的 製造剖面流程圖。首先,在尺寸略大於待測晶圓2〇〇(見第 8 本紙張尺度適用中國國家標準(CNS)A4規格(210X297公釐) ...........鲁裝.........訂---1..... (請先閲讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 506035 A7 __ B7 五、發明説明() 7圖)之絕緣的基材1 〇〇(僅繪示其中的一小部分)上覆蓋一 層第一金屬層102,其中基材1〇〇之材料可例如為氧化石夕, 且第一金屬層102之材料可例如鋁(A1)、銅(Cu)、或鋁銅合 金等。再以例如熱氧化法(Thermal Oxidation)或化學氣相沉 積法(Chemical Vapor Deposition ; CVD)等方式,在第一金 <屬層102上覆蓋第一氧化層1〇4。其中,第一金屬層ι〇2 以及第一氧化層丨〇4之厚度皆可隨製程需求而變化。接 著’以例如微影以及濕式蝕刻(Wet Etching)或乾式蝕刻(Dry Etching)的方式定義第一氧化層1〇4,直至約暴露出部分之 第一金屬層102,並在第一氧化層104中形成複數個第一 開口 1 06,如第1圖所示之結構。 當第一開口 106設置完成後,形成一層第二金屬層1〇8 覆蓋第一氧化、層104、第一開口 106、以及第一氧化層1〇4 所暴露的部分,其中第二金屬層1〇8的厚度相當厚,約為3 微米至約5微米之間’且第二金·屬層1〇8之材料可配合第 一金屬層102之材料而為鋁、銅、或鋁銅合金等。再利用 例如微影以及蝕刻製程對第二金屬層丨〇8進行定義,而將 部分之第二金屬層1〇8去除,並暴露出部分之第一氧化層 104,但保留第一開口 106上的部分。由於,第二金屬層 108的厚度較厚,因此蝕刻過程中所產生之高分子(p〇iyiner) 聚合物會附著在第二金屬層1 〇 8的側壁上,而使得經餘刻 後之第二金屬層1 08具有傾斜的側壁,如第2圖所示。 9 本紙張尺度適用中國國家標準(CNS)A4規格(210X297公董) ...........·裝——訂......... (請先閲讀背面之注意事項再填寫本頁) 506035 A7 _______ B7 五、發明説明() ............-_裝: (請先閲讀背面之注意事項再填寫本頁) 請參照第3圖,在完成第二金屬層丨〇8之圖案化後, 先形成第二氧化層(僅繪示凸塊11〇的部分)覆蓋第二金屬 層1 〇8以及第一氧化層! 〇4。再利用例如微影以及蝕刻製 程疋義第二氧化層,而去除第一氧化層1〇4上之第二氧化 層以及第二金屬層1〇8上之部分第二氧化層,且暴露出第 一氧化層104以及部分之第二金屬層108,並在第二金屬 層108上形成複數個凸塊1 1〇。 接著,利用高密度電漿化學氣相沉積(High Density Plasma CVD ; HDP-CVD)的技術,進行第三氧化層112的 沉積,而在第二金屬層108以及第一氧化層104上,形成 與凸塊110組合構成之第三氧化層112。其中,藉由調控 高密度電漿化學氣相沉積步驟之濺擊率/沉積率 (Sputtering Rate/Deposition Rate ; S/D)的比值,來控制第 三氧化層112的外型,而在原先的凸塊11〇區域上形成錐 狀結構1 1 4,如第4圖所示之結構。 經濟部智慧財產局員工消費合作社印製 在錐狀結構1 1 4完成後,利用例如微影以及蝕刻製程 定義第二金屬層108上的第三氧化層112 ’而在第二金屬 層1 08上形成複數個第二開口 1 1 6,並約暴露出部分之第 二金屬層108。在定義第二金屬層108上之第三氧化層 112的同時,亦對距第二金屬層108 一預設距離的第一金V. Description of the invention () Another object of the invention is to provide a method for manufacturing a probe set, which (please read the precautions on the back of t before filling out this page) is using the I-conductor process in a size slightly larger than the chip to be tested. A probe set is formed on the substrate of the wafer. Because the semiconductor process technology has matured, and the pattern size can be controlled at A level. Therefore, the process parameters can be adjusted and controlled according to requirements, and a probe set with high precision and average sentence degree can be obtained. In addition, since the present invention is a wafer-level manufacturing, a large number of probe sets can be manufactured simultaneously on a single substrate. As a result, manufacturing costs can be significantly reduced. Another object of the present invention is to obtain a wafer-level probe set by the method of manufacturing the probe set of the present invention. Because of the round-sized probe set of the present invention, the position of the probe corresponds to each pad of each wafer on the wafer. Therefore, when performing wafer testing, only one alignment is required to align the probes to all the wafers on the wafer, and the need to align them one by one can not only reduce the complexity of wafer testing, but also greatly reduce the wafer testing time. Time schedule. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs According to the above-mentioned purpose, the present invention further provides a probe set suitable for detecting a chip, wherein the probe set is electrically connected to an external test system, and the detection The needle group includes at least: a substrate, wherein the substrate is an insulating material; a first metal layer is located on the substrate; a first oxide layer is located on the first metal layer, and the first metal layer includes at least a plurality of The first opening is applied to the Chinese National Standard (CNS) A4 specification (210X297) on a 5ΐ paper scale. 506035 A7 B7 V. Description of the invention ((Please read the precautions on the back before filling this page) and multiple third openings. And a portion of the first metal layer is exposed; the second metal layer covers a portion of the first oxide layer, all of the first openings, and a portion of the first metal layer exposed by the first openings; a third oxide layer covers The second metal layer 'and the third oxide layer include at least a plurality of second openings and a plurality of cone-shaped structures, wherein the second openings expose a part of the first metal layer; and a third metal layer The third oxide layer on the cover portion, all the second openings, all the third openings, and the above-mentioned tapered structure, wherein each of the tapered structure and the third oxide layer covering it constitute the probe of the present invention. In addition, in order to obtain a cone-shaped structure, a third oxide layer is formed using a high density chemical vapor deposition technique. On the other hand, in order to reduce the loss rate of the probe and strengthen the structure of the probe, the first The material of the tri-metal layer is a hard metal or metal compound, such as tungsten (W) or titanium nitride (TiN). Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. According to the other purposes described above, the present invention further provides A method for manufacturing a probe set includes at least: providing a substrate and insulating the material of the substrate, wherein the substrate has been covered with a first metal layer and a first oxide layer sequentially stacked; forming a plurality of A first opening is formed in the first oxide layer, and a part of the first metal layer is exposed; a second metal layer is formed to cover the first oxide layer, and the first metal layer is exposed. Part and the first opening; performing a high-density plasma chemical vapor deposition step to form a third oxide layer covering the second metal layer and another part of the first oxide layer 'and forming the second metal layer Multiple cone-shaped structures; forming multiple 6 paper sizes applicable to Chinese National Standard (CNS) A4 specifications (210X297 mm) 506035 A7 B7 V. Description of the invention (Several second openings in the third oxide layer and approximately exposed Part of the layer, forming a plurality of third openings in the portion of the first oxide layer covered by the third oxygen and the third oxide layer, and approximately exposing another portion of the first gold; and forming a portion of the third metal layer covering portion The first layer, the cone-shaped structure, the exposed portion of the first metal layer, the second exposed portion, all the second openings, and all the openings, and fill the second openings and the third openings. The step of forming the second oxide layer includes at least forming a second covering layer on the second metal layer, and then defining the second oxide layer to form a plurality of bumps on the second layer. Furthermore, the third oxide layer is more It includes covering bumps' so that the aforementioned cone-shaped structure is formed on these bumps. Schematic description: $ 3 metallization layer belongs to the three gasification metal layer $ 3 open 'in the shape of the oxide layer metal layer & the 4b C Please read the precautions on the back, then fill in, write this page > Economy The preferred embodiment of the present invention printed by the Ministry of Intellectual Property Bureau's Consumer Cooperatives will be explained in more detail in the following explanatory text, in which: Figures 1 to 6 are drawings showing one of the present inventions. A cross-sectional manufacturing flow chart of the probe set of the preferred embodiment; and FIG. 7 is a schematic diagram showing a wafer test using a probe set of a preferred embodiment of the present invention. " Comparison of drawing numbers: This paper size is applicable to China National Standard (CNS) A4 specifications (21〇χ297 公 ^ 506035 A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention (100) 102 First Metal layer 104 First oxide layer 106 First opening 108 Second metal layer 110 Bump 112 Third oxide layer 114 Conical structure 116 Second opening 118 Third opening 120 Third metal layer 121 Contact area 122 Probe 124 Probe Group 200 Wafer to be tested 202 Wafer 204 Bonding Pad 206 Passivation Layer Detailed description of the invention: The present invention discloses a probe set and a manufacturing method thereof, which are manufactured by using semiconductor technology. Semiconductor technology can produce a large number of probe sets with excellent precision and uniformity at a relatively low cost. In order to make the description of the present invention more detailed and complete, please refer to the following inserts and cooperate with Figures 1 to 7 In order to reduce the cost of purchasing test equipment for integrated circuit wafers, the present invention uses semiconductor process technology to manufacture test probes. Please refer to Figures! To Figure 6, which are flowcharts showing the manufacturing cross-section of a probe set according to a preferred embodiment of the present invention. First, the size is slightly larger than the wafer to be tested by 200 (see Figure 8). This paper size is applicable to China National Standard (CNS) A4 specification (210X297 mm) ........... Lu installation ......... Order --- 1 ..... ( Please read the notes on the back before filling in this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 506035 A7 __ B7 V. Description of the invention () 7) Insulating base material 1 (only one of them is shown) A small portion) is covered with a first metal layer 102, wherein the material of the substrate 100 may be, for example, stone oxide, and the material of the first metal layer 102 may be, for example, aluminum (A1), copper (Cu), or aluminum copper Alloy, etc. Then, the first metal layer 104 is covered with a first oxide layer 104 by, for example, a thermal oxidation method (Chemical Vapor Deposition; CVD), or the like. Among them, The thickness of the first metal layer ι02 and the first oxide layer 〇04 can be changed according to process requirements. Then, for example, lithography and wet etching (Wet Etchi ng) or Dry Etching to define the first oxide layer 104 until a portion of the first metal layer 102 is exposed, and a plurality of first openings 106 are formed in the first oxide layer 104, such as The structure shown in Figure 1. After the first opening 106 is set, a second metal layer 108 is formed to cover the first oxide, the layer 104, the first opening 106, and the first oxide layer 104. In part, the thickness of the second metal layer 108 is quite thick, between about 3 micrometers and about 5 micrometers, and the material of the second metallographic layer 108 can be matched with the material of the first metal layer 102 to be aluminum. , Copper, or aluminum-copper alloy. Then, the second metal layer 008 is defined by, for example, lithography and etching processes, and a part of the second metal layer 108 is removed, and a part of the first oxide layer 104 is exposed, but the first opening 106 remains. part. Because the thickness of the second metal layer 108 is relatively thick, the polymer (poiyiner) polymer generated during the etching process will adhere to the side wall of the second metal layer 108, so that the first The two metal layers 108 have inclined sidewalls, as shown in FIG. 2. 9 This paper size is applicable to China National Standard (CNS) A4 specification (210X297 public director) ........... · installation-order ... (Please read the note on the back first Please fill in this page again) 506035 A7 _______ B7 V. Description of the invention () ............-_ Pack: (Please read the precautions on the back before filling this page) Please refer to Figure 3 After completing the patterning of the second metal layer 丨 〇8, first form a second oxide layer (only the portion of the bump 110 is shown) to cover the second metal layer 108 and the first oxide layer! 〇4. The second oxide layer is defined by, for example, lithography and etching processes, to remove the second oxide layer on the first oxide layer 104 and a part of the second oxide layer on the second metal layer 108, and expose the first oxide layer An oxide layer 104 and a portion of the second metal layer 108 are formed on the second metal layer 108. Next, a high-density plasma chemical vapor deposition (High Density Plasma CVD; HDP-CVD) technique is used to deposit a third oxide layer 112, and on the second metal layer 108 and the first oxide layer 104, an The third oxide layer 112 is formed by combining the bumps 110. Among them, the shape of the third oxide layer 112 is controlled by adjusting the sputtering rate / deposition rate (S / D) ratio of the high-density plasma chemical vapor deposition step. A cone-shaped structure 1 1 4 is formed on the region of the bump 11, as shown in FIG. 4. After the consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs has printed the cone-shaped structure 1 1 4, the third oxide layer 112 ′ on the second metal layer 108 is defined by the lithography and etching processes, and the second metal layer 108 is formed. A plurality of second openings 1 1 6 are formed, and a portion of the second metal layer 108 is exposed. While defining the third oxide layer 112 on the second metal layer 108, the first gold layer at a predetermined distance from the second metal layer 108 is also defined.
本紙張尺度適用中國國家標準(CNS)A4規格(210X297公愛) I 506035This paper size applies to China National Standard (CNS) A4 (210X297 public love) I 506035
五、發明説明( 經濟部智慧財產局員工消費合作社印製 屬層102上之第三氧化層丨 、一 與第一氧化層104進行定 義’而在第一金屬層丨 .H ^ 上形成複數個第三開口 118,並 約暴露出部分之第一会屈 ,,.. 屬層102,而形成如第5圖所示之 結構。 然後’形成第三金屬層12〇V. Description of the Invention (The third oxide layer on the printed layer 102 of the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs, and the definition of the first oxide layer 104 with the first oxide layer 104, and a plurality of layers are formed on the first metal layer. The third opening 118 exposes a portion of the first flexion,... Of the first layer 102, and forms a structure as shown in FIG. 5. Then, a third metal layer 12 is formed.
Ba 项’ 120覆蓋第三氧化層112、第 一開口 116所暴露之第二金屬 金屬層!〇8、以及第三開口 118 所暴路之第一金屬層1〇2, 亚異滿第二開口 1 1 6與第三開 口 118。其中,第三金屬屉 層2〇之材料可例如為鎢以及氮 化欽等較為堅硬的金屬或金屬 觖纟 屬化《物,以利測試,強化錐 製㈣第三金屬降二:率^ a _ 、 層120進仃疋義,而去除部分之第三金屬 層120,並暴露出部分笛一 丨刀之第二氧化層1 12。但保留位於錐 狀、,、口構114、第二開口 肉 開11 6内、以及第三開口 1 1 8内之第 三金屬層120,而裉占‘赞(一 ^ 形成如第6圖所示之結構。其中,錐 結構m以及位於其上之第三金屬層12〇則構成本發明 之探針組124的探針122,且位於第三開〇 ιΐ8 = 金屬層120則形成接觸區12卜製程進行至此,已完成; 本發明之探針組124。 1 本發明之探針組124的探針122的數量並沒有特 限定’可依製程需求而予以變化,但至少需有一個杜 122。而構成探針組124之各個材料層的厚度以 本紙張尺躺财目目家標準(CNS)A4規格(21〇χ9^ .........-,·裝---:!訂.........Φ (請先閲讀背面之注意事項再填、寫本頁) 506035 A7Item Ba '120 covers the third oxide layer 112 and the second metal metal layer exposed by the first opening 116! 〇8, and the first metal layer 102 of the third opening 118, the second opening 1 16 and the third opening 118. Among them, the material of the third metal drawer layer 20 may be, for example, tungsten and nitride, such as harder metals or metal compounds, to facilitate testing and strengthen the cone. The third metal is reduced by two: rate ^ a The layer 120 is defined, and a part of the third metal layer 120 is removed, and a part of the second oxide layer 112 is exposed. However, the third metal layer 120, which is located in the cone shape, the mouth structure 114, the second opening body 116, and the third opening 1 18, is retained, and the Zhan (Za) is formed as shown in FIG. 6 The structure shown in the figure. Among them, the cone structure m and the third metal layer 120 located thereon constitute the probe 122 of the probe set 124 of the present invention, and the third area θ 8 = metal layer 120 forms the contact area 12 The manufacturing process has been completed so far; the probe set 124 of the present invention is not limited. 1 The number of probes 122 of the probe set 124 of the present invention is not limited. It can be changed according to process requirements, but at least one Du 122 The thickness of each material layer constituting the probe set 124 is in accordance with this paper rule (CNS) A4 specification (21〇χ9 ^ .........-, · install --- :: ! Order ......... Φ (Please read the notes on the back before filling and writing this page) 506035 A7
五、發明説明() (請先閲讀背面之注意事項再填寫本頁) 屬層1 0 8之尺寸可根據待測晶圓2 〇 〇之結構進行變化,僅 須在進行晶片202之測試時,使探針組124之探針122 能順利接觸到晶片202之銲墊204即可。 經濟部智慧財產局員工消費合作社印製 利用本發明之探針組124進行待測晶圓2〇〇之晶片 的測試時,先將探針組124之接觸區121與外部測試系統 (未、’曰示)電性連接0由於,晶片202之銲塾204上之保護 層206已被去除。因此,此時可直接將探針組124之探針 122與晶片202之銲墊204接觸。其中,由於本發明之探 針組1 24可具有不只一個探針i 22 ,因此可確保探針j 22 能接觸到晶片202之銲墊204。當探針組124之探針122 與晶片202之銲墊204接觸後,外部測試系統發出待測晶 圓200上之晶片202所需的電性訊號,並透過與外部測試 系統電性連接之探針組1 2 4上的接觸區1 2 1、第一金屬層 102、第二金屬層108、以及探針122將電性訊號傳輸至 晶片202的銲墊204上。當晶片202接收外部測試系統所 傳來之電性訊號後,晶片202會產生回應的電性訊號,再 次透過探針組1 24上的探針1 22,而將回應的電性訊號傳 至外部測試系統。外部測試系統就根據回應的電性訊號, 判斷出晶片202的電性測試結果。 此外,由於本發明之探針組1 24可在尺寸略大於待測 晶圓200的基材1〇〇上製作。因此,在製作探針組124時, 12 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐)V. Description of the invention () (Please read the precautions on the back before filling this page) The size of the metal layer 1 0 8 can be changed according to the structure of the wafer 200 to be tested, only when testing the wafer 202, The probes 122 of the probe set 124 can smoothly contact the pads 204 of the wafer 202. When the consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs prints and uses the probe set 124 of the present invention to test a 200-wafer wafer, the contact area 121 of the probe set 124 and an external test system (not, ' (Shown) The electrical connection 0 is because the protective layer 206 on the solder pad 204 of the chip 202 has been removed. Therefore, at this time, the probe 122 of the probe set 124 can be directly contacted with the pad 204 of the wafer 202. Among them, since the probe set 1 24 of the present invention can have more than one probe i 22, it can be ensured that the probe j 22 can contact the pad 204 of the wafer 202. After the probe 122 of the probe set 124 contacts the solder pad 204 of the wafer 202, the external test system sends out the electrical signals required by the wafer 202 on the wafer 200 to be tested, and the probe is electrically connected to the external test system The contact area 1 2 1 on the pin group 1 2 4, the first metal layer 102, the second metal layer 108, and the probe 122 transmit electrical signals to the bonding pads 204 of the chip 202. When the chip 202 receives the electrical signal from the external test system, the chip 202 will generate a response electrical signal, and again pass the probe 1 22 on the probe set 1 24 to transmit the response electrical signal to the outside. Test the system. The external test system judges the electrical test result of the chip 202 according to the electrical signal in response. In addition, since the probe set 124 of the present invention can be fabricated on a substrate 100 whose size is slightly larger than the wafer 200 to be measured. Therefore, when making the probe set 124, 12 paper sizes are applicable to China National Standard (CNS) A4 (210 X 297 mm)
^06035 A7 五、發明説明() 可將探針組124之探針122的位置對應至待測晶圓2〇〇上 之每一晶片202的每一個銲墊2〇4的位置。如此一來,便 可進行晶圓級尺寸的測試,而將整個基材1〇〇上的每一個 探針組124之探針122與待測晶圓200上之每一晶片2〇2 的每一個銲墊204接觸,再依測試製程的設計進行檢測。 因此,可避免逐一對準的麻煩,相當方便、省時。 本發明之優點就是在提供一種運用半導體製程來自行 製造探針組,藉以省下購置測試探針的昂貴費用。由於, 製造本發明之探針組所需進行之半導體製程,其花費遠低 於購置探針的費用ν因此,可大幅降低積體電路的測試成 本。 本發明之另一優點就是在提供一種探針組之製造方 法’其可利用半導體製程在尺寸略大於待測晶圓的基材 上’形成眾多探針組。藉由成熟的半導體製程技術,可將 圖案尺寸控制在Α等級,並可依需求來調整並控制製程參 數’因此可製造出精密度以及均勻度皆相當高的探針組。 此外’由於本發明屬晶圓級尺寸製造,而可在一片基材上, 同時製造出大量的探針組。因此,可大幅降低製造成本。 藉由本發明之探針組的製造方法,可獲得晶圓級尺寸 的探針組。由於,本發明之晶圓級尺寸的探針組,可設計 13 本紙張尺度適用中國國家標準(CNS)A4規格(210X297公釐) ........:__裝_--------訂.........Φ (請先閲1^謂背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明説明() 探針的位置使其對應至待測晶圓 0 ^ . 舳上 吗工〈母一晶片的每一個錄 墊。在進行晶片測試時,僅需進行一 1 -人對準,便可使禊4, 對準待測晶圓上的全部晶片,並 |曰日乃亚不須逐一對準。因此,不 僅可降低晶片測試的繁瑣 — π I貝更可大幅縮減晶片測試的時 程。 叮 如熟悉此技術之人員所瞭解的,以上所述僅為本發明 之較佳實施例而已,並“以限定本發明之t請專利範 圍;凡其它未脫離本發明所揭示之精神下所完成之等效改 變或修飾,均應包含在下述之申請專利範圍内。 I----41^ 裝-, (請先閲讀背面之注意事項再填寫本頁) 訂 經濟部智慧財產局員工消費合作社印製 Μ 本紙張尺度適用中國國家標準(CNS)A4規格(210X297公釐)^ 06035 A7 V. Description of the invention () The position of the probe 122 of the probe set 124 can be corresponding to the position of each pad 202 of each wafer 202 on the wafer to be tested 200. In this way, a wafer-level size test can be performed, and each of the probes 122 of each probe group 124 on the entire substrate 100 and each of the wafers 200 on the wafer 200 to be tested A pad 204 is in contact, and then tested according to the design of the test process. Therefore, the trouble of one-by-one alignment can be avoided, which is quite convenient and time-saving. The advantage of the present invention is to provide a self-produced probe set using a semiconductor manufacturing process, thereby saving the expensive cost of purchasing test probes. Because the semiconductor process required to manufacture the probe set of the present invention costs much less than the cost of purchasing a probe, ν, the test cost of the integrated circuit can be greatly reduced. Another advantage of the present invention is to provide a method for manufacturing a probe set, which can use a semiconductor process to form a plurality of probe sets on a substrate slightly larger than a wafer to be measured. With mature semiconductor process technology, the pattern size can be controlled at grade A, and the process parameters can be adjusted and controlled according to demand ', so that a probe set with high precision and uniformity can be manufactured. In addition, since the present invention is a wafer-level manufacturing, a large number of probe sets can be manufactured on one substrate at the same time. Therefore, manufacturing costs can be significantly reduced. By the method for manufacturing a probe set of the present invention, a wafer-level probe set can be obtained. Because of the wafer-level probe set of the present invention, 13 paper sizes can be designed to comply with the Chinese National Standard (CNS) A4 specification (210X297 mm) .....: __ 装 _--- ----- Order ......... Φ (Please read the precautions on the back of 1 ^ before filling out this page) Printed by A7 B7, Consumer Cooperative of Intellectual Property Bureau, Ministry of Economic Affairs V. Description of Invention () The position of the probe corresponds to 0 ^. Of the wafer to be tested. 〈Each of the recording pads of the mother-wafer. When performing wafer testing, only 1-person alignment is required, so that 禊 4 can be aligned to all the wafers on the wafer under test, and it is not necessary to align them one by one. As a result, not only can the tediousness of wafer testing be reduced — π I can significantly reduce the time required for wafer testing. As understood by those familiar with this technology, the above is only a preferred embodiment of the present invention, and "to limit the patent scope of the present invention; all others can be completed without departing from the spirit disclosed by the present invention. Equivalent changes or modifications should be included in the scope of patent application below. I ---- 41 ^ 装-, (Please read the precautions on the back before filling this page) Order the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs Printed M This paper is sized for China National Standard (CNS) A4 (210X297 mm)
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TW90132949A TW506035B (en) | 2001-12-28 | 2001-12-28 | Probe set and the manufacturing method thereof |
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TW90132949A TW506035B (en) | 2001-12-28 | 2001-12-28 | Probe set and the manufacturing method thereof |
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