TW505995B - A method to form transistors with multiple threshold voltages (VT) using a combination of different work function gate materials - Google Patents

A method to form transistors with multiple threshold voltages (VT) using a combination of different work function gate materials Download PDF

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TW505995B
TW505995B TW090111538A TW90111538A TW505995B TW 505995 B TW505995 B TW 505995B TW 090111538 A TW090111538 A TW 090111538A TW 90111538 A TW90111538 A TW 90111538A TW 505995 B TW505995 B TW 505995B
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gate electrode
group
scribed
angstroms thick
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TW090111538A
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Ravi Sundaresan
Yang Pan
Yong Meng James Lee
Ying Keung Leung
Yelehanka Ramachandram Pradeep
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Chartered Semiconductor Mfg
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0135—Manufacturing their gate conductors
    • H10D84/014—Manufacturing their gate conductors the gate conductors having different materials or different implants
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
    • H10D30/0225—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate using an initial gate mask complementary to the prospective gate location, e.g. using dummy source and drain electrodes
    • H10D64/01322—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/665—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of elemental metal contacting the insulator, e.g. tungsten or molybdenum
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/667—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/671—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor having lateral variation in doping or structure
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe

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  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Description

505995 五、發明說明（1) 【發明之領域 本發明一般而言係有關於形成積體電路電晶體，並且 更特別地是有關一種用於形成控制短通道效應之積體電路 電晶體閘極的方法。 【發明之背景】 深次微米電晶體需要諸如口袋植入（parket implant )等特別的植入，以便控制短通道效應。 美國專利第5,960,270號（Misra等人）說明一種具有
氮化矽間隔物2 3之閘極以及一種諸如金屬之肝J閘極。 天國專利第5,447,874號（Grivna等人）說明一種雙 金屬閘極。 美國專利第5,776,823號（Agnelio等人）說明一 層（WF )閘極 國專利第5，9 6 6，5 9 7號（W r i g h t )以及美國專利| 5,965,911號（j〇〇等人）說明雙材料閘極。 美國專利第6, 05 1,470號（An等人）說明一種雙閘右 電極)其具有一個側邊導電部分、一個中心導電部分， 及形攻於該側邊導電部分與中心導電部分之間的介電質 滿物= 、 【發明之概要】
第8頁 505995 五、發明說明（2) 本發明 閘極材料組 壓之閘極的 其他的 現已發 成。特別地 板部分以及 被形成於該 之部分的經 弟一功函數 形成於該經 鄰接。該閘 成。該内間 其他目 具有暴 個上覆 邊緣上 方。該 > 一個矣 餘部分 一功函 形成閘 藉由使用相異功函數 以製造具肴多重閥電 之另一目的在於提 合（而避免特殊植 方法。 目的將表示如下。 現本發明的上述及 是，一半導體基板 經刻劃層開口的一 經刻劃層所暴露之 暴露基板部分的上 的WF1材料所組成< 刻劃薄層開口之其 電極由一個具有第 隔物與該閘電極將 的可以下列方法完 路出主動區中之該基 經刻劃層。内間隔物 的该經刻劃層開口中 内間隔物由一個具有 1平坦化的閘電極被 中’並與該内間隔物 數的WF2材料所組 電極。 【圖號對照說明】 10 半導體基板 12 淺溝渠隔離（STI ) 14 主動區 16 犧牲氧化層 18 經刻劃層 20 矽基板部分 22 閘極氧化層 24 内間隔物 26 氮化層開口 第9頁 505995 五、發明說明（3) 2 7 暴露邊緣 28肝2閘電極體 3 0 閘電極 【較佳貫施例之細節說明】 習知ϊ ί t別地說明’否則所有的結肖、薄層等皆可藉由 S技*中所熟知的傳統方法被形成或完成。 初始結構 井^^第1圖所示’初始半導體基板1Q可為石夕基板。 1定用开與p井遮罩進行。 3渠隔離（STI)12被形成於石夕基板 主動區1 4於其間。 里η/取 犧=被形成於碎基板10與淺溝渠隔離Κ上。 犧在虱化層16偏好約100至30〇埃的厚度。 經刻劃層的形成 如第2圖所示，犧牲氧化層16被移除。 經刻劃層18被形成於矽基板1〇與 · :約_至3000埃的厚度。經刻劃層以偏： 二戈： 化石夕所組成，ϋ為偏好由氮切所組成。由減石夕或亂 經刻劃層1 8具有暴露出主動區丨4 的開口26。經刻劃層18亦具有位於開，中
閘極氧化層的形成 如第3圖所不，閘極氧化層2 2被形成於開口 2 基板10部分20上。闡炻ft儿^“ 7 閘極虱化物22偏好約1〇至50埃厚，且鉍 為偏好約1 5至2 5埃厚。 車乂 WF1内間隔物的形成 如第3圖所不，呈右笛 ,. -’弟一功函數的一個WF 1材料声 積於經刻劃的氮化声間σ士 啊竹增破沈 ^ 層開口26中，並被蝕刻而形成WF1内門 隔物24於該經刻書ij氮化#! /战”丄円間 ^ a ^ L化層18的暴露邊緣27上。WF1内間隘 物24偏妤具有約2〇〇至i2nn祕隔 μ王ιζυυ埃厚的基座宽廑？7， 好約20 0至40 0埃厚。 ！見沒」 且议為偏 F 2閘電極體的形成 户二％二所示有第二功函數的-麵材料層被、'尤 接；以及接著被平坦：（偏:夢：fF1内間隔物24鄰 )’而形成WF2閘電極體28。功曰函干機械拋先（CMP) 名詞=其係為將位於材料之f 為tF'用的半導體物理 或無能量能階所需的能^費“階的-個電子帶至真空 厚，極體28偏好具有約1_至3。。〇埃 烊且丁乂马偏好約1D00至2500埃厚
Ml内間議侧閉電極體2; 一同組成間電極。
505995 五、發明說明（5) ' W F1内間隔物2 4與W F 2閘電極體的組成 PMOS _S WF1 —— IWF2 WF1 WF2 !TaN w Ru〇2 Co !Ti Co Pt Ni_ iTa Ki T[Si2 !Mo TiSi2 丨A1 WSix ilSix i KiSix ! CoSix WN a ! TiNx 下表I說明形成PM0S與NM0S裝置用之閘電極30的該WF1 内間隔物24與WF2閘電極體28的較佳WF1/WF2材料組合。表 I說明組成閘電極30之較佳的WF1/WF2材料組合，其中更為 較佳的材料以（，，_，，）標示。PMOS WF1攔中的任何PM〇s 、，1材料叮被選擇，而與PMqs肝2搁中的任何pmqs肝2材 料結合；以及NMOS WF1攔中的任何NM0S評1材料可被選 擇而與N Μ 〇 S丨丨F 2攔中的任何n Μ 0 S F 2材料結合。 傳统技術可接著被使用於形成整合有根據本發明所製 造之閘電極30的半導體電晶體。
505995 五、發明說明（6) 閘電極30將控制短通道效應，無須形成諸如口袋植入 等特殊的植入，因為該在邊緣附近的相異功函叙將給予一 個較高的局部閥電壓。 本發明的優點包含有： 1. 其與先進的金屬閘極製程相容；以及 2. 其為無須口袋植入的較簡易製程。 雖然本發明的特定實施例已被舉例並說明，但並不希 冀本發明僅被限制於其，而應如下列申請專利範圍所定 義0
第13頁 505995 圖式簡單說明 本發明的特徵及優點將由下列配合附圖的說明而更清 楚地被瞭解，其中相同的參考數字代表相似或相當的元 件、區域與部分，以及其中： 第1圖至第4圖為示意說明本發明之較佳實施例的剖面

Claims (1)

  1. 505995
    1 一種用於形成閘電極的 a)提供一半導體基板， 部分以及經刻劃層開 劃層具有暴露的邊緣 方法，包含的步驟有： 其具有暴露出主動區中之該基板 口的一個上覆經刻劃層；該經刻 b)形成内間隔物於該經刻劃層所暴露之邊緣上之該經刻 劃層開口中之部分的經暴露基板部分的上方；該内間 隔物由一個具有第一功函數的WF1材料所組成；以及 c)形成一個經平坦化的間電極於該經刻劃薄層開口之其餘 部分中，並與該内間隔物鄰接；該閘電極由一個具有第 二功函數的W F 2材料所细士、.分&日日u ^ 7、、且成，該内間隔物與該閘電極將 形成該閘電極。 2.如申請 主動區 3·如申請 矽與氮 材料係 CoSix、 TaN、T 4.如申請 矽與氮 材料係 CoSix ^ 含 Ru02 2 ίΐ第1項之方法’其中該基板包含形成該 的淺溝渠隔離。 專利範圍第1項之古、土 ^ ^ 7 、之方法，其中该經刻劃層由氧化 化石夕組成的族群中；登掘^ μ ^ 砰甲&擇的一薄層所組成；該WF1 ㈣、及TiN的έ日游· X Ni bix u x的組群，以及該WF2材料係選自於 Ta、Mo、及A1的組群。 專利範圍第1項之太、土 # rh ^ 化石夕細成的始、方法，其中该經刻劃層由氧化 且成的族群中選擇的一薄層 :及K 有/、。。，，“二、 、及Pt的組群群；以及讎材料係選自於包 5 ·如申請專利範圍第1項之方法 其中該經刻劃層由氧化
    i號 9Π1Π538 六、申請專利範圍 曰 修正 石夕與氮化矽組成的族群 ^ m ^ ^ 材料係選自於包含有w Λ擇的一薄層所組成；該WF1 C〇Si、WN …、…“、WSix、MSix、 ^Ta； T. fTlNx的組群；以及該WF2材料係選自於包 3TaN、Tl、Ta、M〇、及A1 的組群。 如申請專利範圍第1項之f 甘士 e W & 以及該WF2材料為TaN 其中該經刻劃層由氮化 以及該WF2材料為ru〇2 包含在該内間隔物形成 ^ ,, 貝之方法，其中该經刻劃層由氮化 8 石夕所組成；該WF1材料為TiNx 如申請專利範圍第1項之方丄 矽所組成；該WF1材料為TiSis 如申請專利範圍第1項之方法‘ 牛驟々兑 ^ W. (HJ (m WJ ρχ : 刖，形成一個閘極氧化層於該經刻劃層開口中之 二，板暴露部分上方的步驟；該閘極氧化層具有約丨0至 50埃的厚度。 如申請專利範圍第1項之方法，其中該經刻劃層約1〇〇〇 至3〇 〇〇埃厚，並由氮化矽所組成；該内間隔物24具有約 200至1200埃厚的基座寬度；以及該閘電極體約至 3 0 0 0埃厚。 1〇·如申請專利範圍第1項之方法，其中該經刻劃層約1000 至30 00埃厚，並由氮化矽所組成；該内間隔物24具有約 200至400埃厚的基座寬度；以及該閘電極體約1500至 2500埃厚。 •一種用於形成閘電極的方法，包含的步驟有： a)，，一半導體基板，其具有暴露出主動區中之該基板 4刀以及經刻劃層開口的一個上覆經刻劃層；該經刻 層具有暴露的邊緣；
    505995 i號 90111538
    六、申請專利範圍 b)形成一個閘極氧化層於該被暴露的基板部分； C )形成内間隔物於該經刻劃層所暴露之邊緣上之节鋅 劃層開口中之部分的該閘極氧化層的上方；該：:： 物由一個具有第一功函數的肝1材料所組成；以及0 d)形成一個經平坦化的閘電極體於該經刻劃薄層 J餘：分中之該間極氧化層上方，並與該内；；物： 该閘電極由一個具有第二功函數的WF2材料 ，該内間隔物與該閘電極將形成該閘電極。'、 Λ申^厂專利範圍第11項之方法’其中該基板包含形成 4主動區的淺溝渠隔離。 战 13.二請專利範圍第11項之方法，其中該經刻割層由氧 wf材Λ切組成的族群中選擇的—薄層所組成；該 肝1材枓係選自於包含有w、c〇、Ni、Tisi2、、仙 x CoSl 、WN、及TiN 的 έ日魏· 包含W、Ti、、M〇U及該肝2材料係選自於 丄a ίο、及Ai的組群。 化石夕^專利範圍第11項之方法，#中該經刻劃層由氧 WF1材料W組成的族群中選擇的一薄層所組成；該 包人右1χ 、及ΤΐΝχ的組群；以及該WF2材料係選自於 巴3有Ru〇2、及pt的組群。 化石/所^s第11項之方法’其中該經刻劃層由氮 。、、、’該WF1材料為ΠΝΧ ;以及該WF2材料為TaN 16·如申請專利範圍第11項之方法，其中該經刻劃層由氮
    ΙΡ®ι im 第17頁 505995 - -塞建一 90111538 车月 日 鉻γρ 六、申請專利範圍 "―"' ~' 化矽所組成；該ffF1材料為TiSi2 ;以及該WF2材料為Ru〇 2 ° 17·、如申請專利範圍第u項之方法，其中該閘極氧化層約 為10至50埃厚；該經刻劃層約1 00 0至3000埃厚，並由氮 $石夕所組成；該内間隔物具有約2〇〇至12〇〇埃厚的基座 寬度；以及該閘電極體約1〇〇〇至3〇〇〇埃厚。 1 8 ·、如申請專利範圍第11項之方法，其中該閘極氧化層約 為15至25埃厚；該經刻劃層約1 00 0至3000埃厚，並由氮 化石夕所組成；該内間隔物具有約2〇〇至4〇〇埃厚的基座寬 度；以及該閘電極體約1 5 0 0至2 5 0 0埃厚。 1 9 · 一種用於形成閘電極的方法，包含的步驟有： a) 提供一半導體基板，其具有暴露出主動區中之該基板 部分以及經刻劃層開口的一個上覆經刻劃層；該經刻 wj層具有暴4的邊緣，該基板包含定義該主動區的淺 溝渠隔離； / b) 形成一個閘極氧化層於該被暴露的基板部分； c) 形成内間隔物於該經刻劃層所暴露之邊緣上之該經刻 劃層開口中之部分的該閘極氧化層的上方·，該内間隔 物由一個具有第一功函數的WF 1材料所組成；以及 e)形成一個經平坦化的閘電極體於該經刻劃薄層開口之 其餘部分中之該閘極氧化層上方，並與該内間隔物鄰 接；該閘電極由一個具有第二功函數的評2材料所組 成；該内間隔物與該閘電極將形成該閘電極。 2〇·如申請專利範圍第1 9項之方法，其中該經刻劃層由氧
    505995 i 號 901
    六、申請專利範圍 化矽與氮化矽組成的族 WF1材料係選自於包含中選擇的一薄層所組成；該 x、c〇Six，LW C〇、Ni、TlSl2、C 包含TaN、Ti、Ta、MX〇、、，、且群，以及該肝2材料係選自於 2 1.如申請專利範圍第1 9項之方^ ’、且^ 化石夕與氮化♦組成的族群選’-中^刻劃層由氧 WF1材料係選自於 中選。擇的-二層所組成；該 X、CoSi、WN、；5TiM 沾 Co、Nl、TlSl2、WSix、NiSi 包含杨g2、及Pt的組群組群；以及該WF2材料係選自於 22·如申請專利籠圜第iq /1 ^ 項之方法，其中該經刻劃層由氧 wn材料ϋ夕白組成^群中選擇的一薄層所組成；該 =包含有W、C〇、Ni、TiSi2HNiSi x包人τΛχ τ及^比的組群；以及該wf2材料係選自於 包含TaN、Ti、Ta、M〇、及八丨的組群。 化如石夕申利範圍第19項之方法，其中該經刻劃層由氮 化矽所組成；該wn材料為TiNx ;以及該WF2材料為TaN 24‘广中請專利範圍第19項之方法，&中該經刻割層由氮 化矽所組成；該WF1材料為TiSi2 ;以及該WF2材料為Ru〇 2 0 •如申凊專利範圍第1 9項之方法，其中該閘極氧化層約 .、、、10至50埃厚；該經刻劃層約1 00 0至3000埃厚，並由氮 化石夕所組成；該内間隔物具有約2〇〇至12〇〇埃厚的基座 寬度；以及該閘電極體約1 000至3 〇〇〇埃厚。
    第19頁 505995
    第20頁
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