502339 A7 B7 五、發明説明（） 5-1發明領域： 本發明是有關一種在矽晶圓上的毫米矽島的結構及其 製造方法，特別有關於一種在矽晶圓上之單電子電晶體的 結構及其製造方法。 5-2發明背#景： 經濟部中央標準局員工消費合作社印製 (請先閲讀背面之注意事項再填寫本頁) 單電子電晶體（Single Electron Transistor，SET)已經成 為電子技術中的重要元件，此元件是利用 Coulomb Blockade效應作操作。然而，單電子電晶體元件的操作 限制於在低於絕對溫度4K，是因為單電子電晶體的最小 電容小於100aF，這代表在低溫中的充電能量e2/(2C)遠大 於熱能。在西元1994年的IEDM Tech. Dig.期刊的第938 頁中，Y. Takajashi等人提到一個矽單電子電晶體的電容 約在2aF。在此篇文章中所介紹的矽單電子電晶體，即使 在室溫之中，依然顯現出導通震M (conductance oscillation) 的現象。因此，使用半導體技術，可在基板上製造一單電 子電晶體，於室溫中使用這個元件。在此篇論文之中’使 用氧植入隔離製程（Separation by Implanted oxygen， SIMOX)形成一逢薄砂層（Superficial Silicon layer)，單電 子電晶體元件是製造在此淺薄矽層之中。然後，作者在淺 薄矽層之中，利用半導體技術，製造—維矽線（〇ne-dimensional Silicon Wire)，此取線的的寬度約在毫米尺才 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 502339 A7 B7 五、發明説明（） 之間。 近來，利用一毫米尺才大的複晶微晶粒矽，作為浮動 閘極與元件的通道，來瞭解單電子記憶體的室溫操作。在 西元1996年的IEDM Tech. Dig.期刊的第952頁，A. Nakajima等人報導一種具有自行對準浮動閘極的單電子 記憶體，說明此種新的矽單電子記憶體元件包含一窄通道 場效電晶體（FET)，具有一個超小自行對準浮動點閘極 (Floating Dot Gate)，足以在室溫中表現出乾淨的單電子 記憶效應。在此篇文章之中，矽單電子場效電晶體記憶體 具有大約30毫米的寬度，可於室溫之下操作。 經濟部中央標準局員工消費合作社印製 (請先閱讀背面之注意事項再填寫本頁) 進行許多的努力，製造以矽為材料的單電子電晶體元 件，對單電子元件操作所需的最小尺才，決定於非人為所 能控制的製程之中，例如晶粒控制與非均勻的氧化製程， 這些過程很難決定於元件設計過程之中。在西元1996年 的IEDM Tech. Dig.的第955頁之中，L. Guo等人提出一 個製造矽單電子金屬氧化半導體記憶體（Single-Electron MOS Memory，SEMM)的過程，並測量元件的電性特性。 此元件具有毫米尺才的浮動閘極與一個窄閘極。對具有7 毫米χ7毫米面積的浮動閘極，與40毫米的控制氧化層的 元件，在給予此單電子充電電壓約為4V，電容約為4><1(Τ 2GF。矽單電子金屬氧化半導體記憶體（SEMM)元件是利用 SOI(Silicon on Insulator)技術加以製作，利用電子東微影 製程與反應性離子蝕刻製程，製造元件的通道，通道的長 度變化於25毫米到120毫米之間。 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 502339 經濟部中央標準局員工消費合作社印製 Λ 7 Β7 五、發明说明（ ） 於西元1997年的Jpn· J· Appl· Phys·的第4161頁之中， N. Yoshikawa說明在毫米尺才的粒狀微橋（Nanoscale Granular Microbridge)的單電子穿隧效應（Single-Electron-502339 A7 B7 V. Description of the invention (5) Field of the invention: The present invention relates to a structure of a millimeter silicon island on a silicon wafer and a method for manufacturing the same, and more particularly to a single electron transistor on a silicon wafer. Structure and its manufacturing method. 5-2 发明 背 # Scenery: Printed by the Consumer Cooperatives of the Central Bureau of Standards of the Ministry of Economic Affairs (please read the notes on the back before filling this page) Single Electron Transistor (SET) has become an important element in electronic technology This element is operated using the Coulomb Blockade effect. However, the operation of single-electron transistor elements is limited to 4K below the absolute temperature because the minimum capacitance of single-electron transistors is less than 100aF, which means that the charging energy e2 / (2C) at low temperatures is much larger than thermal energy. In page 938 of the 1994 IEDM Tech. Dig. Journal, Y. Takajashi et al. Mentioned that the capacitance of a silicon single electron transistor is about 2aF. The silicon single electron transistor described in this article still exhibits the phenomenon of conduction oscillation (M) even at room temperature. Therefore, using semiconductor technology, a single electron crystal can be fabricated on a substrate, and this element can be used at room temperature. In this paper, ‘the separation by implanted oxygen (SIMOX) process is used to form a thin layer of superficial silicon (semi-silicon layer). Single-electron transistor components are fabricated in this shallow silicon layer. Then, the author used semiconductor technology to fabricate a single-dimensional silicon wire in a thin layer of silicon. The width of this wire is about millimeters. The paper size applies the Chinese National Standard (CNS) A4. Specifications (210X297 mm) 502339 A7 B7 V. Description of invention (). Recently, a one-millimeter ruler of multi-crystalline microcrystalline silicon was used as a floating gate and device channel to understand the room temperature operation of a single electron memory. On page 952 of the 1996 IEDM Tech. Dig. Journal, A. Nakajima et al. Reported a single-electron memory with self-aligned floating gates, stating that this new silicon single-electron memory element contains a narrow The channel field effect transistor (FET) has an ultra-small self-aligned floating dot gate, which is sufficient to show a clean single-electron memory effect at room temperature. In this article, silicon single-electron field-effect transistor memory has a width of approximately 30 mm and can be operated at room temperature. Printed by the Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs (please read the precautions on the back before filling this page). Make many efforts to manufacture silicon single-electron transistor components, the minimum size required for single-electronic component operation. It is determined by non-artificially controllable processes, such as grain control and non-uniform oxidation processes. These processes are difficult to determine in the component design process. In IEDM Tech. Dig., P. 955, 1996, L. Guo et al. Proposed a process for manufacturing a single-electron metal oxide semiconductor memory (SEMM) and measured the electrical Sexual properties. This component has a millimeter ruler floating gate and a narrow gate. For a floating gate with a 7 mm x 7 mm area and a 40 mm control oxide layer, the single-electron charge voltage is about 4V, and the capacitance is about 4 > < 1 (T 2GF. Silicon single-electron metal oxide Semiconductor memory (SEMM) elements are manufactured using SOI (Silicon on Insulator) technology, and the electronic element lithography process and reactive ion etching process are used to fabricate the channel of the device. The length of the channel varies from 25 mm to 120 mm. This paper size applies to Chinese National Standard (CNS) A4 (210X297 mm) 502339 Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs Λ 7 Β7 V. Description of the invention () Jpn · J · Appl · Phys · 1997 On page 4161, N. Yoshikawa describes the single-electron-tunneling effect of a nanoscale Granular Microbridge at the millimeter scale (Single-Electron-
Tunneling Effect) 。 粒狀微 橋是在— 氧化製程之中製造， —薄膜在此氧化步驟之中被沉積，然後進行45度斜角的 離子蝕刻製程，在氧化製程之後，形成—微橋。 在最後這兩篇文章之中，製造單電子通道的方法是一 種非人為所能控制的方法，而且很難加以掌握。換言之’ 設計者很難設計一種良好的結構，而且很難控制通道的長 度。因此，非常需要一種簡單而穩定的製程方法，來製造 單電子電晶體。 5-3發明目的及概述： 本發明揭露一種單電子電晶體之記憶體陣列的結構及 其製造方法。首先，形成^~•契:氧化$夕層在5夕碁板之上’對 矽基板進行離子佈植製程，在矽基板中形成一多氧非結晶 區域。在矽基板的離子佈植之後，使用高溫退火製程，形 成一埋藏層，埋藏層的深度介於0.3到0.5微米之間。— 熱氧化矽層形成在矽基板之上，以減少在埋藏層之上的矽 基板厚度。移除熱氧化矽層，於矽基板的表面形成超薄氧 化矽層。然後*數個氮化矽方塊形成在超薄氧化矽層之上， 以定義獨立圖案。一複晶矽層沉積在氮化矽方塊之上，然 後進行回蝕刻處理*形成複晶矽側壁。利用熱磷酸溶液移 本紙張尺度適用中國國家標準（CNS ) Α4規格（210X297公釐） (讀先閲讀背面之注意事項再填寫本頁)Tunneling Effect). Granular micro-bridges are manufactured during the oxidation process. The thin film is deposited during this oxidation step, and then subjected to a 45-degree oblique ion etching process. After the oxidation process, micro-bridges are formed. In the last two articles, the method of making a single electron channel is a method beyond human control and it is difficult to master. In other words, it is difficult for the designer to design a good structure, and it is difficult to control the length of the channel. Therefore, there is a great need for a simple and stable process method for manufacturing single electron transistors. 5-3 Purpose and Summary of the Invention: The present invention discloses a structure of a memory array of a single electron transistor and a method for manufacturing the same. First, the formation of ^ ~ •: oxidized layer on the 5th plate is performed on the silicon substrate by an ion implantation process to form a polyoxygen amorphous region in the silicon substrate. After the ion implantation of the silicon substrate, a high temperature annealing process is used to form a buried layer with a depth between 0.3 and 0.5 microns. — A thermally oxidized silicon layer is formed on the silicon substrate to reduce the thickness of the silicon substrate over the buried layer. The thermally oxidized silicon layer is removed to form an ultra-thin silicon oxide layer on the surface of the silicon substrate. Then several silicon nitride blocks are formed on top of the ultra-thin silicon oxide layer to define independent patterns. A polycrystalline silicon layer is deposited on the silicon nitride block and then etched back * to form a polycrystalline silicon sidewall. Use hot phosphoric acid solution to transfer This paper size applies Chinese National Standard (CNS) Α4 specification (210X297 mm) (read the precautions on the back before filling in this page)
502339 經濟部中央標準局員工消費合作社印製 A7 B7 五、發明説明（） 除氮化矽方塊，以複晶矽側壁作為硬罩幕，對超薄氧化矽 層進行回蝕刻處理。複晶矽側壁與剩餘超薄氧化矽層作為 硬罩幕，定義毫米矽島的圖案。去除矽島上的超薄氧化矽 層，一超薄氮氧化矽層形成在矽島的表面之上。最後，一 n+摻雜複晶矽層沉積在埋藏層與毫米矽島的表面。 5-4圖式簡單說明： 本發明的許多發明目的與優點，將會因為參考下列的 詳細說明，變得更容易被鑑賞與瞭解，同時參酌下列的圖 式加以說明，其中： 第一圖係顯示本發明之半導體基板的剖面示意圖，解釋 墊氧化層形成在基板之上； 第二圖係顯示本發明之半導體基板之剖面示意圖，解釋 進行一全面性離子佈植製程，摻雜氧離子到基板之 中； 第三圖係顯示本發明之半導體基板的剖面示意圖，解釋 —埋藏層形成在基板之中； 第四圖係顯示本發明之半導體基板的剖面示意圖，解釋 形成一熱氧化層，在基板上形成毫米矽島； 第五圖是顯示本發明之半導體基板的剖面示意圖’解釋 熱氧化層的移除與超薄氧化層的形成； 第六圖係顯示本發明之半導體基板的剖面示意圖，解釋 氮化矽方塊形成在超薄氧化層之上； 本紙張尺度適用中國國家標準（CNS ) Α4規格（21〇Χ297公釐） (請先閱讀背面之注意事項再填寫本頁)502339 Printed by the Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs A7 B7 V. Description of the invention () In addition to the silicon nitride block, the side wall of the polycrystalline silicon is used as a hard cover to etch back the ultra-thin silicon oxide layer. The polysilicon sidewall and the remaining ultra-thin silicon oxide layer serve as a hard mask, defining the pattern of millimeter silicon islands. The ultra-thin silicon oxide layer on the silicon island is removed, and an ultra-thin silicon oxynitride layer is formed on the surface of the silicon island. Finally, an n + doped polycrystalline silicon layer is deposited on the surface of the buried layer and the millimeter silicon island. 5-4 Schematic illustrations: Many of the objects and advantages of the present invention will become easier to appreciate and understand by referring to the following detailed descriptions, while referring to the following drawings to illustrate, where: The first diagram is Shows a schematic cross-sectional view of a semiconductor substrate of the present invention, explaining that a pad oxide layer is formed on the substrate; The second figure shows a schematic cross-sectional view of a semiconductor substrate of the present invention, explaining a comprehensive ion implantation process, and doping oxygen ions into the substrate The third diagram is a schematic cross-sectional view of a semiconductor substrate of the present invention, explaining that a buried layer is formed in the substrate. The fourth diagram is a cross-sectional schematic view of a semiconductor substrate of the present invention, explaining the formation of a thermal oxide layer on the substrate. Millimeter silicon islands are formed on the top; the fifth figure is a schematic cross-sectional view showing the semiconductor substrate of the present invention, 'explaining the removal of the thermal oxide layer and the formation of the ultra-thin oxide layer; the sixth figure is a cross-sectional schematic view of the semiconductor substrate of the present invention, explaining The silicon nitride block is formed on the ultra-thin oxide layer; the paper size is applicable to China National Standard (CNS) A4 regulations (21〇Χ297 mm) (Please read the back of the precautions to fill out this page)
、1T 線 502339 A7 B7五、發明説明（） 第七圖係顯示本發明之半導體基板的剖面示意· 解釋 經濟部中央標準局員工消費合作社印製 氮化矽方塊的複晶矽側壁的形成； 第八圖係顯示本發明之半導體基板的剖面示意圖，解釋 氮化矽方塊的移除； 第九圖係顯示本發明之半導體基板的剖面示意圖，解釋 毫米矽線的形成； 第十圖係顯示本發明之半導體基板的剖面示意圖，解釋 閘極之側壁與主動區的形成； 第十—圖係顯示本發明之半導體基板的剖面示意圖，解 釋一厚氧化層形成在基板的表面* —金屬接觸形成 在厚氧化層之中；以及 第十二圖係顯示本發明之毫米矽單電子電晶體元件的俯 視示意圖。 5-5發明詳細說明： 本發明揭露一種在矽晶圓上毫微米矽島的結構及其製 造方法，製造毫微米矽島以形成單電子電晶體（Single-Electron Transistor) ， 在下面的敍 述之中 ，一種基板上的單 電子電晶體記憶體陣列（Memory Array)的結構及其製造方 法，將參考第一圖至第Η--圖，作一詳細的說明。 請參閱第十一圖，一結構製造在一半導體基板1〇〇之 上，一氧化矽層形成在基板100之上*將在下面的敘述之 中，說明這是·—^里藏層115。埋藏氧化5夕層115(Buried Oxide 6 請 龙· 閱 ik 背 面. 意 事 項1T line 502339 A7 B7 V. Description of the invention (7) The figure 7 shows a schematic cross-sectional view of the semiconductor substrate of the present invention. Explains the formation of a polycrystalline silicon sidewall printed with silicon nitride cubes by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs. Figure 8 shows a schematic cross-sectional view of the semiconductor substrate of the present invention, explaining the removal of silicon nitride blocks; Figure 9 shows a schematic cross-sectional view of the semiconductor substrate of the present invention, explaining the formation of millimeter silicon lines; Figure 10 shows the present invention A schematic cross-sectional view of a semiconductor substrate explaining the formation of the sidewalls of the gate electrode and the active region. The tenth-picture is a schematic cross-sectional view of the semiconductor substrate of the present invention, explaining a thick oxide layer formed on the surface of the substrate *-a metal contact is formed in the thick Among the oxide layers; and the twelfth figure is a schematic plan view showing a millimeter silicon single electron transistor device according to the present invention. 5-5 Detailed description of the invention: The present invention discloses a structure of nanometer silicon islands on a silicon wafer and a method for manufacturing the same, manufacturing nanometer silicon islands to form a single-electron transistor (Single-Electron Transistor), described below. In the structure of a single-electron transistor memory array on a substrate and a method for manufacturing the same, a detailed description will be made with reference to the first to the third drawings. Referring to the eleventh figure, a structure is fabricated on a semiconductor substrate 100, and a silicon oxide layer is formed on the substrate 100. * This will be described in the following description. Buried Oxide 6 (Buried Oxide 6) Please read the back of ik.
裝 訂 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 502339 修正本方年/神日 五、發明說明（) layer)是當作絕緣層，數個單電子電晶體製造在埋藏氧化石夕 層115之上，埋藏氧化取層115的厚度是介於〇.3到0·5 微米之間。然後，數個矽線（Silicon Wire) 135被製造在埋 藏氧化矽層11 5之上，數個砂線13 5之間是互相分開的。 熟知該項技術者必定瞭解’砂線13 5具有足夠贺的寬度’ 可使單個電子穿隱而過。氮氧化砂層140覆蓋在砂線135 的表面，作為矽線135的絕緣。在砂線135形成之後’一 複晶矽層145形成在氮氧化矽層（Oxynitride layer)145與碁 板100之上，並連接—控制單電子電晶體的鬧極。請參閲 第十二圖，每一個矽線135具有兩個端點，一端點接往一 源極10，另—個端點接往—汲極20，因此，—單電子電晶 體記憶體陣列形成在基板100之上’此陣列是由數條5夕線 .1 35所組成，複晶矽層145連接閘極、源極1 〇與设極20。 請參閱第一圖，提供單晶P型具有<100>晶軸方向的基 板100，一堅氧化層105形成在基板1〇〇之上’所用的技 術為在氧氣中的熱氧化製程，墊氧化層105的厚度介於1⑽ 到500埃之間。 請參閱第二圖，將氧離子以高劑量植入於基板100之 中，在基板 1〇〇之中形成—多氧非結晶區域（〇xygenThe size of the bound paper is in accordance with the Chinese National Standard (CNS) A4 specification (210X297 mm) 502339 Amendments to this year / God's Day V. Description of the invention () layer) is used as an insulating layer, and several single-electron crystals are manufactured in buried oxidation Above the Shixi layer 115, the thickness of the buried oxide layer 115 is between 0.3 and 0.5 micrometers. Then, several silicon wires 135 are fabricated on the buried silicon oxide layer 115, and the several sand wires 13 5 are separated from each other. Those skilled in the art must understand that 'sand line 13 5 has sufficient width' to allow a single electron to pass through. The oxynitride sand layer 140 covers the surface of the sand wire 135 and serves as insulation of the silicon wire 135. After the formation of the sand line 135, a 'multi-crystalline silicon layer 145 is formed on the oxynitride layer 145 and the ytterbium plate 100, and is connected to control the anode of the single electron transistor. Please refer to the twelfth figure, each silicon wire 135 has two terminals, one terminal is connected to a source 10, and the other terminal is connected to a drain 20, therefore, a single electron transistor memory array Formed on the substrate 100 'This array is composed of a plurality of lines 55. A polycrystalline silicon layer 145 is connected to the gate, the source 10 and the set 20. Please refer to the first figure, to provide a single crystal P-type substrate 100 with <100> crystal axis direction, and a solid oxide layer 105 is formed on the substrate 100. The technology used is a thermal oxidation process in oxygen. The thickness of the oxide layer 105 is between 1 ⑽ and 500 Angstroms. Referring to the second figure, oxygen ions are implanted into the substrate 100 at a high dose to form a polyoxygen amorphous region (〇xygen) in the substrate 100.
Amorphized region) 110,所用的高劑量約在 5χ1〇ι6 到 5x10 離子/cm2之間，佈植能量介於1〇〇到3 00KeV之間。 接著，請參閱第三圖，利用高溫熱退火製程。將多氧 非結晶區1 10轉換成一埋藏氧化矽層（Buried Oxide layer) ’ 在基板之中形成一埋藏層115，退火製程是進行於N2或 本紙張瓦度適用中國國家標準（CNS)A4規格（210 X 297公t ) I——ί!----ΛΨ.----II 丨訂------ — Is— (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印制衣 502339 A7 B7 經濟部中央標準局員工消費合作社印製 五、發明説明（） N2/02的混合氣體之中，需要足夠的反應時間（3到5小時 之間），與高溫退火溫度（1050到1350°C之間）。一般來 說，埋藏氧化層115的深度約在0.3到0.5微米之間，形 成埋藏氧化層 115的技術，是被稱為”氧植入隔離技 術’’（Separation by Implanted oxygen，SIMOX) 〇 請參閱第四圖，使用熱氧化製程，在基板100之上形 成一熱氧化矽 116，此熱氧化製程可減少在熱氧化矽116 與埋藏氧化層115之間的單晶矽區域，在熱氧化矽116與 埋藏氧化矽層115之間的矽基板100的厚度，約為毫米尺 才之間，這是因為在埋藏氧化層115上的矽基板100轉換 成熱氧化層116。 請參閱第五圖，移除熱氧化層116，在基板100上形成 —超薄氧化矽層 120。普遍來說，移除熱氧化矽層 116的 技術是使用 B0E 溶液（Buffer Oxide Etching Solution)，或 者是稀釋氫氟酸（Diluted HF Solution)。使用熱氧化製程， 在基板100之上重新生長超薄氧化矽層120，厚度約在20 到200之間。 請參閱第六圖，沉積一氮化矽層在超薄氧化矽層 120 之上，然後對此氮化矽層進行回蝕刻處理，形成氮化矽方 塊125，氮化矽方塊125的厚度約在100到1000埃之間， 氮化矽方塊125在基板100之上形成一氮化矽圖案。在一 較佳實施例之中，氮化矽方塊125的沉積方法是使用低壓 化學氣相沉積製程（LPCVD)，或者是電漿增強化學氣相沉 積製程（PECVD)。 (請先閱讀背面之注意事項再填寫本頁) 衣· 訂 •齡丨 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 經濟部中央標準局員工消費合作社印製 502339 A 7 B7 五、發明説明（） 請參閱第七圖，一複晶矽層沉積在氮化矽方塊125之 上，然後進行回蝕刻製程，形成氮化矽方塊125的複晶矽 側壁130。複晶矽層的沉積方法是使用低壓化學氣相沉積 製程，工作壓力介於50到600mtorr之間，工作溫度介於400 到600 °C之間，複晶矽層的厚度約在50到500埃之間。 請參閱第八圖，移去氮化矽層125，在基板100上形成 矽島。移去氮化矽層 125的方法是使用熱磷酸（Hot Phosphoric Acid)，然後使用複晶矽側壁130作為硬罩幕 (Hard Mask)，對超薄氧化層120進行回蝕刻製程。複晶矽 側壁130與剩餘超薄氧化矽薄膜被用作硬罩幕，在基板100 之上形成矽島。 請參閱第九圖，回蝕刻矽基板100,使用複晶矽側壁130 與超薄氧化矽層 120作為硬罩幕，形成毫米矽島。毫米矽 線135形成埋藏氧化矽層115之上。在一較佳實施例之中， 進行一乾蝕刻製程，例如電漿蝕刻製程，在基板1〇〇之上 形成矽線135，其中矽線135的寬度約在40到1000埃之 間。 請參閱第十圖，在形成取線13 5之後，一超薄氣氧化 5夕層140成長在毫米砂島之上，使用N20或是NO氣體* 超薄氮氧化矽層140的厚度約在10到100埃之間。 請參閱第十一圖，沉積一n+複晶矽層145作為單電子 穿隧（Single Electron Tunneling，SET)元件的間極材料。通 常形成n+複晶矽層145是使用同步摻雜複晶矽材料，沈積 方法是使用化學氣相沉積製程，加入磷氣體或砷氣體到化 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） (請先閎讀背面之注意事項再填寫本頁) ·裝. 訂 502339 A7 B7 五、發明説明（） 學氣相沉積反應氣體之中，作為摻雜雜質源。n+複晶矽層 145的厚度介於200到2000埃之間。 請再度參閱第十一圖，顯示單電子電晶體記憶體陣列 的剖面圖，埋藏氧化層115形成在基板100之上，複數個 矽線135排列在埋藏氧化矽層115之上，並且被氮氧化矽 層 140所覆蓋。在形成單電子電晶體之後，複晶矽層 145 覆蓋在氮氧化矽層140與基板100之上。 在上述製程之後，數個毫米取單電子穿隨（Nanometer SET)元件被製造在基板100之上，這些元件形成一個記 憶體陣列。請參閱第十二圖，顯示記憶體陣列的俯視圖， 而第Η--圖是第十二圖沿著ΑΑ’方向的剖面示意圖。於此 圖之中，記憶體陣列被製造在埋藏氧化矽層 115之上，η+ 摻雜複晶矽層145是一條在埋藏氧化矽層115之上的寬帶， 矽線135跨越複晶矽層145，形成單電子電晶體（SET)。在 圖式之中，虛線顯示出在矽線135之上的氮氧化矽層140。 矽線135的兩個端點接往源極10與汲極20，而且* n+摻 雜複晶矽層145接往一閘極30。使用源極10、汲極20與 閘極30控制記憶體陣列。在本發明之中，製造一連串的單 電子電晶體，毫米單電子電晶體被製造在基板100之中。 本發明以較佳實施例說明如上，而熟悉此領域技藝者* 在不脫離本發明之精神範圍内，當可作些許更動潤飾，其 專利保護範圍更當視後附之申請專利範圍及其等同領域而 定。 10 本紙張又度適用中國國家標準（CNS〉A4規格（210X297公釐） 請 先 閱 讀 背 ιδ 之 注 意 項Amorphized region) 110. The high dose used is between about 5 × 10 6 and 5 × 10 ions / cm 2, and the implantation energy is between 100 and 300 KeV. Next, referring to the third figure, a high temperature thermal annealing process is used. Converting the polyoxygen amorphous region 1 10 into a buried oxide layer (Buried Oxide layer) 'A buried layer 115 is formed in the substrate, and the annealing process is performed on N2 or the paper wattage. The Chinese National Standard (CNS) A4 specification is applicable. (210 X 297 public t) I——ί! ---- ΛΨ .---- II 丨 Order ------ — Is— (Please read the notes on the back before filling this page) Wisdom of the Ministry of Economic Affairs Printed by the Consumer Cooperative of the Property Bureau 502339 A7 B7 Printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs V. Invention Description () In the mixed gas of N2 / 02, sufficient reaction time (between 3 and 5 hours) is required, And high temperature annealing temperature (between 1050 and 1350 ° C). Generally, the depth of the buried oxide layer 115 is between 0.3 and 0.5 micrometers. The technology for forming the buried oxide layer 115 is called "Separation by Implanted oxygen (SIMOX)." See also In the fourth figure, a thermal oxidation process is used to form a thermal silicon oxide 116 on the substrate 100. This thermal oxidation process can reduce the area of single crystal silicon between the thermal silicon oxide 116 and the buried oxide layer 115. The thickness of the silicon substrate 100 between the buried silicon oxide layer 115 and the buried silicon oxide layer 115 is about a millimeter. This is because the silicon substrate 100 on the buried oxide layer 115 is converted into a thermal oxide layer 116. Please refer to the fifth figure. In addition to the thermal oxidation layer 116, an ultra-thin silicon oxide layer 120 is formed on the substrate 100. Generally, the technology for removing the thermal silicon oxide layer 116 is to use a BOE solution (Buffer Oxide Etching Solution), or to dilute hydrofluoric acid ( Diluted HF Solution). Using a thermal oxidation process, the ultra-thin silicon oxide layer 120 is re-grown on the substrate 100, with a thickness of about 20 to 200. See Figure 6, depositing a silicon nitride layer on the ultra-thin silicon oxide. Layer 120 Then, the silicon nitride layer is etched back to form a silicon nitride block 125. The thickness of the silicon nitride block 125 is about 100 to 1000 angstroms. The silicon nitride block 125 is formed on the substrate 100. Silicon nitride pattern. In a preferred embodiment, the silicon nitride block 125 is deposited using a low pressure chemical vapor deposition process (LPCVD) or a plasma enhanced chemical vapor deposition process (PECVD). (Please Please read the notes on the back before filling this page) Clothing, order and age 丨 This paper size applies to Chinese National Standard (CNS) A4 (210X297 mm) Printed by the Staff Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 502339 A 7 B7 V. Description of the Invention () Please refer to the seventh figure, a polycrystalline silicon layer is deposited on the silicon nitride block 125, and then an etch-back process is performed to form the polycrystalline silicon sidewall 130 of the silicon nitride block 125. The deposition of the polycrystalline silicon layer The method is to use a low-pressure chemical vapor deposition process with a working pressure between 50 and 600 mtorr, a working temperature between 400 and 600 ° C, and a thickness of the polycrystalline silicon layer between about 50 and 500 Angstroms. Eight figures, nitrogen removed The silicon layer 125 forms a silicon island on the substrate 100. The method for removing the silicon nitride layer 125 is to use hot phosphoric acid, and then use the polysilicon sidewall 130 as a hard mask, for ultra-thin The oxide layer 120 is etched back. The polycrystalline silicon sidewall 130 and the remaining ultra-thin silicon oxide film are used as a hard mask to form a silicon island on the substrate 100. Referring to the ninth figure, the silicon substrate 100 is etched back, and the polycrystalline silicon sidewall 130 and the ultra-thin silicon oxide layer 120 are used as a hard mask to form a millimeter silicon island. The millimeter silicon line 135 forms a buried silicon oxide layer 115. In a preferred embodiment, a dry etching process, such as a plasma etching process, is performed to form a silicon line 135 on the substrate 100, wherein the width of the silicon line 135 is between about 40 and 1000 angstroms. Please refer to the tenth figure. After forming the line 13 5, an ultra-thin gas oxidation layer 140 grows on the millimeter sand island. Use N20 or NO gas. The thickness of the ultra-thin silicon oxynitride layer 140 is about 10 To 100 angstroms. Referring to the eleventh figure, an n + polycrystalline silicon layer 145 is deposited as an interelectrode material of a single electron tunneling (SET) device. Generally, the n + complex silicon layer 145 is formed by using a synchronously doped complex silicon material. The deposition method is a chemical vapor deposition process. Phosphorus or arsenic gas is added to the paper. (Mm) (Please read the precautions on the reverse side before filling out this page) · Binding. Order 502339 A7 B7 V. Description of the invention () Learn the vapor deposition reaction gas as a source of doping impurities. The thickness of the n + complex silicon layer 145 is between 200 and 2000 angstroms. Please refer to FIG. 11 again, showing a cross-sectional view of a single electron transistor memory array. A buried oxide layer 115 is formed on the substrate 100. A plurality of silicon wires 135 are arranged on the buried silicon oxide layer 115 and are oxidized by nitrogen. Covered by a silicon layer 140. After the single-electron transistor is formed, the polycrystalline silicon layer 145 covers the silicon oxynitride layer 140 and the substrate 100. After the above process, several millimeters of single electron passing (Nanometer SET) elements are fabricated on the substrate 100, and these elements form a memory array. Please refer to the twelfth figure, which shows a top view of the memory array, and the twenty-first figure is a schematic cross-sectional view of the twelfth figure along the AA ′ direction. In this figure, the memory array is fabricated on the buried silicon oxide layer 115. The η + doped polycrystalline silicon layer 145 is a wide band over the buried silicon oxide layer 115. The silicon line 135 crosses the polycrystalline silicon layer. 145. A single electron transistor (SET) is formed. In the figure, the dashed line shows a silicon oxynitride layer 140 over the silicon line 135. The two ends of the silicon line 135 are connected to the source 10 and the drain 20, and the * n + doped polycrystalline silicon layer 145 is connected to a gate 30. The source 10, the drain 20, and the gate 30 are used to control the memory array. In the present invention, a series of single electron transistors are manufactured, and millimeter single electron transistors are manufactured in the substrate 100. The present invention has been described above with reference to the preferred embodiments, and those skilled in the art * can make some minor modifications without departing from the spirit of the present invention, and the scope of patent protection should be regarded as the scope of the attached patent application and its equivalent. Field-specific. 10 This paper is again applicable to the Chinese national standard (CNS> A4 size (210X297 mm). Please read the note on the back of δ
經濟部中央標準局員工消費合作社印製Printed by the Consumer Cooperatives of the Central Bureau of Standards of the Ministry of Economic Affairs